Reset is ignored

[rhinton]

I'm loving the AXI4 VIP in this repo. I'm using Axi4/src/Axi4MemoryVTI.vhd. I finally tracked down an Alert output to the fact that my design is issuing read and write transactions while the nReset port is asserted (low). And I can see in the debug transcript that Axi4MemoryVti is queueing these transactions. Also, a simple text search shows that nReset isn't used anywhere in Axi4MemoryVti.

Unfortunately, I can't submit a test bench showing this problem. Hopefully my description above is sufficient.

[Paebbels]

What would be a definition of a reset on a memory? Memory arrays can't be reset in ASIC and FPGAs. At maximum, you could reset a potential state in reader and writer logics.

[rhinton]

Good point. I don't care what happens in the storage. Instead, I need all the internal transaction FIFOs (write address channel, write data, read address, read data) cleared out. Also any transactions issued during the reset should be ignored. (Take "ready" low?)

The behavior I'm seeing is that I push in a write address, but the "Memory write" transaction actually happens at a different address. This happens because I pushed one or two extra write address transactions before / during the reset.