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Merge branch 'fix_axi_outstanding_counter_1.8.9-rc'
1 parent 257fd5d commit 1afa224

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25 files changed

+289
-275
lines changed

25 files changed

+289
-275
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‎examples/simulation_verilator/test_simulation_verilator.py

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -657,7 +657,7 @@
657657
assign myaxi_arprot = 0;
658658
assign myaxi_arqos = 0;
659659
assign myaxi_aruser = 0;
660-
reg [32-1:0] outstanding_wreq_count_0;
660+
reg [3-1:0] outstanding_wcount_0;
661661
reg _myaxi_read_start;
662662
reg [8-1:0] _myaxi_read_op_sel;
663663
reg [32-1:0] _myaxi_read_local_addr;
@@ -801,7 +801,7 @@
801801
wire [32-1:0] _dataflow__variable_odata_2;
802802
wire _dataflow__variable_ovalid_2;
803803
wire _dataflow__variable_oready_2;
804-
assign _dataflow__variable_oready_2 = (_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_37 > 0) && (myaxi_wready || !myaxi_wvalid));
804+
assign _dataflow__variable_oready_2 = (_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_37 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid));
805805
reg _myaxi_cond_2_1;
806806
assign _myaxi_write_data_done = (last_38 && myaxi_wvalid && myaxi_wready)? 1 : 0;
807807
reg axim_flag_39;
@@ -1007,7 +1007,7 @@
10071007
10081008
always @(posedge CLK) begin
10091009
if(RST) begin
1010-
outstanding_wreq_count_0 <= 0;
1010+
outstanding_wcount_0 <= 0;
10111011
_myaxi_read_start <= 0;
10121012
_myaxi_write_start <= 0;
10131013
_myaxi_ram_a_0_read_start <= 0;
@@ -1074,11 +1074,11 @@
10741074
myaxi_wlast <= 0;
10751075
last_38 <= 0;
10761076
end
1077-
if(myaxi_wlast && myaxi_wvalid && myaxi_wready && !(myaxi_bvalid && myaxi_bready)) begin
1078-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 + 1;
1077+
if(myaxi_wlast && myaxi_wvalid && myaxi_wready && !(myaxi_bvalid && myaxi_bready) && (outstanding_wcount_0 < 7)) begin
1078+
outstanding_wcount_0 <= outstanding_wcount_0 + 1;
10791079
end
1080-
if(!(myaxi_wlast && myaxi_wvalid && myaxi_wready) && (myaxi_bvalid && myaxi_bready) && (outstanding_wreq_count_0 > 0)) begin
1081-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 - 1;
1080+
if(!(myaxi_wlast && myaxi_wvalid && myaxi_wready) && (myaxi_bvalid && myaxi_bready) && (outstanding_wcount_0 > 0)) begin
1081+
outstanding_wcount_0 <= outstanding_wcount_0 - 1;
10821082
end
10831083
_myaxi_read_start <= 0;
10841084
_myaxi_write_start <= 0;
@@ -1171,14 +1171,14 @@
11711171
if(myaxi_awvalid && !myaxi_awready) begin
11721172
myaxi_awvalid <= myaxi_awvalid;
11731173
end
1174-
if(_dataflow__variable_ovalid_2 && ((_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_37 > 0) && (myaxi_wready || !myaxi_wvalid))) && ((counter_37 > 0) && (myaxi_wready || !myaxi_wvalid) && (counter_37 > 0))) begin
1174+
if(_dataflow__variable_ovalid_2 && ((_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_37 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid))) && ((counter_37 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid) && (counter_37 > 0))) begin
11751175
myaxi_wdata <= _dataflow__variable_odata_2;
11761176
myaxi_wvalid <= 1;
11771177
myaxi_wlast <= 0;
11781178
myaxi_wstrb <= { 4{ 1'd1 } };
11791179
counter_37 <= counter_37 - 1;
11801180
end
1181-
if(_dataflow__variable_ovalid_2 && ((_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_37 > 0) && (myaxi_wready || !myaxi_wvalid))) && ((counter_37 > 0) && (myaxi_wready || !myaxi_wvalid) && (counter_37 > 0)) && (counter_37 == 1)) begin
1181+
if(_dataflow__variable_ovalid_2 && ((_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_37 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid))) && ((counter_37 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid) && (counter_37 > 0)) && (counter_37 == 1)) begin
11821182
myaxi_wlast <= 1;
11831183
last_38 <= 1;
11841184
end
@@ -1507,7 +1507,7 @@
15071507
th_matmul <= th_matmul_32;
15081508
end
15091509
th_matmul_32: begin
1510-
if(_myaxi_write_idle && (outstanding_wreq_count_0 == 0)) begin
1510+
if(_myaxi_write_idle && (outstanding_wcount_0 == 0)) begin
15111511
th_matmul <= th_matmul_33;
15121512
end
15131513
end

‎examples/thread_add_ipxact/test_thread_add_ipxact.py

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@
5555
assign _saxi_bready = 1;
5656
assign _saxi_arcache = 3;
5757
assign _saxi_arprot = 0;
58-
reg [32-1:0] outstanding_wreq_count_0;
58+
reg [3-1:0] outstanding_wcount_0;
5959
wire [32-1:0] _tmp_1;
6060
assign _tmp_1 = _saxi_awaddr;
6161
@@ -234,7 +234,7 @@
234234
_saxi_wvalid = 0;
235235
_saxi_araddr = 0;
236236
_saxi_arvalid = 0;
237-
outstanding_wreq_count_0 = 0;
237+
outstanding_wcount_0 = 0;
238238
counter = 0;
239239
th_ctrl = th_ctrl_init;
240240
_th_ctrl_i_3 = 0;
@@ -270,7 +270,7 @@
270270
271271
always @(posedge CLK) begin
272272
if(RST) begin
273-
outstanding_wreq_count_0 <= 0;
273+
outstanding_wcount_0 <= 0;
274274
_saxi_awaddr <= 0;
275275
_saxi_awvalid <= 0;
276276
__saxi_cond_0_1 <= 0;
@@ -315,11 +315,11 @@
315315
if(__saxi_cond_8_1) begin
316316
_saxi_arvalid <= 0;
317317
end
318-
if(_saxi_wvalid && _saxi_wready && !(_saxi_bvalid && _saxi_bready)) begin
319-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 + 1;
318+
if(_saxi_wvalid && _saxi_wready && !(_saxi_bvalid && _saxi_bready) && (outstanding_wcount_0 < 7)) begin
319+
outstanding_wcount_0 <= outstanding_wcount_0 + 1;
320320
end
321-
if(!(_saxi_wvalid && _saxi_wready) && (_saxi_bvalid && _saxi_bready) && (outstanding_wreq_count_0 > 0)) begin
322-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 - 1;
321+
if(!(_saxi_wvalid && _saxi_wready) && (_saxi_bvalid && _saxi_bready) && (outstanding_wcount_0 > 0)) begin
322+
outstanding_wcount_0 <= outstanding_wcount_0 - 1;
323323
end
324324
if((th_ctrl == 7) && (_saxi_awready || !_saxi_awvalid)) begin
325325
_saxi_awaddr <= _th_ctrl_awaddr_4;
@@ -329,7 +329,7 @@
329329
if(_saxi_awvalid && !_saxi_awready) begin
330330
_saxi_awvalid <= _saxi_awvalid;
331331
end
332-
if((th_ctrl == 8) && (_saxi_wready || !_saxi_wvalid)) begin
332+
if((th_ctrl == 8) && ((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
333333
_saxi_wdata <= _th_ctrl_a_5;
334334
_saxi_wvalid <= 1;
335335
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -346,7 +346,7 @@
346346
if(_saxi_awvalid && !_saxi_awready) begin
347347
_saxi_awvalid <= _saxi_awvalid;
348348
end
349-
if((th_ctrl == 13) && (_saxi_wready || !_saxi_wvalid)) begin
349+
if((th_ctrl == 13) && ((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
350350
_saxi_wdata <= _th_ctrl_b_6;
351351
_saxi_wvalid <= 1;
352352
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -363,7 +363,7 @@
363363
if(_saxi_awvalid && !_saxi_awready) begin
364364
_saxi_awvalid <= _saxi_awvalid;
365365
end
366-
if((th_ctrl == 18) && (_saxi_wready || !_saxi_wvalid)) begin
366+
if((th_ctrl == 18) && ((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
367367
_saxi_wdata <= 1;
368368
_saxi_wvalid <= 1;
369369
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -500,7 +500,7 @@
500500
end
501501
end
502502
th_ctrl_8: begin
503-
if(_saxi_wready || !_saxi_wvalid) begin
503+
if((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
504504
th_ctrl <= th_ctrl_9;
505505
end
506506
end
@@ -522,7 +522,7 @@
522522
end
523523
end
524524
th_ctrl_13: begin
525-
if(_saxi_wready || !_saxi_wvalid) begin
525+
if((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
526526
th_ctrl <= th_ctrl_14;
527527
end
528528
end
@@ -544,7 +544,7 @@
544544
end
545545
end
546546
th_ctrl_18: begin
547-
if(_saxi_wready || !_saxi_wvalid) begin
547+
if((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
548548
th_ctrl <= th_ctrl_19;
549549
end
550550
end

‎examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,7 @@
300300
assign _saxi_bready = 1;
301301
assign _saxi_arcache = 3;
302302
assign _saxi_arprot = 0;
303-
reg [32-1:0] outstanding_wreq_count_9;
303+
reg [3-1:0] outstanding_wcount_9;
304304
wire [32-1:0] _tmp_10;
305305
assign _tmp_10 = _saxi_awaddr;
306306
@@ -467,7 +467,7 @@
467467
_saxi_wvalid = 0;
468468
_saxi_araddr = 0;
469469
_saxi_arvalid = 0;
470-
outstanding_wreq_count_9 = 0;
470+
outstanding_wcount_9 = 0;
471471
counter = 0;
472472
th_ctrl = th_ctrl_init;
473473
_th_ctrl_i_11 = 0;
@@ -755,7 +755,7 @@
755755
756756
always @(posedge uut_CLK) begin
757757
if(uut_RST) begin
758-
outstanding_wreq_count_9 <= 0;
758+
outstanding_wcount_9 <= 0;
759759
_saxi_awaddr <= 0;
760760
_saxi_awvalid <= 0;
761761
__saxi_cond_0_1 <= 0;
@@ -804,11 +804,11 @@
804804
if(__saxi_cond_9_1) begin
805805
_saxi_arvalid <= 0;
806806
end
807-
if(_saxi_wvalid && _saxi_wready && !(_saxi_bvalid && _saxi_bready)) begin
808-
outstanding_wreq_count_9 <= outstanding_wreq_count_9 + 1;
807+
if(_saxi_wvalid && _saxi_wready && !(_saxi_bvalid && _saxi_bready) && (outstanding_wcount_9 < 7)) begin
808+
outstanding_wcount_9 <= outstanding_wcount_9 + 1;
809809
end
810-
if(!(_saxi_wvalid && _saxi_wready) && (_saxi_bvalid && _saxi_bready) && (outstanding_wreq_count_9 > 0)) begin
811-
outstanding_wreq_count_9 <= outstanding_wreq_count_9 - 1;
810+
if(!(_saxi_wvalid && _saxi_wready) && (_saxi_bvalid && _saxi_bready) && (outstanding_wcount_9 > 0)) begin
811+
outstanding_wcount_9 <= outstanding_wcount_9 - 1;
812812
end
813813
if((th_ctrl == 6) && (_saxi_awready || !_saxi_awvalid)) begin
814814
_saxi_awaddr <= _th_ctrl_awaddr_12;
@@ -818,7 +818,7 @@
818818
if(_saxi_awvalid && !_saxi_awready) begin
819819
_saxi_awvalid <= _saxi_awvalid;
820820
end
821-
if((th_ctrl == 7) && (_saxi_wready || !_saxi_wvalid)) begin
821+
if((th_ctrl == 7) && ((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
822822
_saxi_wdata <= 4096;
823823
_saxi_wvalid <= 1;
824824
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -835,7 +835,7 @@
835835
if(_saxi_awvalid && !_saxi_awready) begin
836836
_saxi_awvalid <= _saxi_awvalid;
837837
end
838-
if((th_ctrl == 12) && (_saxi_wready || !_saxi_wvalid)) begin
838+
if((th_ctrl == 12) && ((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
839839
_saxi_wdata <= _th_ctrl_src_offset_13;
840840
_saxi_wvalid <= 1;
841841
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -852,7 +852,7 @@
852852
if(_saxi_awvalid && !_saxi_awready) begin
853853
_saxi_awvalid <= _saxi_awvalid;
854854
end
855-
if((th_ctrl == 17) && (_saxi_wready || !_saxi_wvalid)) begin
855+
if((th_ctrl == 17) && ((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
856856
_saxi_wdata <= _th_ctrl_dst_offset_14;
857857
_saxi_wvalid <= 1;
858858
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -869,7 +869,7 @@
869869
if(_saxi_awvalid && !_saxi_awready) begin
870870
_saxi_awvalid <= _saxi_awvalid;
871871
end
872-
if((th_ctrl == 22) && (_saxi_wready || !_saxi_wvalid)) begin
872+
if((th_ctrl == 22) && ((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
873873
_saxi_wdata <= 1;
874874
_saxi_wvalid <= 1;
875875
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -991,7 +991,7 @@
991991
end
992992
end
993993
th_ctrl_7: begin
994-
if(_saxi_wready || !_saxi_wvalid) begin
994+
if((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
995995
th_ctrl <= th_ctrl_8;
996996
end
997997
end
@@ -1013,7 +1013,7 @@
10131013
end
10141014
end
10151015
th_ctrl_12: begin
1016-
if(_saxi_wready || !_saxi_wvalid) begin
1016+
if((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
10171017
th_ctrl <= th_ctrl_13;
10181018
end
10191019
end
@@ -1035,7 +1035,7 @@
10351035
end
10361036
end
10371037
th_ctrl_17: begin
1038-
if(_saxi_wready || !_saxi_wvalid) begin
1038+
if((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
10391039
th_ctrl <= th_ctrl_18;
10401040
end
10411041
end
@@ -1057,7 +1057,7 @@
10571057
end
10581058
end
10591059
th_ctrl_22: begin
1060-
if(_saxi_wready || !_saxi_wvalid) begin
1060+
if((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
10611061
th_ctrl <= th_ctrl_23;
10621062
end
10631063
end
@@ -1229,7 +1229,7 @@
12291229
assign maxi_arprot = 0;
12301230
assign maxi_arqos = 0;
12311231
assign maxi_aruser = 0;
1232-
reg [32-1:0] outstanding_wreq_count_0;
1232+
reg [3-1:0] outstanding_wcount_0;
12331233
reg _maxi_read_start;
12341234
reg [8-1:0] _maxi_read_op_sel;
12351235
reg [32-1:0] _maxi_read_local_addr;
@@ -1411,7 +1411,7 @@
14111411
wire [32-1:0] _dataflow__variable_odata_1;
14121412
wire _dataflow__variable_ovalid_1;
14131413
wire _dataflow__variable_oready_1;
1414-
assign _dataflow__variable_oready_1 = (_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_32 > 0) && (maxi_wready || !maxi_wvalid));
1414+
assign _dataflow__variable_oready_1 = (_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_32 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid));
14151415
reg _maxi_cond_2_1;
14161416
assign _maxi_write_data_done = (last_33 && maxi_wvalid && maxi_wready)? 1 : 0;
14171417
reg axim_flag_34;
@@ -1491,7 +1491,7 @@
14911491
14921492
always @(posedge CLK) begin
14931493
if(RST) begin
1494-
outstanding_wreq_count_0 <= 0;
1494+
outstanding_wcount_0 <= 0;
14951495
_maxi_read_start <= 0;
14961496
_maxi_write_start <= 0;
14971497
_maxi_ram_a_0_read_start <= 0;
@@ -1546,11 +1546,11 @@
15461546
maxi_wlast <= 0;
15471547
last_33 <= 0;
15481548
end
1549-
if(maxi_wlast && maxi_wvalid && maxi_wready && !(maxi_bvalid && maxi_bready)) begin
1550-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 + 1;
1549+
if(maxi_wlast && maxi_wvalid && maxi_wready && !(maxi_bvalid && maxi_bready) && (outstanding_wcount_0 < 7)) begin
1550+
outstanding_wcount_0 <= outstanding_wcount_0 + 1;
15511551
end
1552-
if(!(maxi_wlast && maxi_wvalid && maxi_wready) && (maxi_bvalid && maxi_bready) && (outstanding_wreq_count_0 > 0)) begin
1553-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 - 1;
1552+
if(!(maxi_wlast && maxi_wvalid && maxi_wready) && (maxi_bvalid && maxi_bready) && (outstanding_wcount_0 > 0)) begin
1553+
outstanding_wcount_0 <= outstanding_wcount_0 - 1;
15541554
end
15551555
_maxi_read_start <= 0;
15561556
_maxi_write_start <= 0;
@@ -1623,14 +1623,14 @@
16231623
if(maxi_awvalid && !maxi_awready) begin
16241624
maxi_awvalid <= maxi_awvalid;
16251625
end
1626-
if(_dataflow__variable_ovalid_1 && ((_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_32 > 0) && (maxi_wready || !maxi_wvalid))) && ((counter_32 > 0) && (maxi_wready || !maxi_wvalid) && (counter_32 > 0))) begin
1626+
if(_dataflow__variable_ovalid_1 && ((_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_32 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid))) && ((counter_32 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid) && (counter_32 > 0))) begin
16271627
maxi_wdata <= _dataflow__variable_odata_1;
16281628
maxi_wvalid <= 1;
16291629
maxi_wlast <= 0;
16301630
maxi_wstrb <= { 4{ 1'd1 } };
16311631
counter_32 <= counter_32 - 1;
16321632
end
1633-
if(_dataflow__variable_ovalid_1 && ((_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_32 > 0) && (maxi_wready || !maxi_wvalid))) && ((counter_32 > 0) && (maxi_wready || !maxi_wvalid) && (counter_32 > 0)) && (counter_32 == 1)) begin
1633+
if(_dataflow__variable_ovalid_1 && ((_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_32 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid))) && ((counter_32 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid) && (counter_32 > 0)) && (counter_32 == 1)) begin
16341634
maxi_wlast <= 1;
16351635
last_33 <= 1;
16361636
end
@@ -2045,7 +2045,7 @@
20452045
th_memcpy <= th_memcpy_23;
20462046
end
20472047
th_memcpy_23: begin
2048-
if(_maxi_write_idle && (outstanding_wreq_count_0 == 0)) begin
2048+
if(_maxi_write_idle && (outstanding_wcount_0 == 0)) begin
20492049
th_memcpy <= th_memcpy_24;
20502050
end
20512051
end

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