Merge branch '1.8.0-rc' into develop

Author: shtaxxx

README.md

@@ -89,8 +89,8 @@ sudo apt install iverilog
 ```
 
 - Jinja2: 2.10 or later
-- Pyverilog: 1.1.4 or later
-- NumPy: 1.14 or later
+- Pyverilog: 1.2.0 or later
+- NumPy: 1.17 or later
 
 ```
 pip3 install pyverilog jinja2 numpy
@@ -102,8 +102,8 @@ Optional installation for testing
 These are required for automatic testing of **tests** and **examples**.
 We recommend to install these testing library to verify experimental features.
 
-- pytest: 3.2 or later
-- pytest-pythonpath: 0.7 or later
+- pytest: 3.8.1 or later
+- pytest-pythonpath: 0.7.3 or later
 
 ```
 pip3 install pytest pytest-pythonpath
@@ -133,7 +133,7 @@ pip3 install pygraphviz
 Install
 --------------------
 
-Now you can install Veriloggen using setup.py script.
+Now you can install Veriloggen using setup.py script:
 
 ```
 python3 setup.py install

README.rst

@@ -105,8 +105,8 @@ Requirements
    sudo apt install iverilog
 
 -  Jinja2: 2.10 or later
--  Pyverilog: 1.1.4 or later
--  NumPy: 1.14 or later
+-  Pyverilog: 1.2.0 or later
+-  NumPy: 1.17 or later
 
 ::
 
@@ -119,8 +119,8 @@ These are required for automatic testing of **tests** and **examples**.
 We recommend to install these testing library to verify experimental
 features.
 
--  pytest: 3.2 or later
--  pytest-pythonpath: 0.7 or later
+-  pytest: 3.8.1 or later
+-  pytest-pythonpath: 0.7.3 or later
 
 ::
 
@@ -151,7 +151,7 @@ libraries are required.
 Install
 -------
 
-Now you can install Veriloggen using setup.py script.
+Now you can install Veriloggen using setup.py script:
 
 ::
 

examples/simulation_verilator/test_simulation_verilator.py

@@ -18,7 +18,7 @@
   wire [8-1:0] myaxi_awlen;
   wire [3-1:0] myaxi_awsize;
   wire [2-1:0] myaxi_awburst;
-  wire [2-1:0] myaxi_awlock;
+  wire [1-1:0] myaxi_awlock;
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
@@ -37,7 +37,7 @@
   wire [8-1:0] myaxi_arlen;
   wire [3-1:0] myaxi_arsize;
   wire [2-1:0] myaxi_arburst;
-  wire [2-1:0] myaxi_arlock;
+  wire [1-1:0] myaxi_arlock;
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
@@ -53,7 +53,7 @@
   wire [8-1:0] memory_awlen;
   wire [3-1:0] memory_awsize;
   wire [2-1:0] memory_awburst;
-  wire [2-1:0] memory_awlock;
+  wire [1-1:0] memory_awlock;
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
@@ -72,7 +72,7 @@
   wire [8-1:0] memory_arlen;
   wire [3-1:0] memory_arsize;
   wire [2-1:0] memory_arburst;
-  wire [2-1:0] memory_arlock;
+  wire [1-1:0] memory_arlock;
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
@@ -546,7 +546,7 @@
   output reg [8-1:0] myaxi_awlen,
   output [3-1:0] myaxi_awsize,
   output [2-1:0] myaxi_awburst,
-  output [2-1:0] myaxi_awlock,
+  output [1-1:0] myaxi_awlock,
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
@@ -565,7 +565,7 @@
   output reg [8-1:0] myaxi_arlen,
   output [3-1:0] myaxi_arsize,
   output [2-1:0] myaxi_arburst,
-  output [2-1:0] myaxi_arlock,
+  output [1-1:0] myaxi_arlock,
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,

examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipxact.py

@@ -13,7 +13,7 @@
   wire [8-1:0] uut_maxi_awlen;
   wire [3-1:0] uut_maxi_awsize;
   wire [2-1:0] uut_maxi_awburst;
-  wire [2-1:0] uut_maxi_awlock;
+  wire [1-1:0] uut_maxi_awlock;
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
@@ -32,7 +32,7 @@
   wire [8-1:0] uut_maxi_arlen;
   wire [3-1:0] uut_maxi_arsize;
   wire [2-1:0] uut_maxi_arburst;
-  wire [2-1:0] uut_maxi_arlock;
+  wire [1-1:0] uut_maxi_arlock;
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
@@ -134,7 +134,7 @@
   wire [8-1:0] memory_awlen;
   wire [3-1:0] memory_awsize;
   wire [2-1:0] memory_awburst;
-  wire [2-1:0] memory_awlock;
+  wire [1-1:0] memory_awlock;
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
@@ -153,7 +153,7 @@
   wire [8-1:0] memory_arlen;
   wire [3-1:0] memory_arsize;
   wire [2-1:0] memory_arburst;
-  wire [2-1:0] memory_arlock;
+  wire [1-1:0] memory_arlock;
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
@@ -1123,7 +1123,7 @@
   output reg [8-1:0] maxi_awlen,
   output [3-1:0] maxi_awsize,
   output [2-1:0] maxi_awburst,
-  output [2-1:0] maxi_awlock,
+  output [1-1:0] maxi_awlock,
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
@@ -1142,7 +1142,7 @@
   output reg [8-1:0] maxi_arlen,
   output [3-1:0] maxi_arsize,
   output [2-1:0] maxi_arburst,
-  output [2-1:0] maxi_arlock,
+  output [1-1:0] maxi_arlock,
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,

examples/thread_memcpy_ipxact/test_thread_memcpy_ipxact.py

@@ -12,7 +12,7 @@
   wire [8-1:0] uut_maxi_awlen;
   wire [3-1:0] uut_maxi_awsize;
   wire [2-1:0] uut_maxi_awburst;
-  wire [2-1:0] uut_maxi_awlock;
+  wire [1-1:0] uut_maxi_awlock;
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
@@ -31,7 +31,7 @@
   wire [8-1:0] uut_maxi_arlen;
   wire [3-1:0] uut_maxi_arsize;
   wire [2-1:0] uut_maxi_arburst;
-  wire [2-1:0] uut_maxi_arlock;
+  wire [1-1:0] uut_maxi_arlock;
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
@@ -132,7 +132,7 @@
   wire [8-1:0] memory_awlen;
   wire [3-1:0] memory_awsize;
   wire [2-1:0] memory_awburst;
-  wire [2-1:0] memory_awlock;
+  wire [1-1:0] memory_awlock;
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
@@ -151,7 +151,7 @@
   wire [8-1:0] memory_arlen;
   wire [3-1:0] memory_arsize;
   wire [2-1:0] memory_arburst;
-  wire [2-1:0] memory_arlock;
+  wire [1-1:0] memory_arlock;
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
@@ -1120,7 +1120,7 @@
   output reg [8-1:0] maxi_awlen,
   output [3-1:0] maxi_awsize,
   output [2-1:0] maxi_awburst,
-  output [2-1:0] maxi_awlock,
+  output [1-1:0] maxi_awlock,
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
@@ -1139,7 +1139,7 @@
   output reg [8-1:0] maxi_arlen,
   output [3-1:0] maxi_arsize,
   output [2-1:0] maxi_arburst,
-  output [2-1:0] maxi_arlock,
+  output [1-1:0] maxi_arlock,
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,

examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

@@ -13,7 +13,7 @@
   wire [8-1:0] uut_maxi_awlen;
   wire [3-1:0] uut_maxi_awsize;
   wire [2-1:0] uut_maxi_awburst;
-  wire [2-1:0] uut_maxi_awlock;
+  wire [1-1:0] uut_maxi_awlock;
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
@@ -32,7 +32,7 @@
   wire [8-1:0] uut_maxi_arlen;
   wire [3-1:0] uut_maxi_arsize;
   wire [2-1:0] uut_maxi_arburst;
-  wire [2-1:0] uut_maxi_arlock;
+  wire [1-1:0] uut_maxi_arlock;
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
@@ -134,7 +134,7 @@
   wire [8-1:0] memory_awlen;
   wire [3-1:0] memory_awsize;
   wire [2-1:0] memory_awburst;
-  wire [2-1:0] memory_awlock;
+  wire [1-1:0] memory_awlock;
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
@@ -153,7 +153,7 @@
   wire [8-1:0] memory_arlen;
   wire [3-1:0] memory_arsize;
   wire [2-1:0] memory_arburst;
-  wire [2-1:0] memory_arlock;
+  wire [1-1:0] memory_arlock;
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
@@ -1123,7 +1123,7 @@
   output reg [8-1:0] maxi_awlen,
   output [3-1:0] maxi_awsize,
   output [2-1:0] maxi_awburst,
-  output [2-1:0] maxi_awlock,
+  output [1-1:0] maxi_awlock,
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
@@ -1142,7 +1142,7 @@
   output reg [8-1:0] maxi_arlen,
   output [3-1:0] maxi_arsize,
   output [2-1:0] maxi_arburst,
-  output [2-1:0] maxi_arlock,
+  output [1-1:0] maxi_arlock,
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,

setup.py

@@ -24,10 +24,10 @@ def read(filename):
       package_data={'veriloggen.utils': ['VERSION'],
                     'veriloggen.simulation': ['*.cpp'], },
       install_requires=['jinja2>=2.10',
-                        'pyverilog>=1.1.4',
-                        'numpy>=1.14'],
+                        'pyverilog>=1.2.0',
+                        'numpy>=1.17'],
       extras_require={
-          'test': ['pytest>=3.2', 'pytest-pythonpath>=0.7'],
+          'test': ['pytest>=3.8.1', 'pytest-pythonpath>=0.7.3'],
           'graph': ['pygraphviz>=1.3.1'],
       },
       )

tests/extension/resolver_/bram/resolver_bram.py

@@ -26,7 +26,7 @@ def mkBram(datawidth=32, addrwidth=10, numports=2):
         delay_addr = m.Reg('delay_ADDR%d' % i, addrwidth)
         ports.append( (addr, din, we, dout, delay_addr) )
 
-    mem = m.Reg('mem', datawidth, length=Int(2)**addrwidth)
+    mem = m.Reg('mem', datawidth, Int(2)**addrwidth)
 
     for i in range(numports):
         addr, din ,we, dout, delay_addr = ports[i]

tests/extension/types_/axi_/axi_to_ram/test_types_axi_axi_to_ram.py

@@ -12,7 +12,7 @@
   wire [8-1:0] myaxi_awlen;
   wire [3-1:0] myaxi_awsize;
   wire [2-1:0] myaxi_awburst;
-  wire [2-1:0] myaxi_awlock;
+  wire [1-1:0] myaxi_awlock;
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
@@ -31,7 +31,7 @@
   wire [8-1:0] myaxi_arlen;
   wire [3-1:0] myaxi_arsize;
   wire [2-1:0] myaxi_arburst;
-  wire [2-1:0] myaxi_arlock;
+  wire [1-1:0] myaxi_arlock;
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
@@ -245,7 +245,7 @@
   output reg [8-1:0] myaxi_awlen,
   output [3-1:0] myaxi_awsize,
   output [2-1:0] myaxi_awburst,
-  output [2-1:0] myaxi_awlock,
+  output [1-1:0] myaxi_awlock,
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
@@ -264,7 +264,7 @@
   output reg [8-1:0] myaxi_arlen,
   output [3-1:0] myaxi_arsize,
   output [2-1:0] myaxi_arburst,
-  output [2-1:0] myaxi_arlock,
+  output [1-1:0] myaxi_arlock,
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,

tests/extension/types_/axi_/memory_model_read/test_types_memory_model_read.py

@@ -12,7 +12,7 @@
   wire [8-1:0] myaxi_awlen;
   wire [3-1:0] myaxi_awsize;
   wire [2-1:0] myaxi_awburst;
-  wire [2-1:0] myaxi_awlock;
+  wire [1-1:0] myaxi_awlock;
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
@@ -31,7 +31,7 @@
   wire [8-1:0] myaxi_arlen;
   wire [3-1:0] myaxi_arsize;
   wire [2-1:0] myaxi_arburst;
-  wire [2-1:0] myaxi_arlock;
+  wire [1-1:0] myaxi_arlock;
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
@@ -47,7 +47,7 @@
   wire [8-1:0] memory_awlen;
   wire [3-1:0] memory_awsize;
   wire [2-1:0] memory_awburst;
-  wire [2-1:0] memory_awlock;
+  wire [1-1:0] memory_awlock;
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
@@ -66,7 +66,7 @@
   wire [8-1:0] memory_arlen;
   wire [3-1:0] memory_arsize;
   wire [2-1:0] memory_arburst;
-  wire [2-1:0] memory_arlock;
+  wire [1-1:0] memory_arlock;
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
@@ -528,7 +528,7 @@
   output reg [8-1:0] myaxi_awlen,
   output [3-1:0] myaxi_awsize,
   output [2-1:0] myaxi_awburst,
-  output [2-1:0] myaxi_awlock,
+  output [1-1:0] myaxi_awlock,
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
@@ -547,7 +547,7 @@
   output reg [8-1:0] myaxi_arlen,
   output [3-1:0] myaxi_arsize,
   output [2-1:0] myaxi_arburst,
-  output [2-1:0] myaxi_arlock,
+  output [1-1:0] myaxi_arlock,
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,