Merge branch 'develop'

Author: shtaxxx

.travis.yml

@@ -4,6 +4,8 @@ sudo: false
 
 python:
   - 3.7
+  - 3.8
+  - 3.9
 
 addons:
   apt:

README.md

@@ -81,15 +81,15 @@ Installation
 Requirements
 --------------------
 
-- Python3: 3.6 or later
+- Python3: 3.7 or later
 - Icarus Verilog: 10.1 or later
 
 ```
 sudo apt install iverilog
 ```
 
 - Jinja2: 2.10 or later
-- Pyverilog: 1.2.1 or later
+- Pyverilog: 1.3.0 or later
 - NumPy: 1.17 or later
 
 ```

examples/fifo_rtl/fifo_rtl.py

@@ -34,7 +34,7 @@ def mkMain(n=128, datawidth=32, numports=2):
 
     fsm.goto_next()
 
-    step = 127
+    step = n - 2
 
     ack, ready = myfifo.enq_rtl(count, cond=fsm)
 
@@ -55,7 +55,7 @@ def mkMain(n=128, datawidth=32, numports=2):
 
     fsm.goto_next()
 
-    data, valid = myfifo.deq_rtl(cond=fsm)
+    data, valid, ready = myfifo.deq_rtl(cond=fsm)
 
     fsm.If(valid)(
         sum(sum + data),
@@ -70,6 +70,12 @@ def mkMain(n=128, datawidth=32, numports=2):
 
     fsm.If(count == step).goto_next()
 
+    fsm(
+        Systask('display', "expected_sum=%d", (step - 1) * step // 2)
+    )
+
+    fsm.goto_next()
+
     fsm.make_always()
 
     return m

examples/fifo_rtl/test_fifo_rtl.py

@@ -52,11 +52,11 @@
   input RST
 );
 
-  reg myfifo_enq;
-  reg [32-1:0] myfifo_wdata;
+  wire myfifo_enq;
+  wire [32-1:0] myfifo_wdata;
   wire myfifo_full;
   wire myfifo_almost_full;
-  reg myfifo_deq;
+  wire myfifo_deq;
   wire [32-1:0] myfifo_rdata;
   wire myfifo_empty;
   wire myfifo_almost_empty;
@@ -81,18 +81,24 @@
   reg [32-1:0] sum;
   reg [32-1:0] fsm;
   localparam fsm_init = 0;
-  reg _myfifo_cond_0_1;
-  reg _tmp_0;
-  reg _myfifo_cond_1_1;
-  reg _myfifo_cond_2_1;
-  reg _myfifo_cond_3_1;
-  reg _myfifo_cond_3_2;
+  assign myfifo_wdata = (fsm == 1)? count : 'hx;
+  assign myfifo_enq = (fsm == 1)? (fsm == 1) && !myfifo_almost_full : 0;
+  localparam _tmp_0 = 1;
+  wire [_tmp_0-1:0] _tmp_1;
+  assign _tmp_1 = !myfifo_almost_full;
+  reg [_tmp_0-1:0] __tmp_1_1;
+  assign myfifo_deq = ((fsm == 3) && !myfifo_empty)? 1 : 0;
+  localparam _tmp_2 = 1;
+  wire [_tmp_2-1:0] _tmp_3;
+  assign _tmp_3 = (fsm == 3) && !myfifo_empty;
+  reg [_tmp_2-1:0] __tmp_3_1;
   reg [32-1:0] _d1_fsm;
   reg _fsm_cond_3_0_1;
   localparam fsm_1 = 1;
   localparam fsm_2 = 2;
   localparam fsm_3 = 3;
   localparam fsm_4 = 4;
+  localparam fsm_5 = 5;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -119,10 +125,10 @@
           if(!myfifo_almost_full) begin
             count <= count + 1;
           end 
-          if(!myfifo_full && myfifo_enq) begin
+          if(__tmp_1_1) begin
             $display("count=%d space=%d has_space=%d", count_myfifo, (127 - count_myfifo), (count_myfifo + 1 < 127));
           end 
-          if(!myfifo_almost_full && (count == 126)) begin
+          if(!myfifo_almost_full && (count == 125)) begin
             fsm <= fsm_2;
           end 
         end
@@ -131,16 +137,20 @@
           fsm <= fsm_3;
         end
         fsm_3: begin
-          if(_tmp_0) begin
+          if(__tmp_3_1) begin
             sum <= sum + myfifo_rdata;
             count <= count + 1;
             $write("count=%d space=%d has_space=%d ", count_myfifo, (127 - count_myfifo), (count_myfifo + 1 < 127));
           end 
-          _fsm_cond_3_0_1 <= _tmp_0;
-          if(count == 127) begin
+          _fsm_cond_3_0_1 <= __tmp_3_1;
+          if(count == 126) begin
             fsm <= fsm_4;
           end 
         end
+        fsm_4: begin
+          $display("expected_sum=%d", 7875);
+          fsm <= fsm_5;
+        end
       endcase
     end
   end
@@ -149,49 +159,18 @@
   always @(posedge CLK) begin
     if(RST) begin
       count_myfifo <= 0;
-      myfifo_wdata <= 0;
-      myfifo_enq <= 0;
-      _myfifo_cond_0_1 <= 0;
-      myfifo_deq <= 0;
-      _myfifo_cond_1_1 <= 0;
-      _tmp_0 <= 0;
-      _myfifo_cond_2_1 <= 0;
-      _myfifo_cond_3_1 <= 0;
-      _myfifo_cond_3_2 <= 0;
+      __tmp_1_1 <= 0;
+      __tmp_3_1 <= 0;
     end else begin
-      if(_myfifo_cond_3_2) begin
-        _tmp_0 <= 0;
-      end 
-      if(_myfifo_cond_0_1) begin
-        myfifo_enq <= 0;
-      end 
-      if(_myfifo_cond_1_1) begin
-        _tmp_0 <= !myfifo_empty && myfifo_deq;
-      end 
-      if(_myfifo_cond_2_1) begin
-        myfifo_deq <= 0;
-      end 
-      _myfifo_cond_3_2 <= _myfifo_cond_3_1;
       if(myfifo_enq && !myfifo_full && (myfifo_deq && !myfifo_empty)) begin
         count_myfifo <= count_myfifo;
       end else if(myfifo_enq && !myfifo_full) begin
         count_myfifo <= count_myfifo + 1;
       end else if(myfifo_deq && !myfifo_empty) begin
         count_myfifo <= count_myfifo - 1;
       end 
-      if((fsm == 1) && !myfifo_full) begin
-        myfifo_wdata <= count;
-      end 
-      if((fsm == 1) && !myfifo_full) begin
-        myfifo_enq <= 1;
-      end 
-      _myfifo_cond_0_1 <= 1;
-      if(fsm == 3) begin
-        myfifo_deq <= 1;
-      end 
-      _myfifo_cond_1_1 <= fsm == 3;
-      _myfifo_cond_2_1 <= 1;
-      _myfifo_cond_3_1 <= 1;
+      __tmp_1_1 <= _tmp_1;
+      __tmp_3_1 <= _tmp_3;
     end
   end
 

examples/ram_rtl/ram_rtl.py

@@ -81,6 +81,14 @@ def mkMain(n=128, datawidth=32, numports=2):
         Systask('display', "sum=%d", sum)
     )
 
+    fsm.goto_next()
+
+    fsm(
+        Systask('display', "expected_sum=%d", (step - 1) * step // 2)
+    )
+
+    fsm.goto_next()
+
     fsm.make_always()
 
     return m

examples/ram_rtl/test_ram_rtl.py

@@ -52,10 +52,11 @@
   input RST
 );
 
-  reg [14-1:0] myram_0_addr;
+  wire [14-1:0] myram_0_addr;
   wire [32-1:0] myram_0_rdata;
-  reg [32-1:0] myram_0_wdata;
-  reg myram_0_wenable;
+  wire [32-1:0] myram_0_wdata;
+  wire myram_0_wenable;
+  wire myram_0_enable;
 
   myram
   inst_myram
@@ -64,25 +65,33 @@
     .myram_0_addr(myram_0_addr),
     .myram_0_rdata(myram_0_rdata),
     .myram_0_wdata(myram_0_wdata),
-    .myram_0_wenable(myram_0_wenable)
+    .myram_0_wenable(myram_0_wenable),
+    .myram_0_enable(myram_0_enable)
   );
 
   reg [32-1:0] count;
   reg [32-1:0] sum;
   reg [32-1:0] addr;
   reg [32-1:0] fsm;
   localparam fsm_init = 0;
-  reg _myram_cond_0_1;
-  reg _tmp_0;
-  reg _myram_cond_1_1;
-  reg _myram_cond_2_1;
-  reg _myram_cond_2_2;
+  assign myram_0_wdata = (fsm == 1)? count : 'hx;
+  assign myram_0_wenable = (fsm == 1)? 1'd1 : 0;
+  assign myram_0_addr = (fsm == 2)? addr : 
+                        (fsm == 1)? addr : 'hx;
+  assign myram_0_enable = (fsm == 2)? 1'd1 : 
+                          (fsm == 1)? 1'd1 : 0;
+  localparam _tmp_0 = 1;
+  wire [_tmp_0-1:0] _tmp_1;
+  assign _tmp_1 = fsm == 2;
+  reg [_tmp_0-1:0] __tmp_1_1;
   reg [32-1:0] _d1_fsm;
   reg _fsm_cond_2_0_1;
   reg _fsm_cond_3_1_1;
   localparam fsm_1 = 1;
   localparam fsm_2 = 2;
   localparam fsm_3 = 3;
+  localparam fsm_4 = 4;
+  localparam fsm_5 = 5;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -128,10 +137,10 @@
         fsm_2: begin
           addr <= addr + 1;
           count <= count + 1;
-          if(_tmp_0) begin
+          if(__tmp_1_1) begin
             sum <= sum + myram_0_rdata;
           end 
-          _fsm_cond_2_0_1 <= _tmp_0;
+          _fsm_cond_2_0_1 <= __tmp_1_1;
           if(count == 15) begin
             addr <= 0;
             count <= 0;
@@ -141,10 +150,15 @@
           end 
         end
         fsm_3: begin
-          if(_tmp_0) begin
+          if(__tmp_1_1) begin
             sum <= sum + myram_0_rdata;
           end 
-          _fsm_cond_3_1_1 <= _tmp_0;
+          _fsm_cond_3_1_1 <= __tmp_1_1;
+          fsm <= fsm_4;
+        end
+        fsm_4: begin
+          $display("expected_sum=%d", 120);
+          fsm <= fsm_5;
         end
       endcase
     end
@@ -153,36 +167,9 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      myram_0_addr <= 0;
-      myram_0_wdata <= 0;
-      myram_0_wenable <= 0;
-      _myram_cond_0_1 <= 0;
-      _myram_cond_1_1 <= 0;
-      _tmp_0 <= 0;
-      _myram_cond_2_1 <= 0;
-      _myram_cond_2_2 <= 0;
+      __tmp_1_1 <= 0;
     end else begin
-      if(_myram_cond_2_2) begin
-        _tmp_0 <= 0;
-      end 
-      if(_myram_cond_0_1) begin
-        myram_0_wenable <= 0;
-      end 
-      if(_myram_cond_1_1) begin
-        _tmp_0 <= 1;
-      end 
-      _myram_cond_2_2 <= _myram_cond_2_1;
-      if(fsm == 1) begin
-        myram_0_addr <= addr;
-        myram_0_wdata <= count;
-        myram_0_wenable <= 1;
-      end 
-      _myram_cond_0_1 <= fsm == 1;
-      if(fsm == 2) begin
-        myram_0_addr <= addr;
-      end 
-      _myram_cond_1_1 <= fsm == 2;
-      _myram_cond_2_1 <= fsm == 2;
+      __tmp_1_1 <= _tmp_1;
     end
   end
 
@@ -197,20 +184,25 @@
   input [14-1:0] myram_0_addr,
   output [32-1:0] myram_0_rdata,
   input [32-1:0] myram_0_wdata,
-  input myram_0_wenable
+  input myram_0_wenable,
+  input myram_0_enable
 );
 
-  reg [14-1:0] myram_0_daddr;
+  reg [32-1:0] myram_0_rdata_out;
+  assign myram_0_rdata = myram_0_rdata_out;
   reg [32-1:0] mem [0:16384-1];
 
   always @(posedge CLK) begin
-    if(myram_0_wenable) begin
-      mem[myram_0_addr] <= myram_0_wdata;
+    if(myram_0_enable) begin
+      if(myram_0_wenable) begin
+        mem[myram_0_addr] <= myram_0_wdata;
+        myram_0_rdata_out <= myram_0_wdata;
+      end else begin
+        myram_0_rdata_out <= mem[myram_0_addr];
+      end
     end 
-    myram_0_daddr <= myram_0_addr;
   end
 
-  assign myram_0_rdata = mem[myram_0_daddr];
 
 endmodule
 """