Bug fix of multiple drivers in stream.Substream

shtaxxx · shtaxxx · commit 46eeb932b595 · 2022-04-04T08:00:57.000+09:00
diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py
@@ -4027,10 +4027,10 @@ def _implement(self, m, seq, svalid=None, senable=None):
             ii_count(0)
         )
 
-        seq.If(self.strm.busy, self.child.ivalid)(
+        self.child.fsm.seq.If(self.strm.busy, self.child.ivalid)(
             self.child.ivalid(vtypes.Int(0, 1))
         )
-        seq.If(enable_cond, ii_count == 0)(
+        self.child.fsm.seq.If(enable_cond, ii_count == 0)(
             self.child.ivalid(vtypes.Int(1, 1))
         )
 

Original file line number	Diff line number	Diff line change
`@@ -4027,10 +4027,10 @@ def _implement(self, m, seq, svalid=None, senable=None):`
`4027`	`4027`	`ii_count(0)`
`4028`	`4028`	`)`
`4029`	`4029`
`4030`		`- seq.If(self.strm.busy, self.child.ivalid)(`
	`4030`	`+ self.child.fsm.seq.If(self.strm.busy, self.child.ivalid)(`
`4031`	`4031`	`self.child.ivalid(vtypes.Int(0, 1))`
`4032`	`4032`	`)`
`4033`		`- seq.If(enable_cond, ii_count == 0)(`
	`4033`	`+ self.child.fsm.seq.If(enable_cond, ii_count == 0)(`
`4034`	`4034`	`self.child.ivalid(vtypes.Int(1, 1))`
`4035`	`4035`	`)`
`4036`	`4036`