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Merge branch 'rc-1.5.2'
2 parents ee30238 + f7d46ee commit 536d48d

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11 files changed

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-96
lines changed

11 files changed

+96
-96
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‎examples/thread_add_ipcore/test_thread_add_ipcore.py‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -807,98 +807,98 @@
807807
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
808808
_saxi_register_7 <= saxi_wdata;
809809
end
810-
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 0)) begin
810+
if((_saxi_register_0 == 1) && (th_add == 2) && 1) begin
811811
_saxi_register_0 <= 0;
812812
end
813-
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 1)) begin
813+
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
814814
_saxi_register_1 <= 0;
815815
end
816-
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 2)) begin
816+
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
817817
_saxi_register_2 <= 0;
818818
end
819-
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 3)) begin
819+
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
820820
_saxi_register_3 <= 0;
821821
end
822-
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 4)) begin
822+
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
823823
_saxi_register_4 <= 0;
824824
end
825-
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 5)) begin
825+
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
826826
_saxi_register_5 <= 0;
827827
end
828-
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 6)) begin
828+
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
829829
_saxi_register_6 <= 0;
830830
end
831-
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 7)) begin
831+
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
832832
_saxi_register_7 <= 0;
833833
end
834-
if((th_add == 6) && (4 == 0)) begin
834+
if((th_add == 6) && 0) begin
835835
_saxi_register_0 <= _th_add_c_2;
836836
_saxi_flag_0 <= 0;
837837
end
838-
if((th_add == 6) && (4 == 1)) begin
838+
if((th_add == 6) && 0) begin
839839
_saxi_register_1 <= _th_add_c_2;
840840
_saxi_flag_1 <= 0;
841841
end
842-
if((th_add == 6) && (4 == 2)) begin
842+
if((th_add == 6) && 0) begin
843843
_saxi_register_2 <= _th_add_c_2;
844844
_saxi_flag_2 <= 0;
845845
end
846-
if((th_add == 6) && (4 == 3)) begin
846+
if((th_add == 6) && 0) begin
847847
_saxi_register_3 <= _th_add_c_2;
848848
_saxi_flag_3 <= 0;
849849
end
850-
if((th_add == 6) && (4 == 4)) begin
850+
if((th_add == 6) && 1) begin
851851
_saxi_register_4 <= _th_add_c_2;
852852
_saxi_flag_4 <= 0;
853853
end
854-
if((th_add == 6) && (4 == 5)) begin
854+
if((th_add == 6) && 0) begin
855855
_saxi_register_5 <= _th_add_c_2;
856856
_saxi_flag_5 <= 0;
857857
end
858-
if((th_add == 6) && (4 == 6)) begin
858+
if((th_add == 6) && 0) begin
859859
_saxi_register_6 <= _th_add_c_2;
860860
_saxi_flag_6 <= 0;
861861
end
862-
if((th_add == 6) && (4 == 7)) begin
862+
if((th_add == 6) && 0) begin
863863
_saxi_register_7 <= _th_add_c_2;
864864
_saxi_flag_7 <= 0;
865865
end
866-
if((th_add == 7) && (1 == 0)) begin
866+
if((th_add == 7) && 0) begin
867867
_saxi_register_0 <= 1;
868868
_saxi_flag_0 <= 1;
869869
_saxi_resetval_0 <= 0;
870870
end
871-
if((th_add == 7) && (1 == 1)) begin
871+
if((th_add == 7) && 1) begin
872872
_saxi_register_1 <= 1;
873873
_saxi_flag_1 <= 1;
874874
_saxi_resetval_1 <= 0;
875875
end
876-
if((th_add == 7) && (1 == 2)) begin
876+
if((th_add == 7) && 0) begin
877877
_saxi_register_2 <= 1;
878878
_saxi_flag_2 <= 1;
879879
_saxi_resetval_2 <= 0;
880880
end
881-
if((th_add == 7) && (1 == 3)) begin
881+
if((th_add == 7) && 0) begin
882882
_saxi_register_3 <= 1;
883883
_saxi_flag_3 <= 1;
884884
_saxi_resetval_3 <= 0;
885885
end
886-
if((th_add == 7) && (1 == 4)) begin
886+
if((th_add == 7) && 0) begin
887887
_saxi_register_4 <= 1;
888888
_saxi_flag_4 <= 1;
889889
_saxi_resetval_4 <= 0;
890890
end
891-
if((th_add == 7) && (1 == 5)) begin
891+
if((th_add == 7) && 0) begin
892892
_saxi_register_5 <= 1;
893893
_saxi_flag_5 <= 1;
894894
_saxi_resetval_5 <= 0;
895895
end
896-
if((th_add == 7) && (1 == 6)) begin
896+
if((th_add == 7) && 0) begin
897897
_saxi_register_6 <= 1;
898898
_saxi_flag_6 <= 1;
899899
_saxi_resetval_6 <= 0;
900900
end
901-
if((th_add == 7) && (1 == 7)) begin
901+
if((th_add == 7) && 0) begin
902902
_saxi_register_7 <= 1;
903903
_saxi_flag_7 <= 1;
904904
_saxi_resetval_7 <= 0;

‎examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipcore.py‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1551,66 +1551,66 @@
15511551
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
15521552
_saxi_register_7 <= saxi_wdata;
15531553
end
1554-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 0)) begin
1554+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin
15551555
_saxi_register_0 <= 0;
15561556
end
1557-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 1)) begin
1557+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15581558
_saxi_register_1 <= 0;
15591559
end
1560-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 2)) begin
1560+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15611561
_saxi_register_2 <= 0;
15621562
end
1563-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 3)) begin
1563+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15641564
_saxi_register_3 <= 0;
15651565
end
1566-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 4)) begin
1566+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15671567
_saxi_register_4 <= 0;
15681568
end
1569-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 5)) begin
1569+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15701570
_saxi_register_5 <= 0;
15711571
end
1572-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 6)) begin
1572+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15731573
_saxi_register_6 <= 0;
15741574
end
1575-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 7)) begin
1575+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15761576
_saxi_register_7 <= 0;
15771577
end
1578-
if((th_memcpy == 28) && (4 == 0)) begin
1578+
if((th_memcpy == 28) && 0) begin
15791579
_saxi_register_0 <= 1;
15801580
_saxi_flag_0 <= 1;
15811581
_saxi_resetval_0 <= 0;
15821582
end
1583-
if((th_memcpy == 28) && (4 == 1)) begin
1583+
if((th_memcpy == 28) && 0) begin
15841584
_saxi_register_1 <= 1;
15851585
_saxi_flag_1 <= 1;
15861586
_saxi_resetval_1 <= 0;
15871587
end
1588-
if((th_memcpy == 28) && (4 == 2)) begin
1588+
if((th_memcpy == 28) && 0) begin
15891589
_saxi_register_2 <= 1;
15901590
_saxi_flag_2 <= 1;
15911591
_saxi_resetval_2 <= 0;
15921592
end
1593-
if((th_memcpy == 28) && (4 == 3)) begin
1593+
if((th_memcpy == 28) && 0) begin
15941594
_saxi_register_3 <= 1;
15951595
_saxi_flag_3 <= 1;
15961596
_saxi_resetval_3 <= 0;
15971597
end
1598-
if((th_memcpy == 28) && (4 == 4)) begin
1598+
if((th_memcpy == 28) && 1) begin
15991599
_saxi_register_4 <= 1;
16001600
_saxi_flag_4 <= 1;
16011601
_saxi_resetval_4 <= 0;
16021602
end
1603-
if((th_memcpy == 28) && (4 == 5)) begin
1603+
if((th_memcpy == 28) && 0) begin
16041604
_saxi_register_5 <= 1;
16051605
_saxi_flag_5 <= 1;
16061606
_saxi_resetval_5 <= 0;
16071607
end
1608-
if((th_memcpy == 28) && (4 == 6)) begin
1608+
if((th_memcpy == 28) && 0) begin
16091609
_saxi_register_6 <= 1;
16101610
_saxi_flag_6 <= 1;
16111611
_saxi_resetval_6 <= 0;
16121612
end
1613-
if((th_memcpy == 28) && (4 == 7)) begin
1613+
if((th_memcpy == 28) && 0) begin
16141614
_saxi_register_7 <= 1;
16151615
_saxi_flag_7 <= 1;
16161616
_saxi_resetval_7 <= 0;

‎examples/thread_ipcore/test_thread_ipcore.py‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -697,50 +697,50 @@
697697
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
698698
_saxi_register_3 <= saxi_wdata;
699699
end
700-
if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 0)) begin
700+
if((_saxi_register_0 == 1) && (th_blink == 2) && 1) begin
701701
_saxi_register_0 <= 0;
702702
end
703-
if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 1)) begin
703+
if((_saxi_register_0 == 1) && (th_blink == 2) && 0) begin
704704
_saxi_register_1 <= 0;
705705
end
706-
if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 2)) begin
706+
if((_saxi_register_0 == 1) && (th_blink == 2) && 0) begin
707707
_saxi_register_2 <= 0;
708708
end
709-
if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 3)) begin
709+
if((_saxi_register_0 == 1) && (th_blink == 2) && 0) begin
710710
_saxi_register_3 <= 0;
711711
end
712-
if((th_blink == 3) && (3 == 0)) begin
712+
if((th_blink == 3) && 0) begin
713713
_saxi_register_0 <= 0;
714714
_saxi_flag_0 <= 0;
715715
end
716-
if((th_blink == 3) && (3 == 1)) begin
716+
if((th_blink == 3) && 0) begin
717717
_saxi_register_1 <= 0;
718718
_saxi_flag_1 <= 0;
719719
end
720-
if((th_blink == 3) && (3 == 2)) begin
720+
if((th_blink == 3) && 0) begin
721721
_saxi_register_2 <= 0;
722722
_saxi_flag_2 <= 0;
723723
end
724-
if((th_blink == 3) && (3 == 3)) begin
724+
if((th_blink == 3) && 1) begin
725725
_saxi_register_3 <= 0;
726726
_saxi_flag_3 <= 0;
727727
end
728-
if((th_blink == 11) && (3 == 0)) begin
728+
if((th_blink == 11) && 0) begin
729729
_saxi_register_0 <= 1;
730730
_saxi_flag_0 <= 1;
731731
_saxi_resetval_0 <= 0;
732732
end
733-
if((th_blink == 11) && (3 == 1)) begin
733+
if((th_blink == 11) && 0) begin
734734
_saxi_register_1 <= 1;
735735
_saxi_flag_1 <= 1;
736736
_saxi_resetval_1 <= 0;
737737
end
738-
if((th_blink == 11) && (3 == 2)) begin
738+
if((th_blink == 11) && 0) begin
739739
_saxi_register_2 <= 1;
740740
_saxi_flag_2 <= 1;
741741
_saxi_resetval_2 <= 0;
742742
end
743-
if((th_blink == 11) && (3 == 3)) begin
743+
if((th_blink == 11) && 1) begin
744744
_saxi_register_3 <= 1;
745745
_saxi_flag_3 <= 1;
746746
_saxi_resetval_3 <= 0;

‎examples/thread_memcpy_ipcore/test_thread_memcpy_ipcore.py‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1537,66 +1537,66 @@
15371537
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
15381538
_saxi_register_7 <= saxi_wdata;
15391539
end
1540-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 0)) begin
1540+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin
15411541
_saxi_register_0 <= 0;
15421542
end
1543-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 1)) begin
1543+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15441544
_saxi_register_1 <= 0;
15451545
end
1546-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 2)) begin
1546+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15471547
_saxi_register_2 <= 0;
15481548
end
1549-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 3)) begin
1549+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15501550
_saxi_register_3 <= 0;
15511551
end
1552-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 4)) begin
1552+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15531553
_saxi_register_4 <= 0;
15541554
end
1555-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 5)) begin
1555+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15561556
_saxi_register_5 <= 0;
15571557
end
1558-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 6)) begin
1558+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15591559
_saxi_register_6 <= 0;
15601560
end
1561-
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 7)) begin
1561+
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
15621562
_saxi_register_7 <= 0;
15631563
end
1564-
if((th_memcpy == 28) && (4 == 0)) begin
1564+
if((th_memcpy == 28) && 0) begin
15651565
_saxi_register_0 <= 1;
15661566
_saxi_flag_0 <= 1;
15671567
_saxi_resetval_0 <= 0;
15681568
end
1569-
if((th_memcpy == 28) && (4 == 1)) begin
1569+
if((th_memcpy == 28) && 0) begin
15701570
_saxi_register_1 <= 1;
15711571
_saxi_flag_1 <= 1;
15721572
_saxi_resetval_1 <= 0;
15731573
end
1574-
if((th_memcpy == 28) && (4 == 2)) begin
1574+
if((th_memcpy == 28) && 0) begin
15751575
_saxi_register_2 <= 1;
15761576
_saxi_flag_2 <= 1;
15771577
_saxi_resetval_2 <= 0;
15781578
end
1579-
if((th_memcpy == 28) && (4 == 3)) begin
1579+
if((th_memcpy == 28) && 0) begin
15801580
_saxi_register_3 <= 1;
15811581
_saxi_flag_3 <= 1;
15821582
_saxi_resetval_3 <= 0;
15831583
end
1584-
if((th_memcpy == 28) && (4 == 4)) begin
1584+
if((th_memcpy == 28) && 1) begin
15851585
_saxi_register_4 <= 1;
15861586
_saxi_flag_4 <= 1;
15871587
_saxi_resetval_4 <= 0;
15881588
end
1589-
if((th_memcpy == 28) && (4 == 5)) begin
1589+
if((th_memcpy == 28) && 0) begin
15901590
_saxi_register_5 <= 1;
15911591
_saxi_flag_5 <= 1;
15921592
_saxi_resetval_5 <= 0;
15931593
end
1594-
if((th_memcpy == 28) && (4 == 6)) begin
1594+
if((th_memcpy == 28) && 0) begin
15951595
_saxi_register_6 <= 1;
15961596
_saxi_flag_6 <= 1;
15971597
_saxi_resetval_6 <= 0;
15981598
end
1599-
if((th_memcpy == 28) && (4 == 7)) begin
1599+
if((th_memcpy == 28) && 0) begin
16001600
_saxi_register_7 <= 1;
16011601
_saxi_flag_7 <= 1;
16021602
_saxi_resetval_7 <= 0;

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