Header

Author: shtaxxx

README.md

@@ -58,7 +58,7 @@ Veriloggen project always welcomes questions, bug reports, feature proposals, an
 
 ### for questions, bug reports, and feature proposals
 
-Please leave your comment on the [issue tracker](https://github.com/PyHDI/Veriloggen/issues) on GitHub.
+Please leave your comment on the [issue tracker](https://github.com/PyHDI/veriloggen/issues) on GitHub.
 
 ### for pull requests
 

README.rst

@@ -68,7 +68,7 @@ for questions, bug reports, and feature proposals
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Please leave your comment on the `issue
-tracker <https://github.com/PyHDI/Veriloggen/issues>`__ on GitHub.
+tracker <https://github.com/PyHDI/veriloggen/issues>`__ on GitHub.
 
 for pull requests
 ~~~~~~~~~~~~~~~~~

veriloggen/__init__.py

@@ -1,9 +1,21 @@
-#-------------------------------------------------------------------------
-# Veriloggen: A library for constructing a Verilog HDL source code in Python
-#
-# Copyright (C) 2015, Shinya Takamaeda-Yamazaki
-# License: Apache 2.0
-#-------------------------------------------------------------------------
+"""
+   Veriloggen: A library for constructing a Verilog HDL source code in Python
+
+   Copyright 2015, Shinya Takamaeda-Yamazaki and Contributors
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
+"""
+
 from __future__ import absolute_import
 from __future__ import print_function