All ID and USER widths of AXI interfaces are customizable.

Author: shtaxxx

examples/simulation_verilator/test_simulation_verilator.py

@@ -14,7 +14,6 @@
 
   reg CLK;
   reg RST;
-  wire [1-1:0] myaxi_awid;
   wire [32-1:0] myaxi_awaddr;
   wire [8-1:0] myaxi_awlen;
   wire [3-1:0] myaxi_awsize;
@@ -29,15 +28,11 @@
   wire [32-1:0] myaxi_wdata;
   wire [4-1:0] myaxi_wstrb;
   wire myaxi_wlast;
-  wire [1-1:0] myaxi_wuser;
   wire myaxi_wvalid;
   reg myaxi_wready;
-  reg [1-1:0] myaxi_bid;
   reg [2-1:0] myaxi_bresp;
-  reg [1-1:0] myaxi_buser;
   reg myaxi_bvalid;
   wire myaxi_bready;
-  wire [1-1:0] myaxi_arid;
   wire [32-1:0] myaxi_araddr;
   wire [8-1:0] myaxi_arlen;
   wire [3-1:0] myaxi_arsize;
@@ -49,14 +44,11 @@
   wire [1-1:0] myaxi_aruser;
   wire myaxi_arvalid;
   reg myaxi_arready;
-  reg [1-1:0] myaxi_rid;
   reg [32-1:0] myaxi_rdata;
   reg [2-1:0] myaxi_rresp;
   reg myaxi_rlast;
-  reg [1-1:0] myaxi_ruser;
   reg myaxi_rvalid;
   wire myaxi_rready;
-  wire [1-1:0] memory_awid;
   wire [32-1:0] memory_awaddr;
   wire [8-1:0] memory_awlen;
   wire [3-1:0] memory_awsize;
@@ -71,15 +63,11 @@
   wire [32-1:0] memory_wdata;
   wire [4-1:0] memory_wstrb;
   wire memory_wlast;
-  wire [1-1:0] memory_wuser;
   wire memory_wvalid;
   reg memory_wready;
-  reg [1-1:0] memory_bid;
   wire [2-1:0] memory_bresp;
-  wire [1-1:0] memory_buser;
   reg memory_bvalid;
   wire memory_bready;
-  wire [1-1:0] memory_arid;
   wire [32-1:0] memory_araddr;
   wire [8-1:0] memory_arlen;
   wire [3-1:0] memory_arsize;
@@ -91,17 +79,13 @@
   wire [1-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
-  reg [1-1:0] memory_rid;
   reg [32-1:0] memory_rdata;
   wire [2-1:0] memory_rresp;
   reg memory_rlast;
-  wire [1-1:0] memory_ruser;
   reg memory_rvalid;
   wire memory_rready;
   assign memory_bresp = 0;
-  assign memory_buser = 1;
   assign memory_rresp = 0;
-  assign memory_ruser = 1;
   reg [32-1:0] _memory_fsm;
   localparam _memory_fsm_init = 0;
   reg [8-1:0] _memory_mem [0:2**20-1];
@@ -119,7 +103,6 @@
   reg __memory_fsm_cond_100_0_1;
   reg __memory_fsm_cond_200_1_1;
   reg __memory_fsm_cond_211_2_1;
-  assign memory_awid = myaxi_awid;
   assign memory_awaddr = myaxi_awaddr;
   assign memory_awlen = myaxi_awlen;
   assign memory_awsize = myaxi_awsize;
@@ -140,7 +123,6 @@
   assign memory_wdata = myaxi_wdata;
   assign memory_wstrb = myaxi_wstrb;
   assign memory_wlast = myaxi_wlast;
-  assign memory_wuser = myaxi_wuser;
   assign memory_wvalid = myaxi_wvalid;
   wire _tmp_1;
   assign _tmp_1 = memory_wready;
@@ -149,36 +131,21 @@
     myaxi_wready = _tmp_1;
   end
 
-  wire [1-1:0] _tmp_2;
-  assign _tmp_2 = memory_bid;
+  wire [2-1:0] _tmp_2;
+  assign _tmp_2 = memory_bresp;
 
   always @(*) begin
-    myaxi_bid = _tmp_2;
+    myaxi_bresp = _tmp_2;
   end
 
-  wire [2-1:0] _tmp_3;
-  assign _tmp_3 = memory_bresp;
+  wire _tmp_3;
+  assign _tmp_3 = memory_bvalid;
 
   always @(*) begin
-    myaxi_bresp = _tmp_3;
-  end
-
-  wire [1-1:0] _tmp_4;
-  assign _tmp_4 = memory_buser;
-
-  always @(*) begin
-    myaxi_buser = _tmp_4;
-  end
-
-  wire _tmp_5;
-  assign _tmp_5 = memory_bvalid;
-
-  always @(*) begin
-    myaxi_bvalid = _tmp_5;
+    myaxi_bvalid = _tmp_3;
   end
 
   assign memory_bready = myaxi_bready;
-  assign memory_arid = myaxi_arid;
   assign memory_araddr = myaxi_araddr;
   assign memory_arlen = myaxi_arlen;
   assign memory_arsize = myaxi_arsize;
@@ -189,53 +156,39 @@
   assign memory_arqos = myaxi_arqos;
   assign memory_aruser = myaxi_aruser;
   assign memory_arvalid = myaxi_arvalid;
-  wire _tmp_6;
-  assign _tmp_6 = memory_arready;
-
-  always @(*) begin
-    myaxi_arready = _tmp_6;
-  end
-
-  wire [1-1:0] _tmp_7;
-  assign _tmp_7 = memory_rid;
-
-  always @(*) begin
-    myaxi_rid = _tmp_7;
-  end
-
-  wire [32-1:0] _tmp_8;
-  assign _tmp_8 = memory_rdata;
+  wire _tmp_4;
+  assign _tmp_4 = memory_arready;
 
   always @(*) begin
-    myaxi_rdata = _tmp_8;
+    myaxi_arready = _tmp_4;
   end
 
-  wire [2-1:0] _tmp_9;
-  assign _tmp_9 = memory_rresp;
+  wire [32-1:0] _tmp_5;
+  assign _tmp_5 = memory_rdata;
 
   always @(*) begin
-    myaxi_rresp = _tmp_9;
+    myaxi_rdata = _tmp_5;
   end
 
-  wire _tmp_10;
-  assign _tmp_10 = memory_rlast;
+  wire [2-1:0] _tmp_6;
+  assign _tmp_6 = memory_rresp;
 
   always @(*) begin
-    myaxi_rlast = _tmp_10;
+    myaxi_rresp = _tmp_6;
   end
 
-  wire [1-1:0] _tmp_11;
-  assign _tmp_11 = memory_ruser;
+  wire _tmp_7;
+  assign _tmp_7 = memory_rlast;
 
   always @(*) begin
-    myaxi_ruser = _tmp_11;
+    myaxi_rlast = _tmp_7;
   end
 
-  wire _tmp_12;
-  assign _tmp_12 = memory_rvalid;
+  wire _tmp_8;
+  assign _tmp_8 = memory_rvalid;
 
   always @(*) begin
-    myaxi_rvalid = _tmp_12;
+    myaxi_rvalid = _tmp_8;
   end
 
   assign memory_rready = myaxi_rready;
@@ -245,7 +198,6 @@
   (
     .CLK(CLK),
     .RST(RST),
-    .myaxi_awid(myaxi_awid),
     .myaxi_awaddr(myaxi_awaddr),
     .myaxi_awlen(myaxi_awlen),
     .myaxi_awsize(myaxi_awsize),
@@ -260,15 +212,11 @@
     .myaxi_wdata(myaxi_wdata),
     .myaxi_wstrb(myaxi_wstrb),
     .myaxi_wlast(myaxi_wlast),
-    .myaxi_wuser(myaxi_wuser),
     .myaxi_wvalid(myaxi_wvalid),
     .myaxi_wready(myaxi_wready),
-    .myaxi_bid(myaxi_bid),
     .myaxi_bresp(myaxi_bresp),
-    .myaxi_buser(myaxi_buser),
     .myaxi_bvalid(myaxi_bvalid),
     .myaxi_bready(myaxi_bready),
-    .myaxi_arid(myaxi_arid),
     .myaxi_araddr(myaxi_araddr),
     .myaxi_arlen(myaxi_arlen),
     .myaxi_arsize(myaxi_arsize),
@@ -280,11 +228,9 @@
     .myaxi_aruser(myaxi_aruser),
     .myaxi_arvalid(myaxi_arvalid),
     .myaxi_arready(myaxi_arready),
-    .myaxi_rid(myaxi_rid),
     .myaxi_rdata(myaxi_rdata),
     .myaxi_rresp(myaxi_rresp),
     .myaxi_rlast(myaxi_rlast),
-    .myaxi_ruser(myaxi_ruser),
     .myaxi_rvalid(myaxi_rvalid),
     .myaxi_rready(myaxi_rready)
   );
@@ -306,10 +252,8 @@
     RST = 0;
     memory_awready = 0;
     memory_wready = 0;
-    memory_bid = 0;
     memory_bvalid = 0;
     memory_arready = 0;
-    memory_rid = 0;
     memory_rdata = 0;
     memory_rlast = 0;
     memory_rvalid = 0;
@@ -331,18 +275,18 @@
     $write("");
   end
 
-  wire _tmp_13;
-  assign _tmp_13 = io_CLK;
+  wire _tmp_9;
+  assign _tmp_9 = io_CLK;
 
   always @(*) begin
-    CLK = _tmp_13;
+    CLK = _tmp_9;
   end
 
-  wire _tmp_14;
-  assign _tmp_14 = io_RST;
+  wire _tmp_10;
+  assign _tmp_10 = io_RST;
 
   always @(*) begin
-    RST = _tmp_14;
+    RST = _tmp_10;
   end
 
   localparam _memory_fsm_200 = 200;
@@ -392,17 +336,9 @@
       memory_rlast <= 0;
       __memory_fsm_cond_211_2_1 <= 0;
       memory_rdata <= 0;
-      memory_bid <= 0;
-      memory_rid <= 0;
       memory_bvalid <= 0;
       _sleep_count <= 0;
     end else begin
-      if(memory_awvalid && memory_awready && !memory_bvalid) begin
-        memory_bid <= memory_awid;
-      end 
-      if(memory_arvalid && memory_arready) begin
-        memory_rid <= memory_arid;
-      end 
       if(memory_bvalid && memory_bready) begin
         memory_bvalid <= 0;
       end 
@@ -606,7 +542,6 @@
 (
   input CLK,
   input RST,
-  output reg [1-1:0] myaxi_awid,
   output reg [32-1:0] myaxi_awaddr,
   output reg [8-1:0] myaxi_awlen,
   output [3-1:0] myaxi_awsize,
@@ -621,15 +556,11 @@
   output reg [32-1:0] myaxi_wdata,
   output reg [4-1:0] myaxi_wstrb,
   output reg myaxi_wlast,
-  output [1-1:0] myaxi_wuser,
   output reg myaxi_wvalid,
   input myaxi_wready,
-  input [1-1:0] myaxi_bid,
   input [2-1:0] myaxi_bresp,
-  input [1-1:0] myaxi_buser,
   input myaxi_bvalid,
   output myaxi_bready,
-  output reg [1-1:0] myaxi_arid,
   output reg [32-1:0] myaxi_araddr,
   output reg [8-1:0] myaxi_arlen,
   output [3-1:0] myaxi_arsize,
@@ -641,11 +572,9 @@
   output [1-1:0] myaxi_aruser,
   output reg myaxi_arvalid,
   input myaxi_arready,
-  input [1-1:0] myaxi_rid,
   input [32-1:0] myaxi_rdata,
   input [2-1:0] myaxi_rresp,
   input myaxi_rlast,
-  input [1-1:0] myaxi_ruser,
   input myaxi_rvalid,
   output myaxi_rready
 );
@@ -703,7 +632,6 @@
   assign myaxi_awprot = 0;
   assign myaxi_awqos = 0;
   assign myaxi_awuser = 1;
-  assign myaxi_wuser = 1;
   assign myaxi_bready = 1;
   assign myaxi_arsize = 2;
   assign myaxi_arburst = 1;
@@ -1102,7 +1030,6 @@
       _myaxi_read_global_addr <= 0;
       _myaxi_read_size <= 0;
       _myaxi_read_local_stride <= 0;
-      myaxi_arid <= 0;
       myaxi_araddr <= 0;
       myaxi_arlen <= 0;
       myaxi_arvalid <= 0;
@@ -1126,7 +1053,6 @@
       _myaxi_write_global_addr <= 0;
       _myaxi_write_size <= 0;
       _myaxi_write_local_stride <= 0;
-      myaxi_awid <= 0;
       myaxi_awaddr <= 0;
       myaxi_awlen <= 0;
       myaxi_awvalid <= 0;
@@ -1179,7 +1105,6 @@
         _myaxi_read_local_stride <= _myaxi_ram_a_0_read_local_stride;
       end 
       if((_myaxi_read_fsm == 2) && ((myaxi_arready || !myaxi_arvalid) && (_tmp_5 == 0))) begin
-        myaxi_arid <= 0;
         myaxi_araddr <= _myaxi_read_cur_global_addr;
         myaxi_arlen <= _myaxi_read_cur_size - 1;
         myaxi_arvalid <= 1;
@@ -1236,7 +1161,6 @@
         _myaxi_write_local_stride <= _myaxi_ram_c_0_write_local_stride;
       end 
       if((_myaxi_write_fsm == 2) && ((myaxi_awready || !myaxi_awvalid) && (_tmp_29 == 0))) begin
-        myaxi_awid <= 0;
         myaxi_awaddr <= _myaxi_write_cur_global_addr;
         myaxi_awlen <= _myaxi_write_cur_size - 1;
         myaxi_awvalid <= 1;