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Merge pull request #56 from estodi/feature_thread_print_fstrings
Add f-strings support in `print()` within threads
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‎tests/extension/thread_/print_fstrings/Makefile

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

‎tests/extension/thread_/print_fstrings/test_thread_print_fstrings.py

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from __future__ import absolute_import
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from __future__ import print_function
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import veriloggen
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import thread_print_fstrings
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expected_verilog = """
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module test
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(
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);
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reg CLK;
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reg RST;
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wire [8-1:0] LED;
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blinkled
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uut
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(
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.CLK(CLK),
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.RST(RST),
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.LED(LED)
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);
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initial begin
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CLK = 0;
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forever begin
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#5 CLK = !CLK;
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end
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end
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initial begin
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RST = 0;
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#100;
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RST = 1;
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#100;
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RST = 0;
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#50000;
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$finish;
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end
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endmodule
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module blinkled
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(
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input CLK,
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input RST,
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output reg [8-1:0] LED
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);
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reg [10-1:0] CNT;
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reg [32-1:0] th_blink;
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localparam th_blink_init = 0;
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localparam th_blink_1 = 1;
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localparam th_blink_2 = 2;
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localparam th_blink_3 = 3;
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localparam th_blink_4 = 4;
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localparam th_blink_5 = 5;
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localparam th_blink_6 = 6;
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localparam th_blink_7 = 7;
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localparam th_blink_8 = 8;
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localparam th_blink_9 = 9;
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localparam th_blink_10 = 10;
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localparam th_blink_11 = 11;
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always @(posedge CLK) begin
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if(RST) begin
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th_blink <= th_blink_init;
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LED <= 0;
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CNT <= 0;
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end else begin
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case(th_blink)
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th_blink_init: begin
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th_blink <= th_blink_1;
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end
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th_blink_1: begin
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$display("Hello, world!");
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th_blink <= th_blink_2;
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end
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th_blink_2: begin
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if(1) begin
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th_blink <= th_blink_3;
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end else begin
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th_blink <= th_blink_11;
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end
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end
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th_blink_3: begin
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LED <= LED + 1;
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th_blink <= th_blink_4;
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end
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th_blink_4: begin
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CNT <= CNT + 3;
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th_blink <= th_blink_5;
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end
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th_blink_5: begin
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if(LED % 70 == 0) begin
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th_blink <= th_blink_6;
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end else begin
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th_blink <= th_blink_10;
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end
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end
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th_blink_6: begin
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$display("");
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th_blink <= th_blink_7;
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end
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th_blink_7: begin
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$display("led = %0d (%b)", LED, LED);
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th_blink <= th_blink_8;
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end
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th_blink_8: begin
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$display("cnt = %0d (%b)", CNT, CNT);
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th_blink <= th_blink_9;
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end
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th_blink_9: begin
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$display("cnt + led = %d", (CNT + LED));
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th_blink <= th_blink_10;
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end
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th_blink_10: begin
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th_blink <= th_blink_2;
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end
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endcase
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end
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end
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endmodule
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"""
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def test():
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veriloggen.reset()
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test_module = thread_print_fstrings.mkTest()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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parser = VerilogParser()
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expected_ast = parser.parse(expected_verilog)
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codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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assert(expected_code == code)
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test()

‎tests/extension/thread_/print_fstrings/thread_print_fstrings.py

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
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os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
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from veriloggen import *
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import veriloggen.thread as vthread
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def mkLed():
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m = Module('blinkled')
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clk = m.Input('CLK')
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rst = m.Input('RST')
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led = m.OutputReg('LED', 8, initval=0)
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cnt = m.Reg('CNT', 10, initval=0)
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def blink():
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print('Hello, world!')
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while True:
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led.value += 1
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cnt.value += 3
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if led.value % 70 == 0:
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print()
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print('led = %0d (%b)' % (led, led))
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print(f'{cnt = :0d} ({cnt:b})')
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print(f'cnt + led = {cnt + led}')
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th = vthread.Thread(m, 'th_blink', clk, rst, blink)
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fsm = th.start()
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return m
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def mkTest():
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m = Module('test')
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# target instance
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led = mkLed()
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# copy paras and ports
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params = m.copy_params(led)
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ports = m.copy_sim_ports(led)
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clk = ports['CLK']
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rst = ports['RST']
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uut = m.Instance(led, 'uut',
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params=m.connect_params(led),
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ports=m.connect_ports(led))
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# vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
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# simulation.setup_waveform(m, uut, dumpfile=vcd_name)
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simulation.setup_clock(m, clk, hperiod=5)
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init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
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init.add(
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Delay(50000),
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Systask('finish'),
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)
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return m
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if __name__ == '__main__':
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test = mkTest()
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verilog = test.to_verilog('tmp.v')
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print(verilog)
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sim = simulation.Simulator(test)
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rslt = sim.run()
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print(rslt)

‎veriloggen/thread/compiler.py

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@@ -471,6 +471,25 @@ def _call_Name_print(self, node):
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formatstring_list.append(form)
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formatstring_list.append(" ")
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elif (sys.version_info >= (3, 6) and
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isinstance(arg, ast.JoinedStr)):
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# Formatted String Literals (f-strings) in print statement
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values, form = self._print_f_strings(arg)
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for value in values:
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if isinstance(value, fxd._FixedBase):
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if value.point >= 0:
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argvalues.append(vtypes.Div(vtypes.SystemTask('itor', value),
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1.0 * (2 ** value.point)))
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else:
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argvalues.append(vtypes.Times(value, 2 ** -value.point))
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else:
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argvalues.append(value)
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formatstring_list.append(form)
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formatstring_list.append(" ")
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elif isinstance(arg, ast.Tuple):
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for e in arg.elts:
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value = self.visit(e)
@@ -535,6 +554,27 @@ def _print_binop_mod(self, arg):
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form = arg.left.s
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return values, form
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def _print_f_strings(self, arg):
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values = []
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form = ''
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for val in arg.values:
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if isinstance(val, ast.Constant):
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form += val.value
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elif isinstance(val, ast.FormattedValue):
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values.append(self.visit(val.value))
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if val.format_spec:
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# no guarantee if a simulator accepts it or not
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if len(val.format_spec.values) == 1:
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# e.g. f"{reg0:x} {reg1:0b}"
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form += '%' + val.format_spec.values[0].value
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else:
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# do not allow nested f-strings
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raise SyntaxError('Illegal format_spec of f-strings')
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else:
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# interpret as integer by default
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form += '%d'
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return values, form
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def _call_Name_int(self, node):
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if len(node.args) > 1:
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raise TypeError(

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