Merge branch 'feature_axi_all_signals' into develop

Author: shtaxxx

README.md

@@ -69,7 +69,6 @@ sudo apt install iverilog
 - pytest: 3.2 or later
 - pytest-pythonpath: 0.7 or later
 - Pyverilog: 1.1.3 or later
-- IPgen: 1.0.1 or later
 
 ```
 pip3 install jinja2 pytest pytest-pythonpath pyverilog ipgen

README.rst

@@ -75,7 +75,6 @@ Requirements
 -  pytest: 3.2 or later
 -  pytest-pythonpath: 0.7 or later
 -  Pyverilog: 1.1.3 or later
--  IPgen: 1.0.1 or later
 
 ::
 

examples/simulation_verilator/test_simulation_verilator.py

@@ -16,46 +16,84 @@
   reg RST;
   wire [32-1:0] myaxi_awaddr;
   wire [8-1:0] myaxi_awlen;
+  wire [3-1:0] myaxi_awsize;
+  wire [2-1:0] myaxi_awburst;
+  wire [2-1:0] myaxi_awlock;
+  wire [4-1:0] myaxi_awcache;
+  wire [3-1:0] myaxi_awprot;
+  wire [4-1:0] myaxi_awqos;
+  wire [1-1:0] myaxi_awuser;
   wire myaxi_awvalid;
   reg myaxi_awready;
   wire [32-1:0] myaxi_wdata;
   wire [4-1:0] myaxi_wstrb;
   wire myaxi_wlast;
   wire myaxi_wvalid;
   reg myaxi_wready;
+  reg [2-1:0] myaxi_bresp;
+  reg myaxi_bvalid;
+  wire myaxi_bready;
   wire [32-1:0] myaxi_araddr;
   wire [8-1:0] myaxi_arlen;
+  wire [3-1:0] myaxi_arsize;
+  wire [2-1:0] myaxi_arburst;
+  wire [2-1:0] myaxi_arlock;
+  wire [4-1:0] myaxi_arcache;
+  wire [3-1:0] myaxi_arprot;
+  wire [4-1:0] myaxi_arqos;
+  wire [1-1:0] myaxi_aruser;
   wire myaxi_arvalid;
   reg myaxi_arready;
   reg [32-1:0] myaxi_rdata;
+  reg [2-1:0] myaxi_rresp;
   reg myaxi_rlast;
   reg myaxi_rvalid;
   wire myaxi_rready;
   wire [32-1:0] memory_awaddr;
   wire [8-1:0] memory_awlen;
+  wire [3-1:0] memory_awsize;
+  wire [2-1:0] memory_awburst;
+  wire [2-1:0] memory_awlock;
+  wire [4-1:0] memory_awcache;
+  wire [3-1:0] memory_awprot;
+  wire [4-1:0] memory_awqos;
+  wire [1-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
   wire [4-1:0] memory_wstrb;
   wire memory_wlast;
   wire memory_wvalid;
   reg memory_wready;
+  wire [2-1:0] memory_bresp;
+  reg memory_bvalid;
+  wire memory_bready;
   wire [32-1:0] memory_araddr;
   wire [8-1:0] memory_arlen;
+  wire [3-1:0] memory_arsize;
+  wire [2-1:0] memory_arburst;
+  wire [2-1:0] memory_arlock;
+  wire [4-1:0] memory_arcache;
+  wire [3-1:0] memory_arprot;
+  wire [4-1:0] memory_arqos;
+  wire [1-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
+  wire [2-1:0] memory_rresp;
   reg memory_rlast;
   reg memory_rvalid;
   wire memory_rready;
+  assign memory_bresp = 0;
+  assign memory_rresp = 0;
+  reg [32-1:0] _memory_fsm;
+  localparam _memory_fsm_init = 0;
   reg [8-1:0] _memory_mem [0:2**20-1];
 
   initial begin
     $readmemh("memimg_test_simulation_verilator.out", _memory_mem);
   end
 
-  reg [32-1:0] _memory_fsm;
-  localparam _memory_fsm_init = 0;
   reg [33-1:0] _write_count;
   reg [32-1:0] _write_addr;
   reg [33-1:0] _read_count;
@@ -67,6 +105,13 @@
   reg __memory_fsm_cond_211_2_1;
   assign memory_awaddr = myaxi_awaddr;
   assign memory_awlen = myaxi_awlen;
+  assign memory_awsize = myaxi_awsize;
+  assign memory_awburst = myaxi_awburst;
+  assign memory_awlock = myaxi_awlock;
+  assign memory_awcache = myaxi_awcache;
+  assign memory_awprot = myaxi_awprot;
+  assign memory_awqos = myaxi_awqos;
+  assign memory_awuser = myaxi_awuser;
   assign memory_awvalid = myaxi_awvalid;
   wire _tmp_0;
   assign _tmp_0 = memory_awready;
@@ -86,33 +131,64 @@
     myaxi_wready = _tmp_1;
   end
 
+  wire [2-1:0] _tmp_2;
+  assign _tmp_2 = memory_bresp;
+
+  always @(*) begin
+    myaxi_bresp = _tmp_2;
+  end
+
+  wire _tmp_3;
+  assign _tmp_3 = memory_bvalid;
+
+  always @(*) begin
+    myaxi_bvalid = _tmp_3;
+  end
+
+  assign memory_bready = myaxi_bready;
   assign memory_araddr = myaxi_araddr;
   assign memory_arlen = myaxi_arlen;
+  assign memory_arsize = myaxi_arsize;
+  assign memory_arburst = myaxi_arburst;
+  assign memory_arlock = myaxi_arlock;
+  assign memory_arcache = myaxi_arcache;
+  assign memory_arprot = myaxi_arprot;
+  assign memory_arqos = myaxi_arqos;
+  assign memory_aruser = myaxi_aruser;
   assign memory_arvalid = myaxi_arvalid;
-  wire _tmp_2;
-  assign _tmp_2 = memory_arready;
+  wire _tmp_4;
+  assign _tmp_4 = memory_arready;
 
   always @(*) begin
-    myaxi_arready = _tmp_2;
+    myaxi_arready = _tmp_4;
   end
 
+  wire [32-1:0] _tmp_5;
+  assign _tmp_5 = memory_rdata;
 
   always @(*) begin
-    myaxi_rdata = memory_rdata;
+    myaxi_rdata = _tmp_5;
   end
 
-  wire _tmp_3;
-  assign _tmp_3 = memory_rlast;
+  wire [2-1:0] _tmp_6;
+  assign _tmp_6 = memory_rresp;
 
   always @(*) begin
-    myaxi_rlast = _tmp_3;
+    myaxi_rresp = _tmp_6;
   end
 
-  wire _tmp_4;
-  assign _tmp_4 = memory_rvalid;
+  wire _tmp_7;
+  assign _tmp_7 = memory_rlast;
 
   always @(*) begin
-    myaxi_rvalid = _tmp_4;
+    myaxi_rlast = _tmp_7;
+  end
+
+  wire _tmp_8;
+  assign _tmp_8 = memory_rvalid;
+
+  always @(*) begin
+    myaxi_rvalid = _tmp_8;
   end
 
   assign memory_rready = myaxi_rready;
@@ -124,18 +200,36 @@
     .RST(RST),
     .myaxi_awaddr(myaxi_awaddr),
     .myaxi_awlen(myaxi_awlen),
+    .myaxi_awsize(myaxi_awsize),
+    .myaxi_awburst(myaxi_awburst),
+    .myaxi_awlock(myaxi_awlock),
+    .myaxi_awcache(myaxi_awcache),
+    .myaxi_awprot(myaxi_awprot),
+    .myaxi_awqos(myaxi_awqos),
+    .myaxi_awuser(myaxi_awuser),
     .myaxi_awvalid(myaxi_awvalid),
     .myaxi_awready(myaxi_awready),
     .myaxi_wdata(myaxi_wdata),
     .myaxi_wstrb(myaxi_wstrb),
     .myaxi_wlast(myaxi_wlast),
     .myaxi_wvalid(myaxi_wvalid),
     .myaxi_wready(myaxi_wready),
+    .myaxi_bresp(myaxi_bresp),
+    .myaxi_bvalid(myaxi_bvalid),
+    .myaxi_bready(myaxi_bready),
     .myaxi_araddr(myaxi_araddr),
     .myaxi_arlen(myaxi_arlen),
+    .myaxi_arsize(myaxi_arsize),
+    .myaxi_arburst(myaxi_arburst),
+    .myaxi_arlock(myaxi_arlock),
+    .myaxi_arcache(myaxi_arcache),
+    .myaxi_arprot(myaxi_arprot),
+    .myaxi_arqos(myaxi_arqos),
+    .myaxi_aruser(myaxi_aruser),
     .myaxi_arvalid(myaxi_arvalid),
     .myaxi_arready(myaxi_arready),
     .myaxi_rdata(myaxi_rdata),
+    .myaxi_rresp(myaxi_rresp),
     .myaxi_rlast(myaxi_rlast),
     .myaxi_rvalid(myaxi_rvalid),
     .myaxi_rready(myaxi_rready)
@@ -158,6 +252,7 @@
     RST = 0;
     memory_awready = 0;
     memory_wready = 0;
+    memory_bvalid = 0;
     memory_arready = 0;
     memory_rdata = 0;
     memory_rlast = 0;
@@ -180,18 +275,18 @@
     $write("");
   end
 
-  wire _tmp_5;
-  assign _tmp_5 = io_CLK;
+  wire _tmp_9;
+  assign _tmp_9 = io_CLK;
 
   always @(*) begin
-    CLK = _tmp_5;
+    CLK = _tmp_9;
   end
 
-  wire _tmp_6;
-  assign _tmp_6 = io_RST;
+  wire _tmp_10;
+  assign _tmp_10 = io_RST;
 
   always @(*) begin
-    RST = _tmp_6;
+    RST = _tmp_10;
   end
 
   localparam _memory_fsm_200 = 200;
@@ -241,8 +336,15 @@
       memory_rlast <= 0;
       __memory_fsm_cond_211_2_1 <= 0;
       memory_rdata <= 0;
+      memory_bvalid <= 0;
       _sleep_count <= 0;
     end else begin
+      if(memory_bvalid && memory_bready) begin
+        memory_bvalid <= 0;
+      end 
+      if(memory_wvalid && memory_wready && memory_wlast) begin
+        memory_bvalid <= 1;
+      end 
       _sleep_count <= _sleep_count + 1;
       if(_sleep_count == 3) begin
         _sleep_count <= 0;
@@ -276,7 +378,7 @@
           end 
         end
         _memory_fsm_100: begin
-          if(memory_awvalid) begin
+          if(memory_awvalid && !memory_bvalid) begin
             memory_awready <= 1;
             _write_addr <= memory_awaddr;
             _write_count <= memory_awlen + 1;
@@ -442,18 +544,36 @@
   input RST,
   output reg [32-1:0] myaxi_awaddr,
   output reg [8-1:0] myaxi_awlen,
+  output [3-1:0] myaxi_awsize,
+  output [2-1:0] myaxi_awburst,
+  output [2-1:0] myaxi_awlock,
+  output [4-1:0] myaxi_awcache,
+  output [3-1:0] myaxi_awprot,
+  output [4-1:0] myaxi_awqos,
+  output [1-1:0] myaxi_awuser,
   output reg myaxi_awvalid,
   input myaxi_awready,
   output reg [32-1:0] myaxi_wdata,
   output reg [4-1:0] myaxi_wstrb,
   output reg myaxi_wlast,
   output reg myaxi_wvalid,
   input myaxi_wready,
+  input [2-1:0] myaxi_bresp,
+  input myaxi_bvalid,
+  output myaxi_bready,
   output reg [32-1:0] myaxi_araddr,
   output reg [8-1:0] myaxi_arlen,
+  output [3-1:0] myaxi_arsize,
+  output [2-1:0] myaxi_arburst,
+  output [2-1:0] myaxi_arlock,
+  output [4-1:0] myaxi_arcache,
+  output [3-1:0] myaxi_arprot,
+  output [4-1:0] myaxi_arqos,
+  output [1-1:0] myaxi_aruser,
   output reg myaxi_arvalid,
   input myaxi_arready,
   input [32-1:0] myaxi_rdata,
+  input [2-1:0] myaxi_rresp,
   input myaxi_rlast,
   input myaxi_rvalid,
   output myaxi_rready
@@ -505,6 +625,21 @@
     .ram_c_0_wenable(ram_c_0_wenable)
   );
 
+  assign myaxi_awsize = 2;
+  assign myaxi_awburst = 1;
+  assign myaxi_awlock = 0;
+  assign myaxi_awcache = 3;
+  assign myaxi_awprot = 0;
+  assign myaxi_awqos = 0;
+  assign myaxi_awuser = 1;
+  assign myaxi_bready = 1;
+  assign myaxi_arsize = 2;
+  assign myaxi_arburst = 1;
+  assign myaxi_arlock = 0;
+  assign myaxi_arcache = 3;
+  assign myaxi_arprot = 0;
+  assign myaxi_arqos = 0;
+  assign myaxi_aruser = 1;
   reg _myaxi_read_start;
   reg [8-1:0] _myaxi_read_op_sel;
   reg [32-1:0] _myaxi_read_local_addr;

examples/thread_add_ipcore/Makefile

@@ -27,4 +27,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf *_v1_00_a
+	rm -rf *_v1_0