Merge branch 'rc-1.6.0' into develop

Author: shtaxxx

README.md

@@ -58,7 +58,7 @@ Veriloggen project always welcomes questions, bug reports, feature proposals, an
 
 ### for questions, bug reports, and feature proposals
 
-Please leave your comment on the [issue tracker](https://github.com/PyHDI/Veriloggen/issues) on GitHub.
+Please leave your comment on the [issue tracker](https://github.com/PyHDI/veriloggen/issues) on GitHub.
 
 ### for pull requests
 
@@ -84,34 +84,34 @@ Requirements
 sudo apt install iverilog
 ```
 
+- Pyverilog: 1.1.4 or later
 - Jinja2: 2.10 or later
-- pytest: 3.2 or later
-- pytest-pythonpath: 0.7 or later
-- Pyverilog: 1.1.3 or later
+- NumPy: 1.14 or later
 
 ```
-pip3 install jinja2 pytest pytest-pythonpath pyverilog ipgen
+pip3 install pyverilog jinja2 numpy
 ```
 
-Options
+Optional Installation
 --------------------
 
-- Graphviz: 2.38.0 or later
-- Pygraphviz: 1.3.1 or later
+- pytest: 3.2 or later
+- pytest-pythonpath: 0.7 or later
 
-These softwares are required for graph visualization by veriloggen.dataflow:
+These are required for the testing execution of test codes in tests and examples.
 
 ```
-sudo apt install graphviz
-pip3 install pygraphviz
+pip3 install pytest pytest-pythonpath
 ```
 
-- NumPy: 1.14 or later
+- Graphviz: 2.38.0 or later
+- Pygraphviz: 1.3.1 or later
 
-This is required for the memory image generation function of types.axi.AxiMemoryModel from Python list or numpy.ndarray:
+These are required for graph visualization by veriloggen.dataflow:
 
 ```
-pip3 install numpy
+sudo apt install graphviz
+pip3 install pygraphviz
 ```
 
 Install

README.rst

@@ -68,7 +68,7 @@ for questions, bug reports, and feature proposals
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Please leave your comment on the `issue
-tracker <https://github.com/PyHDI/Veriloggen/issues>`__ on GitHub.
+tracker <https://github.com/PyHDI/veriloggen/issues>`__ on GitHub.
 
 for pull requests
 ~~~~~~~~~~~~~~~~~
@@ -99,37 +99,36 @@ Requirements
 
    sudo apt install iverilog
 
+-  Pyverilog: 1.1.4 or later
 -  Jinja2: 2.10 or later
--  pytest: 3.2 or later
--  pytest-pythonpath: 0.7 or later
--  Pyverilog: 1.1.3 or later
+-  NumPy: 1.14 or later
 
 ::
 
-   pip3 install jinja2 pytest pytest-pythonpath pyverilog ipgen
+   pip3 install pyverilog jinja2 numpy
 
-Options
--------
+Optional Installation
+---------------------
 
--  Graphviz: 2.38.0 or later
--  Pygraphviz: 1.3.1 or later
+-  pytest: 3.2 or later
+-  pytest-pythonpath: 0.7 or later
 
-These softwares are required for graph visualization by
-veriloggen.dataflow:
+These are required for the testing execution of test codes in tests and
+examples.
 
 ::
 
-   sudo apt install graphviz
-   pip3 install pygraphviz
+   pip3 install pytest pytest-pythonpath
 
--  NumPy: 1.14 or later
+-  Graphviz: 2.38.0 or later
+-  Pygraphviz: 1.3.1 or later
 
-This is required for the memory image generation function of
-types.axi.AxiMemoryModel from Python list or numpy.ndarray:
+These are required for graph visualization by veriloggen.dataflow:
 
 ::
 
-   pip3 install numpy
+   sudo apt install graphviz
+   pip3 install pygraphviz
 
 Install
 -------

setup.py

@@ -23,10 +23,11 @@ def read(filename):
       packages=find_packages(),
       package_data={'veriloggen.utils': ['VERSION'],
                     'veriloggen.simulation': ['*.cpp'], },
-      install_requires=['pyverilog>=1.1.3', 'Jinja2>=2.10'],
+      install_requires=['pyverilog>=1.1.4',
+                        'Jinja2>=2.10',
+                        'numpy>=1.14'],
       extras_require={
-          'graph': ['pygraphviz>=1.3.1'],
           'test': ['pytest>=3.2', 'pytest-pythonpath>=0.7'],
-          'memimg': ['numpy>=1.14'],
+          'graph': ['pygraphviz>=1.3.1'],
       },
       )

veriloggen/__init__.py

@@ -1,9 +1,21 @@
-#-------------------------------------------------------------------------
-# Veriloggen: A library for constructing a Verilog HDL source code in Python
-#
-# Copyright (C) 2015, Shinya Takamaeda-Yamazaki
-# License: Apache 2.0
-#-------------------------------------------------------------------------
+"""
+   Veriloggen: A library for constructing a Verilog HDL source code in Python
+
+   Copyright 2015, Shinya Takamaeda-Yamazaki and Contributors
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
+"""
+
 from __future__ import absolute_import
 from __future__ import print_function
 

veriloggen/utils/VERSION

@@ -1 +1 @@
-1.5.4
+1.6.0