Refactor debugging interface to avoid cluttered clk_enable signals in submodules

[ChoiCube84]

Problem Description

We are currently implementing a CPU and testing it on an FPGA. In order to facilitate debugging, we've inserted clk_enable signals into various submodules, allowing the system to execute sequentially by pressing a button. This approach simplifies debugging but results in a less clean design and might make future modifications more difficult.

At the moment, there isn't a clear solution, and we are considering abstract approaches to improve the debugging interface.

Proposed Solution (Abstract)

• We plan to explore potential ways to implement a cleaner debugging interface that doesn't rely on the current clk_enable signals in each submodule.
• Ideas include centralizing the control of clock enables or using a more structured method for sequential execution that can be toggled easily for debugging purposes.
• The goal is to implement a more maintainable solution that doesn't compromise the code's clarity.

Future Improvement Plan

• Once we have more time, we will investigate alternative solutions for debugging that centralize or optimize clock enable logic.
• The current clk_enable signals are useful for debugging, but they need to be refined to avoid cluttering the submodules.
• We will revisit this problem to find a more elegant approach to debugging without introducing unnecessary complexity in the system design.