[libcpu-riscv]: [surpport SMP]: Support the SMP feature under the Smart framework/environment

By defining a custom .percpu section and controlling the MMU mapping page table entries,
different cores can access different physical memory when accessing the same virtual
address (percpu_hartid), thereby storing their respective hartids. If the satp register
is not used, the hartid is stored in the satp register.

Signed-off-by: Mengchen Teng <teng_mengchen@163.com>

Author: Tm-C-mT

bsp/qemu-virt64-riscv/driver/board.h

@@ -15,14 +15,14 @@
 
 extern unsigned int __bss_start;
 extern unsigned int __bss_end;
-
+extern unsigned int _end;
 #ifndef RT_USING_SMART
 #define KERNEL_VADDR_START 0x0
 #endif
 
 #define VIRT64_SBI_MEMSZ (0x200000)
 
-#define RT_HW_HEAP_BEGIN ((void *)&__bss_end)
+#define RT_HW_HEAP_BEGIN ((void *)&_end)
 #define RT_HW_HEAP_END   ((void *)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024))
 #define RT_HW_PAGE_START RT_HW_HEAP_END
 #define RT_HW_PAGE_END   ((void *)(KERNEL_VADDR_START + (256 * 1024 * 1024 - VIRT64_SBI_MEMSZ)))

bsp/qemu-virt64-riscv/link.lds

@@ -145,6 +145,24 @@ SECTIONS
     __bss_end = .;
     } > SRAM
 
+    .percpu (NOLOAD) :
+    {
+        /* Align for MMU early map */
+        . = ALIGN(1<<(12+9));
+        PROVIDE(__percpu_start = .);
+
+        *(.percpu)
+
+        /* Align for MMU early map */
+       . = ALIGN(1<<(12+9));
+
+        PROVIDE(__percpu_end = .);
+
+        /* Clone the area */
+        . = __percpu_end + (__percpu_end - __percpu_start) * (RT_CPUS_NR - 1);
+        PROVIDE(__percpu_real_end = .);
+    } > SRAM
+
     _end = .;
 
     /* Stabs debugging sections.  */

bsp/qemu-virt64-riscv/link_smart.lds

@@ -9,6 +9,7 @@
  */
 
 INCLUDE "link_stacksize.lds"
+INCLUDE "link_cpus.lds"
 
 OUTPUT_ARCH( "riscv" )
 
@@ -122,12 +123,9 @@ SECTIONS
     {
         . = ALIGN(64);
         __stack_start__ = .;
-
-        . += __STACKSIZE__;
-        __stack_cpu0 = .;
-
-        . += __STACKSIZE__;
-        __stack_cpu1 = .;
+        /* Dynamically allocate stack areas according to RT_CPUS_NR */
+        . += (__STACKSIZE__ * RT_CPUS_NR);
+        __stack_end__ = .;
     } > SRAM
 
     .sbss :
@@ -147,6 +145,24 @@ SECTIONS
         *(COMMON)
     __bss_end = .;
     } > SRAM
+    
+         .percpu (NOLOAD) :
+    {
+        /* Align for MMU early map */
+        . = ALIGN(1<<(12+9));
+        PROVIDE(__percpu_start = .);
+
+        *(.percpu)
+
+        /* Align for MMU early map */
+        . = ALIGN(1<<(12+9));
+
+        PROVIDE(__percpu_end = .);
+
+        /* Clone the area */
+        . = __percpu_end + (__percpu_end - __percpu_start) * (RT_CPUS_NR - 1);
+        PROVIDE(__percpu_real_end = .);
+    } > SRAM
 
     _end = .;
 

libcpu/risc-v/common64/context_gcc.S

@@ -93,9 +93,12 @@ rt_hw_context_switch_to:
     call rt_thread_self
     mv s1, a0
 
+#ifndef RT_USING_SMP
+    //if enable RT_USING_SMP, it will finished by rt_cpus_lock_status_restore.
     #ifdef RT_USING_SMART
-        call lwp_aspace_switch
+      call lwp_aspace_switch
     #endif
+#endif
 
     RESTORE_CONTEXT
     sret
@@ -134,9 +137,12 @@ rt_hw_context_switch:
     call rt_thread_self
     mv s1, a0
 
+#ifndef RT_USING_SMP
+    // if enable RT_USING_SMP, it will finished by rt_cpus_lock_status_restore.
     #ifdef RT_USING_SMART
-        call lwp_aspace_switch
+       call lwp_aspace_switch
     #endif
+#endif
 
     RESTORE_CONTEXT
     sret

libcpu/risc-v/common64/cpuport.c

@@ -18,6 +18,10 @@
 #include <sbi.h>
 #include <encoding.h>
 
+#ifdef ARCH_MM_MMU
+#include "mmu.h"
+#endif
+
 #ifdef RT_USING_SMP
 #include "tick.h"
 #include "interrupt.h"
@@ -54,6 +58,10 @@ volatile rt_ubase_t rt_interrupt_to_thread = 0;
  */
 volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
 
+#ifdef ARCH_MM_MMU
+static rt_ubase_t *percpu_hartid;
+#endif
+
 void *_rt_hw_stack_init(rt_ubase_t *sp, rt_ubase_t ra, rt_ubase_t sstatus)
 {
     rt_hw_switch_frame_t frame = (rt_hw_switch_frame_t)((rt_ubase_t)sp - sizeof(struct rt_hw_switch_frame));
@@ -71,10 +79,19 @@ int rt_hw_cpu_id(void)
 #ifndef RT_USING_SMP
     return 0;
 #else
-    /* Currently, the hartid is stored in the satp register. */
-    rt_ubase_t hart_id;
-    asm volatile("csrr %0, satp" : "=r"(hart_id));
-    return hart_id;
+    if (rt_kmem_pvoff() != 0)
+    {
+        return *percpu_hartid;
+    }
+    else
+    {
+        // if not enable MMU or pvoff==0, read hartid from satp register
+        rt_ubase_t hartid;
+        asm volatile("csrr %0, satp" : "=r"(hartid));
+        return hartid;
+    }
+    
+
 #endif /* RT_USING_SMP */
 }
 
@@ -170,11 +187,19 @@ void rt_hw_secondary_cpu_up(void)
     rt_uint64_t entry_pa;
     int hart, ret;
 
-    /* translate kernel virtual _start to physical address.
-     * TODO: Virtual-to-physical translation is not needed here
-     * because &_start is already a physical address on this platform.
-    */
+    /* translate kernel virtual _start to physical address. */
+#ifdef ARCH_MM_MMU
+    if (rt_kmem_pvoff() != 0)
+    {
+        entry_pa = (rt_uint64_t)rt_kmem_v2p(&_start);
+    }
+    else
+    {
+        entry_pa = (rt_uint64_t)&_start;
+    }
+#else
     entry_pa = (rt_uint64_t)&_start;
+#endif /* ARCH_MM_MMU */
 
     for (hart = 0; hart < RT_CPUS_NR; hart++)
     {
@@ -191,8 +216,31 @@ void rt_hw_secondary_cpu_up(void)
     }
 }
 
+#ifdef ARCH_MM_MMU
+void rt_hw_percpu_hartid_init(rt_ubase_t *percpu_ptr, rt_ubase_t hartid)
+{
+    rt_ubase_t *percpu_hartid_paddr;
+    rt_size_t percpu_size = (rt_size_t)((rt_ubase_t)&__percpu_end - (rt_ubase_t)&__percpu_start);
+    
+    percpu_hartid = percpu_ptr;
+
+    // from virtual address to physical address
+    percpu_ptr = (rt_ubase_t *)((rt_ubase_t)percpu_ptr + (rt_ubase_t)rt_kmem_pvoff());
+    percpu_hartid_paddr = percpu_ptr;
+    
+
+    /* Save to the real area */
+    *(rt_ubase_t *)((void *)percpu_hartid_paddr + hartid * percpu_size) = hartid;
+}
+#endif /* ARCH_MM_MMU */
+
 void secondary_cpu_entry(void)
 {
+    
+#ifdef RT_USING_SMART
+    /* switch to kernel address space */
+    rt_hw_aspace_switch(&rt_kernel_space);
+#endif
     /* The PLIC peripheral interrupts are currently handled by the boot_hart. */
     /* Enable the Supervisor-Timer bit in SIE */
     rt_hw_tick_init();

libcpu/risc-v/common64/cpuport.h

@@ -43,6 +43,10 @@ rt_inline void rt_hw_isb(void)
     __asm__ volatile(OPC_FENCE_I:::"memory");
 }
 
+#ifdef ARCH_MM_MMU
+void rt_hw_percpu_hartid_init(rt_ubase_t *percpu_ptr, rt_ubase_t hartid);
+#endif
+
 #endif
 
 #endif

libcpu/risc-v/common64/encoding.h

@@ -176,6 +176,8 @@
 #define PTE_A     0x040 // Accessed
 #define PTE_D     0x080 // Dirty
 #define PTE_SOFT  0x300 // Reserved for Software
+#define PTE_ATTR_RW         (PTE_R | PTE_W)
+#define PTE_ATTR_RWX        (PTE_ATTR_RW | PTE_X)
 
 #define PTE_PPN_SHIFT 10