[libcpu-riscv]: [surpport SMP]: Fix issues with non-standard formatting

Fix some potential concurrency issues and code standardization problems.
The .percpu section is only used when both ARCH_MM_MMU and RT_USING_SMP
are enabled. However, there is a certain amount of space waste since no
macro guard is added for it in the link script currently.
The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is
modified from the original +256MB to +128MB.

Signed-off-by: Mengchen Teng <teng_mengchen@163.com>

Author: Tm-C-mT

bsp/qemu-virt64-riscv/driver/board.h

@@ -15,17 +15,17 @@
 
 extern unsigned int __bss_start;
 extern unsigned int __bss_end;
-extern unsigned int _end;
+
 #ifndef RT_USING_SMART
 #define KERNEL_VADDR_START 0x0
 #endif
 
 #define VIRT64_SBI_MEMSZ (0x200000)
 
-#define RT_HW_HEAP_BEGIN ((void *)&_end)
+#define RT_HW_HEAP_BEGIN ((void *)&__bss_end)
 #define RT_HW_HEAP_END   ((void *)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024))
 #define RT_HW_PAGE_START RT_HW_HEAP_END
-#define RT_HW_PAGE_END   ((void *)(KERNEL_VADDR_START + (256 * 1024 * 1024 - VIRT64_SBI_MEMSZ)))
+#define RT_HW_PAGE_END   ((void *)(KERNEL_VADDR_START + (128 * 1024 * 1024 - VIRT64_SBI_MEMSZ)))
 
 void rt_hw_board_init(void);
 void rt_init_user_mem(struct rt_thread *thread, const char *name,

bsp/qemu-virt64-riscv/link.lds

@@ -136,32 +136,32 @@ SECTIONS
         *(.scommon)
     } > SRAM
 
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.dynbss)
-        *(COMMON)
-    __bss_end = .;
-    } > SRAM
-
     .percpu (NOLOAD) :
     {
-        /* Align for MMU early map */
-        . = ALIGN(1<<(12+9));
+        /* 2MB Align for MMU early map */
+        . = ALIGN(0x200000);
         PROVIDE(__percpu_start = .);
 
         *(.percpu)
 
-        /* Align for MMU early map */
-       . = ALIGN(1<<(12+9));
+        /* 2MB Align for MMU early map */
+        . = ALIGN(0x200000);
 
         PROVIDE(__percpu_end = .);
 
         /* Clone the area */
         . = __percpu_end + (__percpu_end - __percpu_start) * (RT_CPUS_NR - 1);
         PROVIDE(__percpu_real_end = .);
     } > SRAM
+    
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+    __bss_end = .;
+    } > SRAM
 
     _end = .;
 

bsp/qemu-virt64-riscv/link_smart.lds

@@ -137,25 +137,16 @@ SECTIONS
         *(.scommon)
     } > SRAM
 
-    .bss :
+    .percpu (NOLOAD) :
     {
-        *(.bss)
-        *(.bss.*)
-        *(.dynbss)
-        *(COMMON)
-    __bss_end = .;
-    } > SRAM
-    
-         .percpu (NOLOAD) :
-    {
-        /* Align for MMU early map */
-        . = ALIGN(1<<(12+9));
+        /* 2MB Align for MMU early map */
+        . = ALIGN(0x200000);
         PROVIDE(__percpu_start = .);
 
         *(.percpu)
 
-        /* Align for MMU early map */
-        . = ALIGN(1<<(12+9));
+        /* 2MB Align for MMU early map */
+        . = ALIGN(0x200000);
 
         PROVIDE(__percpu_end = .);
 
@@ -164,6 +155,15 @@ SECTIONS
         PROVIDE(__percpu_real_end = .);
     } > SRAM
 
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+    __bss_end = .;
+    } > SRAM
+
     _end = .;
 
     /* Stabs debugging sections.  */

bsp/qemu-virt64-riscv/run.sh

@@ -27,8 +27,9 @@ fi
 QEMU_CMD="qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin"
 
 if grep -q "#define RT_USING_SMP" ./rtconfig.h 2>/dev/null; then
-    hart_num=$(grep "RT_CPUS_NR = [0-9]*;" ./link_cpus.lds | awk -F'[=;]' '{gsub(/ /, "", $2); print $2}')
-    if [ -z "$hart_num" ]; then
+    hart_num=$(grep "RT_CPUS_NR = [0-9]*;" ./link_cpus.lds 2>/dev/null | awk -F'[=;]' '{gsub(/ /, "", $2); print $2}')
+    if [ -z "$hart_num" ] || [ "$hart_num" -lt 1 ]; then
+        echo "Warning: Invalid or missing RT_CPUS_NR, defaulting to 1"
         hart_num=1
     fi
     QEMU_CMD="$QEMU_CMD -smp $hart_num"

libcpu/risc-v/common64/context_gcc.S

@@ -82,10 +82,7 @@ rt_hw_context_switch_to:
     LOAD sp, (a0)
 
 #ifdef RT_USING_SMP
-    /*
-     * Pass the previous CPU lock status to 
-     * rt_cpus_lock_status_restore for restoration 
-     */ 
+    /* Pass the previous CPU lock status to rt_cpus_lock_status_restore for restoration */
     mv   a0,   a1
     call  rt_cpus_lock_status_restore
 #endif
@@ -125,10 +122,7 @@ rt_hw_context_switch:
     LOAD sp, (a1)
 
 #ifdef RT_USING_SMP
-    /*
-     * Pass the previous CPU lock status to 
-     * rt_cpus_lock_status_restore for restoration 
-     */ 
+    /* Pass the previous CPU lock status to rt_cpus_lock_status_restore for restoration */
     mv   a0,   a2
     call  rt_cpus_lock_status_restore
 #endif /*RT_USING_SMP*/

libcpu/risc-v/common64/cpuport.c

@@ -88,7 +88,7 @@ int rt_hw_cpu_id(void)
         // if not enable MMU or pvoff==0, read hartid from satp register
         rt_ubase_t hartid;
         asm volatile("csrr %0, satp" : "=r"(hartid));
-        return hartid;
+        return hartid & 0xFFFF;  // Assuming hartid fits in lower 16 bits
     }
 #endif /* RT_USING_SMP */
 }
@@ -198,7 +198,8 @@ void rt_hw_secondary_cpu_up(void)
 #else
     entry_pa = (rt_uint64_t)&_start;
 #endif /* ARCH_MM_MMU */
-
+    /* Assumes hart IDs are in range [0, RT_CPUS_NR) */
+    RT_ASSERT(boot_hartid < RT_CPUS_NR);
     for (hart = 0; hart < RT_CPUS_NR; hart++)
     {
         if (hart == boot_hartid)
@@ -217,6 +218,7 @@ void rt_hw_secondary_cpu_up(void)
 #ifdef ARCH_MM_MMU
 void rt_hw_percpu_hartid_init(rt_ubase_t *percpu_ptr, rt_ubase_t hartid)
 {
+    RT_ASSERT(hartid < RT_CPUS_NR);
     rt_ubase_t *percpu_hartid_paddr;
     rt_size_t percpu_size = (rt_size_t)((rt_ubase_t)&__percpu_end - (rt_ubase_t)&__percpu_start);
 

libcpu/risc-v/common64/mmu.c

@@ -38,7 +38,7 @@
 
 static size_t _unmap_area(struct rt_aspace *aspace, void *v_addr);
 
-// Define the structure of early page table
+/* Define the structure of early page table */
 struct page_table
 {
     unsigned long page[ARCH_PAGE_SIZE / sizeof(unsigned long)];
@@ -120,7 +120,7 @@ static int _map_one_page(struct rt_aspace *aspace, void *va, void *pa,
     l1_off = GET_L1((size_t)va);
     l2_off = GET_L2((size_t)va);
     l3_off = GET_L3((size_t)va);
-    // create map for each hart
+    /* Create a separate page table for each hart to facilitate access to the .percpu section. */
     for (int hartid = 0; hartid < RT_CPUS_NR; hartid++)
     {
         mmu_l1 = (rt_ubase_t *)((rt_ubase_t)aspace->page_table + (rt_ubase_t)(hartid * ARCH_PAGE_SIZE)) + l1_off;
@@ -345,11 +345,12 @@ void set_free_page(void *page_array)
 // Early-stage page allocator
 unsigned long get_free_page(void)
 {
-    static unsigned long page_off = 0UL;
+    static rt_atomic_t page_off = 0;
 
-    if (page_off < ARCH_PAGE_SIZE / sizeof(unsigned long))
+    rt_atomic_t old_off = rt_hw_atomic_add(&page_off, 1);
+    if (old_off < ARCH_PAGE_SIZE / sizeof(unsigned long))
     {
-        return (unsigned long)(__init_page_array[page_off++].page);
+        return (unsigned long)(__init_page_array[old_off].page);
     }
 
     return 0;
@@ -860,10 +861,6 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
 
 #define SATP_BASE ((rt_ubase_t)SATP_MODE << SATP_MODE_OFFSET)
 
-extern unsigned int __bss_end;
-#if defined(RT_USING_SMP) && defined(ARCH_MM_MMU)
-extern unsigned int __percpu_real_end;
-#endif
 /**
  * @brief Early memory setup function for hardware initialization.
  *

libcpu/risc-v/common64/startup_gcc.S

@@ -34,7 +34,7 @@ _start:
     la t0, boot_hartid                /* global varible rt_boot_hartid */
 #ifdef RT_USING_SMP
     lw   t2, (t0)
-    li   t3, 0xdeadbeef
+    li   t3, 0xdeadbeef               /* Sentinel value indicating uninitialized boot_hartid */
     li   t4, 0xffffffff
     and  t2, t2, t4                   /* Extract the lower 32 bits. */
     bne  t2, t3, system_init          /* If the current value is 0xdeadbeef, skip the boot_hartid assignment operation. */
@@ -46,9 +46,14 @@ _start:
 system_init:
 #endif
 
-    /* If ARCH_MM_MMU is not enabled or pvoff==0, save the hartid in the satp register;
-     * otherwise, save it in percpu_hartid.
-    */
+    /*
+     * When ARCH_MM_MMU is not enabled or pvoff==0:
+     * Store hartid temporarily in the satp register because:
+     * 1. satp is not used for address translation when MMU is disabled or pvoff==0.
+     * 2. This value will be moved to percpu_hartid once MMU is initialized.
+     * This approach avoids using extra memory or registers during the critical boot phase,
+     * but developers should be aware that satp is overloaded for this purpose until MMU setup.
+     */
     csrw satp, a0
 
     /* clear Interrupt Registers */
@@ -134,7 +139,7 @@ system_init:
     call init_bss
 early_secondary_cpu_entry:
 #ifdef ARCH_MM_MMU
-    // Pages need to be managed manually in the early stage.
+    // Manually manage pages in the early stage
     la      a0, .early_page_array
     call    set_free_page
 
@@ -206,12 +211,14 @@ _start_link_addr:
     .dword __text_start
 
 #ifdef ARCH_MM_MMU
+#ifdef RT_USING_SMP
 /*
  * CPU stack builtin
  */
     .section ".percpu"
 .percpu_hartid:
     .space 16
+#endif
 
     .section ".bss"
 

libcpu/risc-v/virt64/interrupt.c

@@ -226,13 +226,13 @@ void rt_hw_ipi_handler(void)
         ipi_vector &= ~(1 << bitpos);
         if (bitpos < RT_MAX_IPI && ipi_desc[bitpos].handler != RT_NULL)
         {
+            rt_hw_atomic_and((volatile rt_atomic_t *)&ipi_vectors[rt_cpu_get_id()], ~((rt_atomic_t)(1 << bitpos)));
             /* call the irq service routine */
             ipi_desc[bitpos].handler(bitpos, ipi_desc[bitpos].param);
         }
     }
-    ipi_vectors[rt_cpu_get_id()] = 0;
 
-    // clear software interrupt pending bit
+    // TODO: Clear the software interrupt pending bit in CLINT
     clear_csr(sip, SIP_SSIP);
 }
 #endif /* RT_USING_SMP */