Nested addrmap - supported with regblock ?

[galaviel]

Hi,
I'm trying to create an 'addrmap' component that is the top-level of the chip.
It instantiates sub-addrmap's for each sub-unit of the chip. (each such internal 'addrmap' instantiates one or more regfiles. the internal addrmap is what I would like to get RTL generated for).

Is this supported?
Will PeakRDL-regblock know to dive into the internal 'addrmap' and generate RTL for each of them?

Do I need to write a custom exporter to handle the chip's top level addrmap?
any ideas are welcome.
(perhaps I should convert the internal 'addrmap' components to nested regfiles.. I'll try that as well)

Thanks, Gal.

[amykyta3]

I would actually recommend approaching this slightly differently: Call peakrdl regblock separately, multiple times, once per block.

Consider the following example:

addrmap device_a {
    ...
};

addrmap device_b {
    ...
};

addrmap device_c {
    ...
};

addrmap chip_top {
    device_a A @ 0x1_0000;
    device_b B @ 0x1_1000;
    device_c[16] C @ 0x2_0000 += 0x1000;
};

Assuming devices A, B, and C all require their own regblock export, do the following from your command-line:

peakrdl regblock <input files> --top device_a ...
peakrdl regblock <input files> --top device_b ...
peakrdl regblock <input files> --top device_c ...

The remaining chip_top addrmap is not used in any export other than for documentation purposes (peakrdl html?) for the chip's memory layout.
Also, if your RDL files are split apart such that each device is defined in separate files, you may be able to simply feed each invocation of peakrdl the smaller subset of the files, and omit the --top flag.
Here are a few more details regarding how --top works: https://peakrdl.readthedocs.io/en/latest/processing-input.html#top-level-elaboration

[RasmusGOlsen]

How would you do the actual address mapping from the register description to your RTL implementation? Don't you need to compile and elaborate the entire address map to get the address offset for each device instance?

[galaviel]

my guess / assumption is that inside each sub-unit you've specified only the relative addresses of registers in that unit (relative to the unit's base address), for example you have 50 registers each 32-bit wide, this means you'll need 8-bits of byte resolution address to access those registers. So the emitted RTL only needs to consider and decode the 8-lower address bits, regardless of the absolute base address of the sub-unit itself.

[galaviel]

in other words, when integrating the regblock in your RTL, you can connect only the 8-bit ms-bits of the master's address to the regblock (the ms-bits can be driven as constant 1'b0 / zero padded). If that makes sense.

[RasmusGOlsen]

However, you still need a way to assign the base address, perform address decoding, and select the device. What I am failing to understand is how chip_top offsets are mapped to each device's base address when you integrate the generated Verilog code. To get these offsets, you need to compile and elaborate the complete address map. That information also needs to be available in Verilog. I cannot see how that is done with the current code template.

[amykyta3]

@galaviel has the right idea. The general philosophy is that each individual register block only knows its local addressing. This lets each block be re-used multiple times at different global address offsets. The PeakRDL-regblock output will already prune the MSb's of the address to accomplish this implicitly. See this section of the docs for more details: https://peakrdl-regblock.readthedocs.io/en/latest/cpuif/introduction.html#addressing

Global address mapping is accomplished by the system interconnect that maps these peripherals. If using Xilinx/AMD FPGAs, this would be the SmartConnect device, or similar for Altera. For ASICs, this would be your system interconnect or NoC.
Longer-term, I do have plans for a PeakRDL extension that will generate 1-to-N bus decoders to cover the more simple use-cases without having to resort to the more heavyweight interconnect IPs.

[galaviel]

Excellent! --top is what I was looking for (also 'peakrdl globals' in the documentation link is a great tip. I might use that).

Also, I restructured my RDL such that at the unit level, the component is a 'regfile' rather than an 'addrmap' (and indeed this regfile may contain other regfiles - which is what I need - one regfile for the actual regs, and the other - the registers of a common safety engine all our regfiles must instantiate). So this way I only have one addrmap in the chip.

Again thanks allot!