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| 1 | +.. _lpm_modes_socoff: |
| 2 | + |
| 3 | +############### |
| 4 | +Low power modes |
| 5 | +############### |
| 6 | + |
| 7 | +******** |
| 8 | +Overview |
| 9 | +******** |
| 10 | + |
| 11 | +The following sections describe a high-level description of the different low power modes (LPM) supported on J7200 and J784S4 SOC. |
| 12 | +These modes are validated on TI EVMs. Selection of low power modes need to be done at build time, So user must decide, which low power mode meets the requirements. |
| 13 | +Each mode needs evaluation based on power consumption and latency (the time it takes to wake-up to Active mode) requirements. |
| 14 | +In SDK offering, following low power modes are supported: |
| 15 | + |
| 16 | +#. SOC OFF |
| 17 | +#. I/O Only Plus DDR |
| 18 | + |
| 19 | +******* |
| 20 | +SOC OFF |
| 21 | +******* |
| 22 | + |
| 23 | +In SOC OFF low-power mode, partial SW context (Mainly HLOS Linux) is retained in DDR while the SOC is turned off. This can save a significant amount of boot time, because it does not reinitialize whole kernel as it is already present in DDR. |
| 24 | + |
| 25 | +The benefits of using SOC OFF in embedded devices: |
| 26 | + |
| 27 | +#. Faster wake-up: devices can wake-up from this low-power state much faster than |
| 28 | + a complete power cycle. |
| 29 | +#. Better efficiency: This mode can help to improve the efficiency of embedded devices by |
| 30 | + reducing the amount of time that the processor is idle. This is because the processor can |
| 31 | + be kept in a low-power state when it is not needed. |
| 32 | + |
| 33 | +In order to enter SOC OFF, use the following command: |
| 34 | + |
| 35 | + .. code-block:: console |
| 36 | +
|
| 37 | + root@<machine>-evm:~# echo mem > /sys/power/state |
| 38 | + [ 18.380346] PM: suspend entry (deep) |
| 39 | + [ 18.576999] Filesystems sync: 0.193 seconds |
| 40 | + [ 18.587643] Freezing user space processes |
| 41 | + [ 18.593191] Freezing user space processes completed (elapsed 0.001 seconds) |
| 42 | + [ 18.600179] OOM killer disabled. |
| 43 | + [ 18.603395] Freezing remaining freezable tasks |
| 44 | + [ 18.608964] Freezing remaining freezable tasks completed (elapsed 0.001 seconds) |
| 45 | + [ 18.616364] printk: Suspending console(s) (use no_console_suspend to debug) |
| 46 | +
|
| 47 | +This indicates that linux has finished its suspend sequence. |
| 48 | + |
| 49 | +To exit from SOC OFF, |
| 50 | + |
| 51 | +.. ifconfig:: CONFIG_part_variant in ('J7200') |
| 52 | + |
| 53 | + Press SW12 push button on J7200 evm. |
| 54 | + |
| 55 | +.. ifconfig:: CONFIG_part_variant in ('J784S4') |
| 56 | + |
| 57 | + Press SW15 push button on J784S4 evm. |
| 58 | + |
| 59 | +***************** |
| 60 | +I/O Only Plus DDR |
| 61 | +***************** |
| 62 | + |
| 63 | +In I/O Only Plus DDR, only the I/O pins are active while the rest of the SoC is turned off. |
| 64 | + |
| 65 | +#. Low power consumption: IO Only mode can save a significant amount of power, especially in battery-powered |
| 66 | + devices. This is because the DDR is in self-refresh and except the IO pins, rest of the SOC is turned off. |
| 67 | +#. Better efficiency: I/O Only Plus DDR mode can help to improve the efficiency of embedded devices by reducing |
| 68 | + the amount of time that the processor is idle. This is because the processor can be kept in a low-power state when it is not needed. |
| 69 | +#. Respond to external wakeup sources: This allows the system to still respond to external events, while it is in a low-power state and wakeup faster improving boot time. |
| 70 | + |
| 71 | + |
| 72 | +.. ifconfig:: CONFIG_part_variant in ('J7200') |
| 73 | + |
| 74 | + To enter I/O only mode, Enable edge sensitive wakeup for MCAN1_RX pin by writing to PADCONFIG_11 (0x0011C02C) |
| 75 | + |
| 76 | + .. code-block:: console |
| 77 | +
|
| 78 | + # devmem2 0x0011C02C w 0x20050000 |
| 79 | + # echo mem > /sys/power/state |
| 80 | +
|
| 81 | +.. ifconfig:: CONFIG_part_variant in ('J784S4') |
| 82 | + |
| 83 | + To enter I/O only mode, Enable level sensitive wakeup for MCU_MCAN0_RX pin by writing to WKUP_PADCONFIG_47 (at address 0x4301C0BC) |
| 84 | + |
| 85 | + .. code-block:: console |
| 86 | +
|
| 87 | + # devmem2 0x4301C0BC w 0x20050180 |
| 88 | + # echo mem > /sys/power/state |
| 89 | +
|
| 90 | +
|
| 91 | +.. code-block:: console |
| 92 | +
|
| 93 | + root@<machine>-evm:~# echo mem > /sys/power/state |
| 94 | + [ 18.380346] PM: suspend entry (deep) |
| 95 | + [ 18.576999] Filesystems sync: 0.193 seconds |
| 96 | + [ 18.587643] Freezing user space processes |
| 97 | + [ 18.593191] Freezing user space processes completed (elapsed 0.001 seconds) |
| 98 | + [ 18.600179] OOM killer disabled. |
| 99 | + [ 18.603395] Freezing remaining freezable tasks |
| 100 | + [ 18.608964] Freezing remaining freezable tasks completed (elapsed 0.001 seconds) |
| 101 | + [ 18.616364] printk: Suspending console(s) (use no_console_suspend to debug) |
| 102 | +
|
| 103 | +To exit from IO_ONLY_PLUS_DDR, |
| 104 | + |
| 105 | +.. ifconfig:: CONFIG_part_variant in ('J7200') |
| 106 | + |
| 107 | + Press SW1 push button on J7200 SOM |
| 108 | + |
| 109 | +.. ifconfig:: CONFIG_part_variant in ('J784S4') |
| 110 | + |
| 111 | + The second pin-out of J33 is MCU_MCAN0_RX [3] and it is directly connected to the SOC [2] |
| 112 | + 3.3V should be applied on that pin to wake it up from low power. |
| 113 | + |
| 114 | +.. note:: |
| 115 | + |
| 116 | + All low power mode supported implies all low power mode supported by the firmware as per firmware |
| 117 | + capabilities. `TISCI_MSG_QUERY_FW_CAPS <https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-msg-query-fw-caps>`__ |
| 118 | + can be sent to firmware to get the low power modes supported by firmware. |
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