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Merge pull request #5450 from YosysHQ/emil/dff-next_state-reset-pol-fix
dfflibmap: fix next_state inversion propagation for DFF flops by inve…
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+62
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passes/techmap/dfflibmap.cc

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@@ -271,6 +271,13 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
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continue;
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol) || (has_enable && (cell_enable_pin.empty() || cell_enable_pol != enapol)))
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continue;
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if (has_reset && !cell_next_pol) {
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// next_state is negated
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// we later propagate this inversion to the output,
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// which requires the negation of the reset value
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rstval = !rstval;
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}
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if (has_reset && rstval == false) {
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if (!parse_pin(cell, ff->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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@@ -0,0 +1,24 @@
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library (test_not_next) {
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cell (dff_not_next) {
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area: 1.0;
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pin (QN) {
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direction : output;
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function : "STATE";
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}
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pin (CLK) {
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direction : input;
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clock : true;
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}
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pin (D) {
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direction : input;
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}
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pin (RN) {
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direction : input;
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}
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ff (STATE, STATEN) {
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clocked_on: "CLK";
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next_state: "!D";
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preset : "!RN";
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}
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}
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}

tests/techmap/dfflibmap_formal.ys

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@@ -108,6 +108,37 @@ copy top top_unmapped
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simplemap top
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dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
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async2sync
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct equiv
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equiv_status -assert equiv
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##################################################################
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design -reset
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read_verilog <<EOT
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module top(input C, D, R, output Q);
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// DFF with preset
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always @(posedge C or negedge R) begin
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if (!R) Q <= 1'b1;
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else Q <= D;
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end
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffn_dffe.lib
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read_liberty dfflibmap_dff_not_next.lib
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copy top top_unmapped
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simplemap top
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dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dff_not_next.lib top
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async2sync
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flatten
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opt_clean -purge

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