diff --git a/README.md b/README.md index 565f8b3..10f5ded 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,10 @@ -# NES for Analogue Pocket +# NES for Analogue Pocket with Analogizer Support Ported from the core originally developed by [Ludvig Strigeus](https://github.com/strigeus/fpganes) and heavily developed by [@sorgelig](https://github.com/sorgelig), [@greyrogue](https://github.com/greyrogue), [@Kitrinx](https://github.com/Kitrinx), [@paulb-nl](https://github.com/paulb-nl), and many more. Core icon by [spiritualized1997](https://github.com/spiritualized1997). Latest upstream available at https://github.com/MiSTer-devel/NES_MiSTer Please report any issues encountered to this repo. Most likely any problems are a result of my port, not the original core. Issues will be upstreamed as necessary. -## Installation +## Installation (see also Analogizer settings section) ### Easy mode @@ -17,25 +17,25 @@ To install the core, copy the `Assets`, `Cores`, and `Platform` folders over to ROMs should be placed in `/Assets/nes/common` -PAL ROMs should boot, but there will be timing and sound issues as the core currently doesn't properly support PAL (proper support coming soon). I highly recommend you do not play PAL games, and instead use NTSC games (if they exist) at this time. +PAL ROMs are supported with proper timing and sound pitch. The NES ROM headers should be at least iNES2.0 version to correctly identify the ROM region. NES ROMs with legacy header or marked as MultiSystem will be +booted as NTSC. ## Features ### Dock Support -Core supports four players/controllers via the Analogue Dock. To enable four player mode, turn on `Use Multitap` setting. +Core supports four players/controllers via the Analogue Dock. To enable four player mode, turn on `Use Multitap` setting. This is also required to enable to use the Analogizer SNAC PCEngine Multitap. ### Mappers -This core has pairity with the MiSTer core's mapper support. [See the full breakdown here](https://github.com/MiSTer-devel/NES_MiSTer#supported-mappers). Please note that the VRC7 expansion audio chip is not supported in this core (but is in MiSTer) due to space constraints. +This core has pairity with the MiSTer core's mapper support. [See the full breakdown here](https://github.com/MiSTer-devel/NES_MiSTer#supported-mappers). ### Save States/Sleep + Wake Known as "Memories" on the Pocket, this core supports the creation and loading of save states for most mappers. See the full list in the [Mappers section](#mappers). By extension, the core supports Sleep + Wake functionality on the Pocket. In games with supported mappers, tapping the power button while playing will suspend the game, ready to be resumed when powering the Pocket back on. -### Saves - -Supports saves for most games and mappers. Saving on the NES is rather complicated due to the different scenarios for different mappers, so it's possible some less common mappers do not save correctly on this core. Please report all such issues to this repo. +### Save States/Sleep + Wake and Saves +Are supported. ### Controller Turbo @@ -69,10 +69,14 @@ You can load external palettes as well. This palette is stored at `Assets/nes/ag For testing, or to temporarily load a new palette, you can choose the `Load Custom Palette` option (make sure to choose `Core Settings/Palette/Custom`). This palette selection is temporary, and will be reset when quitting and reopening the core. +### Analogizer Options + +* `Enable Analogizer`- Enables/Disables the Analogizer adapter globall. When it is disabled, bypass the specific settings for Analogizer, this settings makes the SNAC adapter settings be ignored, using Pocket's default inputs, also forces the video output to be forwarded towards Pocket screen. +* ### Video Options There are several options provided for tweaking the displayed video: - +* `Video Dejitter` - Intended for use with Analogizer video output with a CRT screen to mimick the real behaviour of the NES. Disable it for use with the Pocket screen, the Dock output or Video Scalers as the OSSC. * `Hide Overscan` - Hides the top and bottom 8 pixels of the video, which would normally be masked by the CRT. Adjusts the aspect ratio to correspond with this modification. This option does nothing in PAL mode * `Edge Masking` - Masks the sides of the screen in black, depending on the chosen option. The auto setting automatically masks the left side when certain conditions are met. * `Square Pixels` - The internal resolution of the NES is a 8:7 pixel aspect ratio (wide pixels), which roughly corresponds to what users would see on 4:3 display aspect ratio CRTs. Some games are designed to be displayed at 8:7 PAR (the core's default), and others at 1:1 PAR (square pixels). The `Square Pixels` option is provided to switch to a 1:1 pixel aspect ratio. @@ -80,6 +84,129 @@ There are several options provided for tweaking the displayed video: ### Lightguns -Core supports virtual lightguns by enabling the "Use Zapper" setting. The crosshair can be controlled with the D-Pad or left joystick, using the A button to fire. D-Pad aim sensitivity can be adjusted with the "D-Pad Aim Speed" setting. +Core supports virtual lightguns by enabling the `Use Zapper > Emulated Zapper (Stick)` setting. The crosshair can be controlled with the D-Pad or left joystick, using the A button to fire. D-Pad aim sensitivity can be adjusted with the "D-Pad Aim Speed" setting. In addition, the Analogizer core version supports directly connecting the Zapper gun using a SNAC NES adapter by enabling the `Use Zapper > SNAC Zapper` setting **NOTE:** Joystick support for aiming only appears to work when a controller is paired over Bluetooth and not connected to the Analogue Dock directly by USB. + +### Analogizer settings + +This Analogizer core use a configuration file to select Analogizer adapter options, not based on the Pocket's menu system. It is necessary to use [Pupdate](https://github.com/mattpannella/pupdate) release >= 4.3.1 or run an external [utility](https://github.com/RndMnkIII/AnalogizerConfigurator) to generate such a file. Once generated, you must copy the `analogizer.bin` file to the `/Assets/analogizer/common` folder on the Pocket SD card. If this folder does not exist, you must create it or if you have already extracted the Amiga core distribution file it will be created. Pupdate does all actions automatically after running this tool. Inside Pupdate navigate to: `Pocket Setup>Analogizer Config>Standard Analogizer Config`, choose Analogizer settings and exit to save to file. + +For the PAL/NTSC/Dendy ROM detection the Chip32 loader reads the NES game ROM header previously to load the core to decode the system type, this needs a iNES2.0 ROM header. If the ROM that are you using is of an older header type or not `analogizer.bin` file is detected the core will boot into NTSC mode. + +The Loader uses the regional settings from `analogizer.bin`file to determine the mode the ROM is loaded/NES hardware runs. +The settings are: + 1) Auto>NTSC: Try to autodetect the regional setting from the ROM header. If the ROM is `Multi-System` uses the NTSC mode. + 2) Auto>PAL: Try to autodetect the regional setting from the ROM header. If the ROM is `Multi-System` uses the PAL mode. + 3) Auto>Another: Try to autodetect the regional setting from the ROM header. If the ROM is `Multi-System` uses the Dendy mode. + 4) Force NTSC: The ROM uses the NTSC mode. + 5) Force PAL: The ROM uses the PAL mode. + 6) Force Another: The ROM uses the Dendy mode. + +Tested NES SNAC adapters working with the Zapper lightgun: +* https://ultimatemister.com/product/ultimate-snac-mini-hdmi/ +* Blue212 based design (uses two board, a common board and console specific connector board). https://manuferhi.com/p/snac-adapter-for-mister with the [two port NES](https://www.etsy.com/de-en/listing/1556489601/mister-fpga-snac-adapter-nes-2p) connector or [one port](https://www.etsy.com/de-en/listing/1781156747/mister-snac-adapter-nes-vertical). Any SNAC adapter based on Blue212 design will be work. + +Recomended settings inside Pupdate (PocketSetup>Analogizer Config>Standard Analogizer Config) for use the NES Zapper lightgun with a NES SNAC adapter: +``` +SNAC Controller: NES - Nintendo Entertainment System gamepad +SNAC Assigments: SNAC P1,P2 -> Pocket P1,P2 +``` + +Recomended settings with NES Core Pocket menu for use the NES Zapper lightgun with a NES SNAC adapter: +``` +Use Zapper > SNAC Zapper +``` + +Connect the Zapper to the second port of the NES SNAC adapter (if you have the two ports version) or to the first port (if you have the one port version). + +For use with PSX Analog stick emulating the reticle lightgun. Use this settings inside Pupdate (PocketSetup>Analogizer Config>Standard Analogizer Config): +``` +SNAC Controller: PSX (Analog PAD) - PlayStation 1/2 analog gamepad +SNAC Assigments: SNAC P1,P2 -> Pocket P1,P2 +``` + +Recomended settings with NES Core Pocket menu for use the NES Zapper lightgun with a NES SNAC adapter: +``` +Use Zapper > Emulated Zapper (Stick) +``` + +Use the PSX game controller connected to the first port of th PSX SNAC adapter. + +Analogizer support added by RndMnkIII. See more in the Analogizer main repository: [Analogizer](https://github.com/RndMnkIII/Analogizer) + +Adapted to Analogizer by [@RndMnkIII](https://github.com/RndMnkIII) based on **agg23** NES for Analogue Pocket: +https://github.com/agg23/openfpga-NES + +The core can output RGBS, RGsB, YPbPr, Y/C and SVGA scandoubler (50% scanlines) video signals. +| Video output | Status | SOG Switch(Only R2,R3 Analogizer) | +| :----------- | :----: | :-------------------------------: | +| RGBS | ✅ | Off | +| RGsB | ✅ | On | +| YPbPr | ✅🔹 | On | +| Y/C NTSC | ✅ | Off | +| Y/C PAL | ✅ | Off | +| Scandoubler | ✅ | Off | + +🔹 Tested with Sony PVM-9044D + +| :SNAC game controller: | Analogizer A/B config Switch | Status | +| :---------------------- | :--------------------------- | :----: | +| DB15 | A | ✅ | +| NES/Zapper | A | ✅ | +| SNES | A | ✅ | +| PCENGINE | A | ✅ | +| PCE MULTITAP | A | ✅ | +| PSX DS/DS2 Digital DPAD | B | ✅ | +| PSX DS/DS2 Analog DPAD | B | ✅ | + +The Analogizer interface allow to mix game inputs from compatible SNAC gamepads supported by Analogizer (DB15 Neogeo, NES, SNES, PCEngine, PSX) with Analogue Pocket built-in controls or from Dock USB or wireless supported controllers (Analogue support). + +All Analogizer adapter versions (v1, v2 and v3) has a side slide switch labeled as 'A B' that must be configured based on the used SNAC game controller. +For example for use it with PSX Dual Shock or Dual Shock 2 native gamepad you must position the switch lever on the B side position. For the remaining +game controllers you must switch the lever on the A side position. +Be careful when handling this switch. Use something with a thin, flat tip such as a precision screwdriver with a 2.0mm flat blade for example. Place the tip on the switch lever and press gently until it slides into the desired position: + +``` + --- + B|O |A A/B switch on position B + --- + --- + B| O|A A/B switch on position A + --- +``` + +* **Analogizer** is responsible for generating the correct encoded Y/C signals from RGB and outputs to R,G pins of VGA port. Also redirects the CSync to VGA HSync pin. +The required external Y/C adapter that connects to VGA port is responsible for output Svideo o composite video signal using his internal electronics. Oficially +only the Mike Simone Y/C adapters (active) designs will be supported by Analogizer and will be the ones to use. +However, depending on the type of screen you have, passive Y/C adapters could work with different degrees of success. + +Support native PCEngine/TurboGrafx-16 2btn, 6 btn gamepads and 5 player multitap using SNAC adapter +and PC Engine cable harness (specific for Analogizer). Many thanks to [Mike Simone](https://github.com/MikeS11/MiSTerFPGA_YC_Encoder) for his great Y/C Encoder project. + +You will need to connect an active VGA to Y/C adapter to the VGA port (the 5V power is provided by VGA pin 9). I'll recomend one of these (active): +* [MiSTerAddons - Active Y/C Adapter](https://misteraddons.com/collections/parts/products/yc-active-encoder-board/) +* [MikeS11 Active VGA to Composite / S-Video](https://ultimatemister.com/product/mikes11-active-composite-svideo/) +* [Active VGA->Composite/S-Video adapter](https://antoniovillena.com/product/mikes1-vga-composite-adapter/) + +Using another type of Y/C adapter not tested to be used with Analogizer will not receive official support. + +### Build & Install instructions (Windows): + +1) Install Quartus 21.1 (x64) +2) Add to the system or user Path: \quartus\bin64 + clone the project files: git clone +3) Open a PowerShell terminal to project folder openfpga-NES + +4) Generate the four bitstreams files running the scripts: + .\build.ps1 NTSC_SET1 + .\build.ps1 NTSC_SET2 + .\build.ps1 PAL_SET1 + .\build.ps1 PAL_SET2 + + The generated *.rev bitstream files are stored in the 'core_bitstreams' folder +6) Copy the contents from 'pkg\pocket' folder to the root of Pocket SD Card. +5) Copy the bitstream files from 'core_bitstreams' to the Core folder 'Cores\agg23.NES' in the Pocket SD Card. + + + diff --git a/analogizer/analogizer.qip b/analogizer/analogizer.qip new file mode 100644 index 0000000..6577529 --- /dev/null +++ b/analogizer/analogizer.qip @@ -0,0 +1,14 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) openFPGA_Pocket_Analogizer.v] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) vga_out_sw.v] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) openFPGA_Pocket_Analogizer_SNAC.sv] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) clock_divider_fract.v] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) serlatch_gc.v] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pcengine_gc.v] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pcengine_game_controller_multitap.v] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler_2.v] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines_analogizer.v] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) dualshock_controller.v] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) analogizer_psx.sv] diff --git a/analogizer/analogizer_psx.sv b/analogizer/analogizer_psx.sv new file mode 100644 index 0000000..a7cc86e --- /dev/null +++ b/analogizer/analogizer_psx.sv @@ -0,0 +1,210 @@ + +// convert dualshock to Analogizer Analogue Pocket format +// @RndMnkIII. 11/2024 +//Analogue pocket format +//key1 +// Pocket logic button order: +// [0] dpad_up +// [1] dpad_down +// [2] dpad_left +// [3] dpad_right +// [4] face_a +// [5] face_b +// [6] face_x +// [7] face_y +// [8] trig_l1 +// [9] trig_r1 +// [10] trig_l2 +// [11] trig_r2 +// [12] trig_l3 +// [13] trig_r3 +// [14] face_select +// [15] face_start +// [28:16] +// [31:28] type: +// Type Field (4 bits) Description +// 0x0 Nothing connected +// 0x1 Pocket built-in buttons (only possible on Player 1) +// 0x2 Docked game controller, no analog support +// 0x3 Docked game controller, analog support +// 0x4 Docked keyboard +// 0x5 Docked mouse +// 0x7-0xF Reserved +//JOY +// [31:0] joy +// [ 7: 0] lstick_x +// [15: 8] lstick_y +// [23:16] rstick_x +// [31:24] rstick_y + +module analogizer_psx #(parameter MASTER_CLK_FREQ=50_000_000) ( + input i_clk, + input i_rst, + input i_ena, + input i_stb, + //Pocket control interface + output reg [15:0] key1, + output reg [31:0] joy1, + output reg [15:0] key2, + output reg [31:0] joy2, + //PSX INTERFACE + + input [1:0] i_VIB_SW1, // Vibration SW VIB_SW[0] Small Moter OFF 0:ON 1: + //VIB_SW[1] Bic Moter OFF 0:ON 1(Dualshook Only) + input [7:0] i_VIB_DAT1, // Vibration(Bic Moter)Data 8'H00-8'HFF (Dualshook Only) + input [1:0] i_VIB_SW2, + input [7:0] i_VIB_DAT2, + output PSX_CLK, + input PSX_DAT, + output PSX_CMD, + output PSX_ATT1, + output PSX_ATT2, + input PSX_ACK, + //output PSX_IRQ + output wire [3:0] DBG_TX +); + logic [7:0] rx0, rx1, rx2, rx3, rx4, rx5, rx6; + logic [7:0] RXD_ID; + reg att1r, att2r; + //reg [3:0] id1, id2; + reg no_gamepad; + //reg send_bytes1_stb, send_bytes2_stb; + + always @(posedge i_clk) begin + no_gamepad <= (&RXD_ID) & (&rx0); //both are FF no device detected + att1r <= PSX_ATT1; + att2r <= PSX_ATT2; + //send_bytes1_stb <= 0; + //send_bytes2_stb <= 0; + + if (~att1r & PSX_ATT1) begin //capture when ATT1 becomes idle + //send_bytes1_stb <= 1; + + if(no_gamepad) begin //no gamepad detected, default data + key1 <= 16'h00; + joy1 <= 32'h80808080; //neutral position + end + else + begin + // START SELECT R3 L3 R2 L2 R1 L1 Y X B A LEFT RIGHT DOWN UP + key1 <= {~rx1[3], ~rx1[0],~rx1[2],~rx1[1],~rx2[1],~rx2[0],~rx2[3],~rx2[2],~rx2[7],~rx2[4],~rx2[6],~rx2[5],~rx1[5],~rx1[7],~rx1[6],~rx1[4]}; + // rstick_y rstick_x lstick_y lstick_x + joy1 <= {rx4,rx3,rx6,rx5}; + end + end + else if(~att2r & PSX_ATT2) begin //capture when ATT2 becomes idle + //send_bytes2_stb <= 1; + + if(no_gamepad) begin //no gamepad detected, default data + key2 <= 16'h00; + joy2 <= 32'h80808080; //neutral position + end + else + begin + // START SELECT R3 L3 R2 L2 R1 L1 Y X B A LEFT RIGHT DOWN UP + key2 <= {~rx1[3], ~rx1[0],~rx1[2],~rx1[1],~rx2[1],~rx2[0],~rx2[3],~rx2[2],~rx2[7],~rx2[4],~rx2[6],~rx2[5],~rx1[5],~rx1[7],~rx1[6],~rx1[4]}; + // rstick_y rstick_x lstick_y lstick_x + joy2 <= {rx4,rx3,rx6,rx5}; + end + end + end + //assign DBG_TX = {PSX_ATT1,PSX_CLK,PSX_CMD,PSX_DAT}; //r_Tx_DV; + //assign DBG_TX = {dbgtx,dbgtx,dbgtx,1'b0}; + assign DBG_TX = {4'b0000}; + // Dualshock controller + + dualshock_controller #(.FREQ(MASTER_CLK_FREQ)) ds1 ( + .clk(i_clk), .i_RSTn(~i_rst), .i_ena(i_ena), .i_stb(i_stb), + .i_MULTITAP_ena(1'b0), .i_VIB_SW1(i_VIB_SW1), .i_VIB_DAT1(i_VIB_DAT1), .i_VIB_SW2(i_VIB_SW2), .i_VIB_DAT2(i_VIB_DAT2), + .o_psCLK(PSX_CLK), .o_ATT1(PSX_ATT1), .o_ATT2(PSX_ATT2), .o_psTXD(PSX_CMD), + .i_psRXD(PSX_DAT), .i_psACK(PSX_ACK), + .o_RXD_ID(RXD_ID), .o_RXD_0(rx0), + .o_RXD_1(rx1), .o_RXD_2(rx2), .o_RXD_3(rx3), + .o_RXD_4(rx4), .o_RXD_5(rx5), .o_RXD_6(rx6) + ); + + //debug as UART TX at 500000bps +// wire [7:0] lut[15:0]; +// +// assign lut[0]=8'h30; // ascii 0 +// assign lut[1]=8'h31; // ascii 1 +// assign lut[2]=8'h32; // ascii 2 +// assign lut[3]=8'h33; // ascii 3 +// assign lut[4]=8'h34; // ascii 4 +// assign lut[5]=8'h35; // ascii 5 +// assign lut[6]=8'h36; // ascii 6 +// assign lut[7]=8'h37; // ascii 7 +// assign lut[8]=8'h38; // ascii 8 +// assign lut[9]=8'h39; // ascii 9 +// assign lut[10]=8'h41; // ascii A +// assign lut[11]=8'h42; // ascii B +// assign lut[12]=8'h43; // ascii C +// assign lut[13]=8'h44; // ascii D +// assign lut[14]=8'h45; // ascii E +// assign lut[15]=8'h46; // ascii F +// +// reg r_Tx_DV; +// wire w_Tx_Done; +// reg [7:0] r_Tx_Byte; +// reg r_Rx_Serial; +// +// //cycle bytes to send +// reg [5:0] byte_cnt; +// +// always @(posedge i_clk) begin +// r_Tx_DV <= 1'b0; +// if(~i_rst) begin +// byte_cnt <= 6'd0; +// r_Tx_DV <= 1'b0; +// end +// else begin +// if(send_bytes1_stb || send_bytes2_stb) begin +// byte_cnt <= 6'd1; +// r_Tx_DV <= 1'b1; +// end +// else begin +// if ((byte_cnt < 6'd27) && w_Tx_Done) begin +// byte_cnt <= byte_cnt + 6'd1; +// r_Tx_DV <= 1'b1; +// end +// end +// end +// end +// +// always@(*) begin +// case(byte_cnt) +// 6'd01: r_Tx_Byte = "R"; +// 6'd02: r_Tx_Byte = "x"; +// 6'd03: r_Tx_Byte = ":"; +// 6'd04: r_Tx_Byte = lut[RXD_ID[7:4]]; +// 6'd05: r_Tx_Byte = lut[RXD_ID[3:0]]; +// 6'd07: r_Tx_Byte = lut[rx0[7:4]]; +// 6'd08: r_Tx_Byte = lut[rx0[3:0]]; +// 6'd10: r_Tx_Byte = lut[rx1[7:4]]; +// 6'd11: r_Tx_Byte = lut[rx1[3:0]]; +// 6'd13: r_Tx_Byte = lut[rx2[7:4]]; +// 6'd14: r_Tx_Byte = lut[rx2[3:0]]; +// 6'd16: r_Tx_Byte = lut[rx3[7:4]]; +// 6'd17: r_Tx_Byte = lut[rx3[3:0]]; +// 6'd19: r_Tx_Byte = lut[rx4[7:4]]; +// 6'd20: r_Tx_Byte = lut[rx4[3:0]]; +// 6'd22: r_Tx_Byte = lut[rx5[7:4]]; +// 6'd23: r_Tx_Byte = lut[rx5[3:0]]; +// 6'd25: r_Tx_Byte = lut[rx6[7:4]]; +// 6'd26: r_Tx_Byte = lut[rx6[3:0]]; +// 6'd27: r_Tx_Byte = 8'h0D; //carriage return +// default: r_Tx_Byte = " "; +// endcase +// end + + //i_clk 48_000_000 +// wire dbgtx; +// uart_tx #(.CLKS_PER_BIT(96)) UART_TX_INST +// (.i_Clock(i_clk), +// .i_Tx_DV(r_Tx_DV), //enable to send byte +// .i_Tx_Byte(r_Tx_Byte), +// .o_Tx_Active(), +// .o_Tx_Serial(dbgtx), +// .o_Tx_Done(w_Tx_Done) +// ); +endmodule \ No newline at end of file diff --git a/analogizer/clock_divider_fract.v b/analogizer/clock_divider_fract.v new file mode 100644 index 0000000..ae48802 --- /dev/null +++ b/analogizer/clock_divider_fract.v @@ -0,0 +1,17 @@ +`timescale 1ns / 1ps + +module clock_divider_fract ( + input wire i_clk, + input wire i_rst, + input wire [31:0] i_step, + output reg o_stb +); + reg [31:0] counter=33'd0; + + always @(posedge i_clk) begin + if(i_rst) //synchronous reset + counter <= 32'd0; + else + {o_stb,counter} <= counter + i_step; + end +endmodule \ No newline at end of file diff --git a/analogizer/csync.v b/analogizer/csync.v new file mode 100644 index 0000000..21c584d --- /dev/null +++ b/analogizer/csync.v @@ -0,0 +1,34 @@ +module csync +( + input clk, + input hsync, + input vsync, + + output csync +); + +assign csync = (csync_vs ^ csync_hs); + +reg csync_hs, csync_vs; +always @(posedge clk) begin + reg prev_hs; + reg [15:0] h_cnt, line_len, hs_len; + + // Count line/Hsync length + h_cnt <= h_cnt + 1'd1; + + prev_hs <= hsync; + if (prev_hs ^ hsync) begin + h_cnt <= 0; + if (hsync) begin + line_len <= h_cnt - hs_len; + csync_hs <= 0; + end + else hs_len <= h_cnt; + end + + if (~vsync) csync_hs <= hsync; + else if(h_cnt == line_len) csync_hs <= 1; + + csync_vs <= vsync; +end \ No newline at end of file diff --git a/analogizer/dualshock_controller.v b/analogizer/dualshock_controller.v new file mode 100644 index 0000000..d9e8622 --- /dev/null +++ b/analogizer/dualshock_controller.v @@ -0,0 +1,365 @@ +//------------------------------------------------------------------- +// +// PLAYSTATION CONTROLLER(DUALSHOCK TYPE) INTERFACE TOP +// +// Version : 2.00 +// +// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved +// +// Important ! +// +// This program is freeware for non-commercial use. +// An author does no guarantee about this program. +// You can use this under your own risk. +// +// 2003.10.30 It is optimized . by K Degawa +// 2023.12 nand2mario: rewrite without ripple clocks to improve stability +// remove fine-grained vibration control as we don't use it +// 2024.11 RndMnkIII: added capability to read two controllers using two ATT signals +// check when there is a game controller connected +// +//------------------------------------------------------------------- +`timescale 100ps/10ps + +// Protocol: https://store.curiousinventor.com/guides/PS2/ +// - Full duplex (command and data at the same time) +// - On negedge of clock, the line start to change. +// On posedge, values are read. +// - Command 0x01 0x42(cmd) 0x00 0x00 0x00 +// Data 0xFF 0x41 0x5A 0xFF(btns) 0xFF(btns) +// ^- mode + # of words + +//--------- SIMULATION ---------------------------------------------- +//`define SIMULATION_1 +// +// Poll controller status every 2^Timer clock cycles +// 125Khz / 2^11 = 61Hz +// +// SONY PLAYSTATION® CONTROLLER INFORMATION +// https://gamesx.com/controldata/psxcont/psxcont.htm +// +// "The DS4 stock polling rate is 250Hz 3-4 ms compared to the SN30 which is 67-75Hz 13-18 ms" +// https://www.reddit.com/r/8bitdo/comments/u8z3ag/has_anyone_managed_to_get_their_controllers/ +`ifdef SIMULATION_1 +`define Timer_siz 18 +`else +`define Timer_siz 11 +`endif + +module dualshock_controller #( + parameter FREQ // frequency of `clk` +) ( + input clk, // Any main clock faster than 1Mhz + input i_RSTn, // MAIN RESET + input i_ena, // Enable operation of the module + input i_stb, + //PSX interface + input i_MULTITAP_ena, + input [1:0] i_VIB_SW1, // Vibration SW VIB_SW[0] Small Moter OFF 0:ON 1: + // VIB_SW[1] Bic Moter OFF 0:ON 1(Dualshook Only) + input [7:0] i_VIB_DAT1, // Vibration(Bic Moter)Data 8'H00-8'HFF (Dualshook Only) + input [1:0] i_VIB_SW2, + input [7:0] i_VIB_DAT2, + output o_psCLK, // psCLK CLK OUT + output o_ATT1, // ATT1 OUT + output o_ATT2, // ATT1 OUT + output o_psTXD, // psTXD OUT + input i_psRXD, // psRXD IN + input i_psACK, //ACK + + //vibration control + output reg [7:0] o_RXD_ID, // RX DEVICE ID (UPPER NIBBLE) AND PAYLOAD SIZE (LOWER NIBBLE) + output reg [7:0] o_RXD_0, + output reg [7:0] o_RXD_1, // RX DATA 1 (8bit) + output reg [7:0] o_RXD_2, // RX DATA 2 (8bit) + output reg [7:0] o_RXD_3, // RX DATA 3 (8bit) + output reg [7:0] o_RXD_4, // RX DATA 4 (8bit) + output reg [7:0] o_RXD_5, // RX DATA 5 (8bit) + output reg [7:0] o_RXD_6 // RX DATA 6 (8bit) +); + +reg i_CLK ; // SPI clock at 125Khz + // some cheap controllers cannot handle the nominal 250Khz +reg R_CE, F_CE ; // rising and falling edge pulses of i_CLK + +// Generate i_CLK, F_CE, R_CE +always @(posedge clk) begin + //clk_cnt <= clk_cnt + 1; + //if(i_ena)clk_cnt <= clk_cnt + 1; + R_CE <= 0; + F_CE <= 0; + //if (clk_cnt == CLK_DELAY-1) begin + if (i_stb && i_ena) begin + i_CLK <= ~i_CLK; + R_CE <= ~i_CLK; + F_CE <= i_CLK; + //clk_cnt <= 0; + end +end + +reg ack_r/* synthesis noprune */; +always @(posedge clk) begin + if (i_stb && i_ena) begin + ack_r <= i_psACK; + end +end + +reg device_id_type ; //1'b1 digital one, 1'b0 analog one +always @(posedge clk) begin + if(! i_RSTn) device_id_type <= 1'b0; + else if (W_byte_cnt == 2) begin + case(o_RXD_ID) + 8'h23: device_id_type <= 1'b1; + 8'h41: device_id_type <= 1'b0; + 8'h53: device_id_type <= 1'b1; + 8'h73: device_id_type <= 1'b1; + 8'hE3: device_id_type <= 1'b1; + 8'hF3: device_id_type <= 1'b1; + 8'h80: device_id_type <= 1'b1; //multitap + default: device_id_type <= 1'b0; + endcase + end +end + +wire W_type = 1'b1 ; // DIGITAL PAD 0, ANALOG PAD 1 +wire [3:0] W_byte_cnt ; +wire W_RXWT ; +wire W_TXWT ; +wire W_TXEN ; +wire W_TXSET ; +reg [7:0]W_TXD_DAT /* synthesis noprune */; +wire [7:0]W_RXD_DAT ; + +ps_pls_gan pls( + .clk(clk), .R_CE(R_CE), .i_CLK(i_CLK), .i_RSTn(i_RSTn), .i_TYPE(device_id_type), + .o_RXWT(W_RXWT), .o_TXWT(W_TXWT), + .o_TXEN(W_TXEN), .o_psCLK(o_psCLK), + .o_ATT1(o_ATT1), .o_ATT2(o_ATT2), .o_byte_cnt(W_byte_cnt) +); + +ps_txd txd( + .clk(clk), .F_CE(F_CE), .i_RSTn(i_RSTn), + .i_WT(W_TXWT), .i_EN(W_TXEN), .i_TXD_DAT(W_TXD_DAT), .o_psTXD(o_psTXD) +); + +ps_rxd rxd( + .clk(clk), .R_CE(R_CE), .i_RSTn(i_RSTn), + .i_WT(W_RXWT), .i_psRXD(i_psRXD), .o_RXD_DAT(W_RXD_DAT) +); + +// TX command generation +always @* begin + case(W_byte_cnt) + 0: W_TXD_DAT = 8'h01; + 1: W_TXD_DAT = 8'h42; + 2: W_TXD_DAT = (i_MULTITAP_ena) ? 8'h01 : 8'h00; + // 3: W_TXD_DAT = 8'h00; // or vibration command + // 4: W_TXD_DAT = 8'h00; // or vibration command + 3: W_TXD_DAT = (~o_ATT1)? i_VIB_SW1[0] : ((~o_ATT2)? i_VIB_SW2[0] :8'h00 ); // or vibration command + 4: W_TXD_DAT = (~o_ATT1 && i_VIB_SW1[1])? i_VIB_DAT1 : ((~o_ATT2 && i_VIB_SW2[1])? i_VIB_DAT1 :8'h00 ); // or vibration command + default: W_TXD_DAT = 8'h00; + endcase +end + +// RX data decoding +//ID DESCRIPTION PAYLOAD_SIZE (half dwords) +// 1 Mouse 2 +// 9 Lightspan Keyboard SCPH-2000 6 +// 4 Digital Controller SCPH-1010 1 +// 5 Analog Joystick SCPH-1110 (Analog Mode) 3 +// 5 Dual Analog SCPH-1180 (Green LED mode) 3 +// 7 Dual Analog & Dual Shock 1/2 (Analog Mode) 3-8 +// 8 MultiTap disabled: based on device ID connected, enabled: 16 (4x8) + +reg W_RXWT_r ; + +always @(posedge clk) begin + W_RXWT_r <= W_RXWT; + if (~W_RXWT && W_RXWT_r) begin // record received value one cycle after RXWT + case (W_byte_cnt) + 1: o_RXD_ID <= W_RXD_DAT; + 2: o_RXD_0 <= W_RXD_DAT; + 3: o_RXD_1 <= W_RXD_DAT; + 4: o_RXD_2 <= W_RXD_DAT; + 5: o_RXD_3 <= W_RXD_DAT; + 6: o_RXD_4 <= W_RXD_DAT; + 7: o_RXD_5 <= W_RXD_DAT; + 8: o_RXD_6 <= W_RXD_DAT; + default:; + endcase + end +end + +endmodule + + +// timing signal generation module +module ps_pls_gan( + input clk, + input R_CE, + input i_CLK, + input i_RSTn, + input i_TYPE, + + output o_RXWT, // pulse to input RX byte + output o_TXWT, // pulse to output TX byte + output o_TXSET, + output o_TXEN, + output o_psCLK, // SPI clock to send to controller + output o_ATT1, // 0: active + output o_ATT2, // 0: active + output [3:0] o_byte_cnt // index for byte received +); + +parameter Timer_size = `Timer_siz; + +reg [3:0] o_byte_cnt_r ; +reg [`Timer_siz-1:0] Timer ; +reg RXWT, TXWT, TXSET ; +reg psCLK_gate ; // 0: send i_CLK on wire +reg psATT1 ; +reg psATT2 ; + +// increment timer on i_CLK rising edge +always @(posedge clk) begin + if (~i_RSTn) + Timer <= 0; + else if (R_CE) + Timer <= Timer+1; +end + +always @(posedge clk) begin + if (~i_RSTn) begin + psCLK_gate <= 1; + RXWT <= 0; + TXWT <= 0; + TXSET <= 0; + end else begin + TXWT <= 0; + RXWT <= 0; + TXSET <= 0; + if (R_CE) begin + case (Timer[4:0]) + 6: TXSET <= 1; + 9: TXWT <= 1; // pulse to set byte to send + 12: psCLK_gate <= 0; // send 8 cycles of clock: + 20: begin + psCLK_gate <= 1; // 13,14,15,16,17,18,19,20 + RXWT <= 1; // pulse to get received byte + end + default:; + endcase + end + end +end + +always @(posedge clk) begin + if (~i_RSTn) begin + psATT1 <= 1; + psATT2 <= 1; + end + else if (R_CE) begin + if (Timer[9:0] == 0) begin + psATT1 <= Timer[10]; //switch each 2^10 R_CE cycles + psATT2 <= ~Timer[10]; + end + else if ((i_TYPE == 0)&&(Timer[9:0] == 158)) begin// end of byte 4 + psATT1 <= 1; + psATT2 <= 1; + end + else if ((i_TYPE == 1)&&(Timer[9:0] == 286)) begin // end of byte 9 + psATT1 <= 1; + psATT2 <= 1; + end + + end +end + +always @(posedge clk) begin // update o_byte_cnt_r + if (!i_RSTn) + o_byte_cnt_r <= 0; + else if (R_CE) begin + if (Timer[9:0] == 0) + o_byte_cnt_r <= 0; + else begin + if (Timer[4:0] == 31) begin // received a byte + if (i_TYPE == 0 && o_byte_cnt_r == 5) + o_byte_cnt_r <= o_byte_cnt_r; + else if (i_TYPE == 1 && o_byte_cnt_r == 9) + o_byte_cnt_r <= o_byte_cnt_r; + else + o_byte_cnt_r <= o_byte_cnt_r + 4'd1; + end + end + end +end + +assign o_psCLK = psCLK_gate | i_CLK | ~(psATT1 ^ psATT2); +assign o_ATT1 = psATT1; +assign o_ATT2 = psATT2; +assign o_RXWT = (~psATT1 | ~psATT2) & RXWT; +assign o_TXSET = (~psATT1 | ~psATT2) & TXSET; +assign o_TXWT = (~psATT1 | ~psATT2) & TXWT; +assign o_TXEN = (~psATT1 | ~psATT2) & ~psCLK_gate; +assign o_byte_cnt = o_byte_cnt_r; + +endmodule + +// receiver +module ps_rxd( + input clk, + input R_CE, // one bit is transmitted on rising edge + input i_RSTn, + input i_WT, // pulse to output byte to o_RXD_DAT + input i_psRXD, + output reg [7:0] o_RXD_DAT +); + +reg [7:0] sp; + +always @(posedge clk) + if (~i_RSTn) begin + sp <= 1; + o_RXD_DAT <= 1; + end else begin + if (R_CE) // posedge i_CLK + sp <= { i_psRXD, sp[7:1]}; + if (i_WT) + o_RXD_DAT <= sp; + end + +endmodule + +// transmitter +module ps_txd ( + input clk, + input F_CE, // transmit on falling edge of i_CLK + input i_RSTn, + input i_WT, // pulse to load data to transmit + input i_EN, // 1 to do transmission + input [7:0] i_TXD_DAT, // byte to transmit, lowest bit first + output reg o_psTXD // output pin +); + +reg [7:0] ps; // data buffer + +always @(posedge clk) begin + if (~i_RSTn) begin + o_psTXD <= 1; + ps <= 0; + end else begin + if (i_WT) + ps <= i_TXD_DAT; + if (F_CE) begin // bit is sent on falling edge of i_CLK + if (i_EN) begin + o_psTXD <= ps[0]; + ps <= {1'b1, ps[7:1]}; + end else begin + o_psTXD <= 1'd1; + ps <= ps; + end + end + end +end + +endmodule \ No newline at end of file diff --git a/analogizer/hq2x.sv b/analogizer/hq2x.sv new file mode 100644 index 0000000..e70c9c5 --- /dev/null +++ b/analogizer/hq2x.sv @@ -0,0 +1,371 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017,2018 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// altera message_off 10030 + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + + input ce_in, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + + input ce_out, + input [1:0] read_y, + input hblank, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = $clog2(LENGTH)-1; +localparam DWIDTH = HALF_DEPTH ? 11 : 23; +localparam DWIDTH1 = DWIDTH+1; + +(* romstyle = "M10K" *) reg [5:0] hqTable[256]; +initial begin + hqTable = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 + }; +end + +wire [5:0] hqrule = hqTable[nextpatt]; + +reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2; +reg [23:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] cyc; + +reg curbuf; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G; +wire [23:0] blend_result_pre; +Blend blender(clk, ce_in, disable_hq2x ? 6'd0 : hqrule, Curr0, X, B, D, F, H, blend_result_pre); + +wire [DWIDTH:0] Curr20tmp; +wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp; +wire [DWIDTH:0] Curr21tmp; +wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [23:0] h2rgb; + input [11:0] v; +begin + h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]}; +end +endfunction + +function [11:0] rgb2h; + input [23:0] v; +begin + rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(offs), + .rdbuf0(prevbuf), + .rdbuf1(curbuf), + .q0(Curr20tmp), + .q1(Curr21tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [AWIDTH+1:0] read_x; +reg [AWIDTH+1:0] wrout_addr; +reg wrout_en; +reg [DWIDTH1*4-1:0] wrdata, wrdata_pre; +wire [DWIDTH1*4-1:0] outpixel_x4; +reg [DWIDTH1*2-1:0] outpixel_x2; + +assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0]; + +hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out +( + .clock(clk), + + .rdaddress({read_x[AWIDTH+1:1],read_y[1]}), + .q(outpixel_x4), + + .data(wrdata), + .wraddress(wrout_addr), + .wren(wrout_en) +); + +always @(posedge clk) begin + if(ce_out) begin + if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0]; + if(~hblank & ~&read_x) read_x <= read_x + 1'd1; + if(hblank) read_x <= 0; + end +end + +wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0]; + +reg [AWIDTH:0] offs; +always @(posedge clk) begin + reg old_reset_line; + reg old_reset_frame; + reg [3:0] wrdata_finished; + reg [AWIDTH+1:0] waddr; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_in) begin + + // blend_result has been delayed by 4 cycles + case(cyc) + 0: wrdata[DWIDTH:0] <= blend_result; + 1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result; + 2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result; + 3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result; + endcase + + wrdata_finished <= wrdata_finished << 1; + if(wrdata_finished[3]) begin + wrout_en <= 1; + wrout_addr <= waddr; + end + + if(~&offs) begin + if (cyc == 1) begin + Prev2 <= Curr20; + Curr2 <= Curr21; + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + + if(cyc==3) begin + offs <= offs + 1'd1; + waddr <= {offs, curbuf}; + wrdata_finished[0] <= 1; + end + end + + pattern <= new_pattern; + if(cyc==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + cyc <= cyc + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + cyc <= 0; + curbuf <= ~curbuf; + prevbuf <= curbuf; + {Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0; + if(old_reset_frame & ~reset_frame) begin + curbuf <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf0, rdbuf1, + output[DWIDTH:0] q0,q1, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + +localparam AWIDTH = $clog2(LENGTH)-1; +wire [DWIDTH:0] out[2]; +assign q0 = out[rdbuf0]; +assign q1 = out[rdbuf1]; + +hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); +hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + +endmodule + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output reg [DWIDTH:0] q +); + +reg [DWIDTH:0] ram[0:NUMWORDS-1]; + +always_ff@(posedge clock) begin + if(wren) ram[wraddress] <= data; + q <= ram[rdaddress]; +end + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [23:0] rgb1, + input [23:0] rgb2, + output result +); + + wire [7:0] r = rgb1[7:1] - rgb2[7:1]; + wire [7:0] g = rgb1[15:9] - rgb2[15:9]; + wire [7:0] b = rgb1[23:17] - rgb2[23:17]; + wire [8:0] t = $signed(r) + $signed(b); + wire [9:0] y = $signed(t) + $signed({g[7], g}); + wire [8:0] u = $signed(r) - $signed(b); + wire [9:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-96..96) + wire y_inside = (y < 10'h60 || y >= 10'h3a0); + + // if u is inside (-16, 16) + wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0); + + // if v is inside (-24, 24) + wire v_inside = (v < 10'h18 || v >= 10'h3e8); + assign result = !(y_inside && u_inside && v_inside); + +endmodule + +module Blend +( + input clk, + input clk_en, + input [5:0] rule, + input [23:0] E, + input [23:0] A, + input [23:0] B, + input [23:0] D, + input [23:0] F, + input [23:0] H, + output [23:0] Result +); + + localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4 + localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4 + localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4 + + reg [23:0] a,b,d,e,h,f; + reg [3:0] bl_rule; + reg [1:0] df_rule; + always @(posedge clk) if (clk_en) begin + {bl_rule,df_rule} <= rule; + a <= A; b <= B; d <= D; e <= E; f <= F; h <= H; + end + + wire is_diff; + DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff); + + reg [23:0] i10,i20,i30; + reg [6:0] op0; + always @(posedge clk) if (clk_en) begin + i10 <= e; + case({!is_diff, bl_rule}) + 1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0}; + 2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0}; + 3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0}; + 4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b}; + 5,21: {op0, i20, i30} <= {BLEND2, a, b}; + 6,22: {op0, i20, i30} <= {BLEND2, a, d}; + 25,29: {op0, i20, i30} <= {BLEND5, d, b}; + 26: {op0, i20, i30} <= {BLEND6, d, b}; + 28: {op0, i20, i30} <= {BLEND4, d, b}; + 30: {op0, i20, i30} <= {BLEND3, b, d}; + 31: {op0, i20, i30} <= {BLEND3, d, b}; + default: {op0, i20, i30} <= {BLEND1, e, 24'd0}; + endcase + end + + reg [23:0] i1,i2,i3; + reg [6:0] op; + always @(posedge clk) if (clk_en) begin + op <= op0; i1 <= i10; i2 <= i20; i3 <= i30; + end + + function [34:0] mul24x3; + input [23:0] op1; + input [2:0] op2; + begin + mul24x3 = 0; + if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]}; + if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0}; + if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00}; + end + endfunction + + wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]}); + + always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]}; + +endmodule diff --git a/analogizer/openFPGA_Pocket_Analogizer.v b/analogizer/openFPGA_Pocket_Analogizer.v new file mode 100644 index 0000000..8de3738 --- /dev/null +++ b/analogizer/openFPGA_Pocket_Analogizer.v @@ -0,0 +1,472 @@ +//This module encapsulates all Analogizer adapter signals +// Original work by @RndMnkIII. +// Date: 05/2024 +// Releases: +// * 1.0 05/2024 Initial RGBS output mode +// * 1.1 Added SOG modes: RGsB, YPbPt +// * 1.2 Added Mike Simon Y/C module, Scandoubler SVGA Mist module. +// * 1.3 11/02/2025 Added Bridge interface to directly access to the Analogizer settings, now returns the settings. Added NES SNAC Zapper support. + +// *** Analogizer R.3 adapter *** +// * WHEN SOG SWITCH IS IN ON POSITION, OUTPUTS CSYNC ON G CHANNEL +// # WHEN YPbPr VIDEO OUTPUT IS SELECTED, Y->G, Pr->R, Pb->B +//Pin mappings: VGA CONNECTOR USB3 TYPE A FEMALE CONNECTOR (SNAC) +// ______________________________________________________________________________________________________________________________________________________________________________________________________ +// / VS HS R# G*# B# 1 2 3 4 5 6 7 8 9 \ +// | | | | | | VBUS D- D+ GND RX- RX+ GND_D TX- TX+ | +//FUNCTION: | | | | | | +5V OUT1 OUT2 GND IO3 IN4 IO5 IO6 IN7 | +// | A | | | | | ^ ^ ^ | ^ ^ | | +// | N SOG | | | | | | | V V V V V | +// | A ------- | | | | | | +// | O OFF | S |--GND | | +------------+ | +// | L | W | | | SYNC | | | +// PIN DIR: | G | I +--------------------->| |---------------------------------------------------------------------------------------------------------+ | +// ^ OUTPUT | I | T | | | | RGB DAC | | | +// V INPUT | Z | C | | | | |===================================================================++ | | +// | E ON ===| H |--------+ | +------------+ || | | +// | R ------- | | || | | /BLANK || | | +// | | +--------+ || | +------------------------------------------------------------------+ || | | | +// | R +------+ | || +===============================++ | || | | +// | 2 | | || || | || | | +// | CONF.B IO5V --- | | \\================================ \\================================ | \\================================ VID IO3^ IO6^ | +// | CONF.A IN4 --- IN7 IO3V VS HS R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 /BLK B0 B1 B2 B3 B4 B5 CLK OUT1 OUT2 IO5^ IO6V | +// | __3.3V__ |___ | __ |_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____^__GND__ | +//POCKET | / V V V V ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ V \ | +//CARTRIDGE PIN #: \____| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |___/ +// \_________|____|____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_______/ +//Pocket Pin Name: | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank0[7] --------------------+ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank0[6] -------------------------+ | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank0[5] ------------------------------+ | | | | | | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank0[4] ------------------------------------+ | | | | | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank3[0] ------------------------------------------+ | | | | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank3[1] ------------------------------------------------+ | | | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank3[2] ------------------------------------------------------+ | | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank3[3] ------------------------------------------------------------+ | | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank3[4] ------------------------------------------------------------------+ | | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank3[5] ------------------------------------------------------------------------+ | | | | | | | | | | | | | | | | | | | | +//cart_tran_bank3[6] ------------------------------------------------------------------------------+ | | | | | | | | | | | | | | | | | | | +//cart_tran_bank3[7] ------------------------------------------------------------------------------------+ | | | | | | | | | | | | | | | | | | +//------------------ | | | | | | | | | | | | | | | | | | +//cart_tran_bank2[0] ------------------------------------------------------------------------------------------+ | | | | | | | | | | | | | | | | | +//cart_tran_bank2[1] ------------------------------------------------------------------------------------------------+ | | | | | | | | | | | | | | | | +//cart_tran_bank2[2] ------------------------------------------------------------------------------------------------------+ | | | | | | | | | | | | | | | +//cart_tran_bank2[3] ------------------------------------------------------------------------------------------------------------+ | | | | | | | | | | | | | | +//cart_tran_bank2[4] ------------------------------------------------------------------------------------------------------------------+ | | | | | | | | | | | | | +//cart_tran_bank2[5] ------------------------------------------------------------------------------------------------------------------------+ | | | | | | | | | | | | +//cart_tran_bank2[6] ------------------------------------------------------------------------------------------------------------------------------+ | | | | | | | | | | | +//cart_tran_bank2[7] ------------------------------------------------------------------------------------------------------------------------------------+ | | | | | | | | | | +//------------------ | | | | | | | | | | +//cart_tran_bank1[0] ------------------------------------------------------------------------------------------------------------------------------------------+ | | | | | | | | | +//cart_tran_bank1[1] ------------------------------------------------------------------------------------------------------------------------------------------------+ | | | | | | | | +//cart_tran_bank1[2] ------------------------------------------------------------------------------------------------------------------------------------------------------+ | | | | | | | +//cart_tran_bank1[3] ------------------------------------------------------------------------------------------------------------------------------------------------------------+ | | | | | | +//cart_tran_bank1[4] ------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | | | | | +//cart_tran_bank1[5] ------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | | | | +//cart_tran_bank1[6] ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | | | +//cart_tran_bank1[7] ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | | +//cart_tran_pin30 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | +//cart_tran_pin31 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +`default_nettype none +`timescale 1ns / 1ps + +module openFPGA_Pocket_Analogizer #(parameter MASTER_CLK_FREQ=50_000_000, parameter LINE_LENGTH, parameter ADDRESS_ANALOGIZER_CONFIG = 8'hF7,parameter reg USE_OLD_STYLE_SVGA_SCANDOUBLER = 1'b0) ( + input wire clk_74a, + input wire i_clk, + input wire i_rst, + input wire i_ena, + //Video interface + input wire video_clk, + input wire [7:0] R, + input wire [7:0] G, + input wire [7:0] B, + input wire Hblank, + input wire Vblank, + input wire BLANKn, + input wire Hsync, + input wire Vsync, + input wire Csync, + + //openFPGA Bridge interface + input wire bridge_endian_little, + input wire [31:0] bridge_addr, + input wire bridge_rd, + output reg [31:0] analogizer_bridge_rd_data, + input wire bridge_wr, + input wire [31:0] bridge_wr_data, + + //Analogizer settings + output wire [4:0] snac_game_cont_type_out, + output wire [3:0] snac_cont_assignment_out, + output wire [3:0] analogizer_video_type_out, + output wire [2:0] SC_fx_out, + output wire pocket_blank_screen_out, + output wire analogizer_osd_out, + + //Video Y/C Encoder interface + input wire [39:0] CHROMA_PHASE_INC, + input wire PALFLAG, + //Video SVGA Scandoubler interface + input wire ce_pix, + input wire scandoubler, //logic for disable/enable the scandoubler + //SNAC interface + output wire [15:0] p1_btn_state, + output wire [31:0] p1_joy_state, + output wire [15:0] p2_btn_state, + output wire [31:0] p2_joy_state, + output wire [15:0] p3_btn_state, + output wire [15:0] p4_btn_state, + //PSX rumble interface joy1, joy2 + input [1:0] i_VIB_SW1, // Vibration SW VIB_SW[0] Small Moter OFF 0:ON 1: + //VIB_SW[1] Bic Moter OFF 0:ON 1(Dualshook Only) + input [7:0] i_VIB_DAT1, // Vibration(Bic Moter)Data 8'H00-8'HFF (Dualshook Only) + input [1:0] i_VIB_SW2, + input [7:0] i_VIB_DAT2, + // + output wire busy, + //Pocket Analogizer IO interface to the cartridge port + inout wire [7:0] cart_tran_bank2, + output wire cart_tran_bank2_dir, + inout wire [7:0] cart_tran_bank3, + output wire cart_tran_bank3_dir, + inout wire [7:0] cart_tran_bank1, + output wire cart_tran_bank1_dir, + inout wire [7:4] cart_tran_bank0, + output wire cart_tran_bank0_dir, + inout wire cart_tran_pin30, + output wire cart_tran_pin30_dir, + output wire cart_pin30_pwroff_reset, + inout wire cart_tran_pin31, + output wire cart_tran_pin31_dir, + //debug + output wire [3:0] DBG_TX, + output wire o_stb +); + + //Configuration file dat + //reg [31:0] analogizer_bridge_rd_data; + reg analogizer_ena; + reg i_ena2 = 0; + reg [15:0] analogizer_config = 0; + wire [15:0] analogizer_config_s; + wire [5:0] R6,G6,B6; + assign R6 = R[7:2]; + assign G6 = G[7:2]; + assign B6 = B[7:2]; + + synch_3 #(.WIDTH(16)) analogizer_sync(analogizer_config[15:0], analogizer_config_s, i_clk); + + always @(posedge clk_74a) begin + if(bridge_wr && bridge_addr == {ADDRESS_ANALOGIZER_CONFIG,24'h0}) begin + analogizer_config <= {bridge_wr_data[23:16],bridge_wr_data[31:24]}; + end + end + + always @(posedge i_clk) begin + snac_game_cont_type <= analogizer_config_s[4:0]; + snac_cont_assignment <= analogizer_config_s[9:6]; + analogizer_video_type <= analogizer_config_s[13:10]; + analogizer_ena <= analogizer_config_s[5]; + pocket_blank_screen <= analogizer_config_s[14]; + analogizer_osd_out2 <= analogizer_config_s[15]; + end + + wire conf_AB = (snac_game_cont_type >= 5'd16); + + // always @(posedge i_clk) begin + // i_ena2 <= ( i_ena ? analogizer_ena ? 1'b1: 1'b0 : 1'b0;) + // end + always @(posedge i_clk) begin + i_ena2 <= ( i_ena ? 1'b1: 1'b0); + end + + //0 disable, 1 scanlines 25%, 2 scanlines 50%, 3 scanlines 75%, 4 hq2x + always @(posedge i_clk) begin + if(analogizer_video_type >= 4'd5) SC_fx <= analogizer_video_type - 4'd5; +end + +reg [3:0] analogizer_video_type; +reg [4:0] snac_game_cont_type; +reg [3:0] snac_cont_assignment; +reg [2:0] SC_fx; +reg pocket_blank_screen; +reg analogizer_osd_out2; + +assign analogizer_video_type_out = analogizer_video_type; +assign snac_game_cont_type_out = snac_game_cont_type; +assign snac_cont_assignment_out = snac_cont_assignment; +assign SC_fx_out = SC_fx; +assign pocket_blank_screen_out = pocket_blank_screen; +assign analogizer_osd_out = analogizer_osd_out2; +//------------------------------------------------------------------------ + + wire [7:4] CART_BK0_OUT ; + wire [7:4] CART_BK0_IN ; + wire CART_BK0_DIR ; + wire [7:6] CART_BK1_OUT_P76 ; + wire CART_PIN30_OUT ; + wire CART_PIN30_IN ; + wire CART_PIN30_DIR ; + wire CART_PIN31_OUT ; + wire CART_PIN31_IN ; + wire CART_PIN31_DIR ; + + openFPGA_Pocket_Analogizer_SNAC #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ)) snac + ( + .i_clk(i_clk), + .i_rst(i_rst), + .conf_AB(conf_AB), //0 conf. A(default), 1 conf. B (see graph above) + .game_cont_type(snac_game_cont_type), //0-15 Conf. A, 16-31 Conf. B + //.game_cont_sample_rate(game_cont_sample_rate), //0 compatibility mode (slowest), 1 normal mode, 2 fast mode, 3 superfast mode + .p1_btn_state(p1_btn_state), + .p1_joy_state(p1_joy_state), + .p2_btn_state(p2_btn_state), + .p2_joy_state(p2_joy_state), + .p3_btn_state(p3_btn_state), + .p4_btn_state(p4_btn_state), + .i_VIB_SW1(i_VIB_SW1), .i_VIB_DAT1(i_VIB_DAT1), .i_VIB_SW2(i_VIB_SW2), .i_VIB_DAT2(i_VIB_DAT2), + .busy(busy), + //SNAC Pocket cartridge port interface (see graph above) + .CART_BK0_OUT(CART_BK0_OUT), + .CART_BK0_IN(CART_BK0_IN), + .CART_BK0_DIR(CART_BK0_DIR), + .CART_BK1_OUT_P76(CART_BK1_OUT_P76), + .CART_PIN30_OUT(CART_PIN30_OUT), + .CART_PIN30_IN(CART_PIN30_IN), + .CART_PIN30_DIR(CART_PIN30_DIR), + .CART_PIN31_OUT(CART_PIN31_OUT), + .CART_PIN31_IN(CART_PIN31_IN), + .CART_PIN31_DIR(CART_PIN31_DIR), + //debug + .DBG_TX(DBG_TX), + .o_stb(o_stb) + ); + + //Choose type of analog video type of signal + reg [5:0] Rout, Gout, Bout ; + reg HsyncOut, VsyncOut, BLANKnOut ; + wire [5:0] Yout, PrOut, PbOut ; + wire [5:0] R_Sd, G_Sd, B_Sd ; + wire Hsync_Sd, Vsync_Sd ; + wire Hblank_Sd, Vblank_Sd ; + wire BLANKn_SD = ~(Hblank_Sd || Vblank_Sd) ; + + always @(*) begin + case(analogizer_video_type) + 4'h0: begin //RGBS + Rout = R6&{6{BLANKn}}; + Gout = G6&{6{BLANKn}}; + Bout = B6&{6{BLANKn}}; + HsyncOut = Csync; + VsyncOut = 1'b1; + BLANKnOut = BLANKn; + end + 4'h3, 4'h4: begin// Y/C Modes works for Analogizer R1, R2 Adapters + Rout = yc_o[15:10]; //6bpp + Gout = yc_o[7:2]; //6bpp + Bout = 6'h0; + HsyncOut = yc_cs; + VsyncOut = 1'b1; + BLANKnOut = 1'b1; + end + 4'h1: begin //RGsB + Rout = R6&{6{BLANKn}}; + Gout = G6&{6{BLANKn}}; + Bout = B6&{6{BLANKn}}; + HsyncOut = 1'b1; + VsyncOut = Csync; //to DAC SYNC pin, SWITCH SOG ON + BLANKnOut = BLANKn; + end + 4'h2: begin //YPbPr + Rout = PrOut; + Gout = Yout; + Bout = PbOut; + HsyncOut = 1'b1; + VsyncOut = YPbPr_sync; //to DAC SYNC pin, SWITCH SOG ON + BLANKnOut = 1'b1; //ADV7123 needs this + end + + 4'h5, 4'h6, 4'h7, 4'h8, 4'h9: begin //Scandoubler modes + if (USE_OLD_STYLE_SVGA_SCANDOUBLER == 1'b1) begin + Rout = R_Sd; + Gout = G_Sd; + Bout = B_Sd; + HsyncOut = Hsync_Sd; + VsyncOut = Vsync_Sd; + BLANKnOut = 1'b1; + end else begin + Rout = vga_data_sl[23:18]; //R_Sd[7:2]; + Gout = vga_data_sl[15:10]; //G_Sd[7:2]; + Bout = vga_data_sl[7:2]; //B_Sd[7:2]; + HsyncOut = vga_hs_sl; //Hsync_Sd; + VsyncOut = vga_vs_sl; //Vsync_Sd; + BLANKnOut = 1'b1; + end + end + default: begin + Rout = 6'h0; + Gout = 6'h0; + Bout = 6'h0; + HsyncOut = Hsync; + VsyncOut = 1'b1; + BLANKnOut = BLANKn; + end + endcase + end + + wire YPbPr_sync, YPbPr_blank; + vga_out ybpr_video + ( + .clk(video_clk), + .ypbpr_en(1'b1), + .csync(Csync), + .de(BLANKn), + .din({R6&{6{BLANKn}},G6&{6{BLANKn}},B6&{6{BLANKn}}}), //NES specific override, because not zero color data while blanking period. 18 bits + .dout({PrOut,Yout,PbOut}), //18 bit + .csync_o(YPbPr_sync), + .de_o(YPbPr_blank) + ); + + wire [15:0] yc_o ; + //wire yc_hs, yc_vs, + wire yc_cs ; + yc_out yc_out + ( + .clk(i_clk), + .PHASE_INC(CHROMA_PHASE_INC), + .PAL_EN(PALFLAG), + .hsync(Hsync), + .vsync(Vsync), + .csync(Csync), + .din({R6&{6{BLANKn}},G6&{6{BLANKn}},B6&{6{BLANKn}}}), //18 bits + .dout(yc_o), //16 bits + .hsync_o(), + .vsync_o(), + .csync_o(yc_cs) + ); + + +generate + if (USE_OLD_STYLE_SVGA_SCANDOUBLER == 1'b1) begin + //Using old scandoubler code for PC Engine CD core + scandoubler sc_video + ( + // system interface + .clk_sys(i_clk), + .bypass(1'b0), + + // Pixelclock + .ce_divider(3'd7), // 0 - clk_sys/4, 1 - clk_sys/2, 2 - clk_sys/3, 3 - clk_sys/4, etc. + //.ce_divider(3'd0), // 0 - clk_sys/4, 1 - clk_sys/2, 2 - clk_sys/3, 3 - clk_sys/4, etc. + .pixel_ena(), //output + .scanlines(SC_fx[1:0]), // scanlines (00-none 01-25% 10-50% 11-75%) + + // shifter video interface + .hb_in(Hblank), + .vb_in(Vblank), + .hs_in(Hsync), + //.hs_in(delayed_hsync[1]), + .vs_in(Vsync), + .r_in({R[7:2]&{6{BLANKn}}}), + .g_in({G[7:2]&{6{BLANKn}}}), + .b_in({B[7:2]&{6{BLANKn}}}), + + // output interface + .hb_out(Hblank_Sd), + .vb_out(Vblank_Sd), + .hs_out(Hsync_Sd), + .vs_out(Vsync_Sd), + .r_out(R_Sd), + .g_out(G_Sd), + .b_out(B_Sd) + ); + end else begin + wire ce_pix_Sd ; + scandoubler_2 #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(0)) sd + ( + .clk_vid(i_clk), + .hq2x(SC_fx[2]), + + .ce_pix(ce_pix), + .hs_in(Hsync), + .vs_in(Vsync), + .hb_in(Hblank), + .vb_in(Vblank), + .r_in({R[7:0]&{8{BLANKn}}}), + .g_in({G[7:0]&{8{BLANKn}}}), + .b_in({B[7:0]&{8{BLANKn}}}), + + .ce_pix_out(ce_pix_Sd), + .hs_out(Hsync_Sd), + .vs_out(Vsync_Sd), + .hb_out(Hblank_Sd), + .vb_out(Vblank_Sd), + .r_out(R_Sd), + .g_out(G_Sd), + .b_out(B_Sd) + ); + + reg Hsync_SL, Vsync_SL, Hblank_SL, Vblank_SL ; + reg [7:0] R_SL, G_SL, B_SL ; + reg CE_PIX_SL, DE_SL ; + + always @(posedge video_clk) begin + Hsync_SL <= (scandoubler) ? Hsync_Sd : Hsync; + Vsync_SL <= (scandoubler) ? Vsync_Sd : Vsync; + Hblank_SL <= (scandoubler) ? Hblank_Sd : Hblank; + Vblank_SL <= (scandoubler) ? Vblank_Sd : Vblank; + R_SL <= (scandoubler) ? R_Sd : {R[7:0]&{8{BLANKn}}}; + G_SL <= (scandoubler) ? G_Sd : {G[7:0]&{8{BLANKn}}}; + B_SL <= (scandoubler) ? B_Sd : {B[7:0]&{8{BLANKn}}}; + CE_PIX_SL <= (scandoubler) ? ce_pix_Sd : ce_pix; + DE_SL <= BLANKn; + end + + + wire [23:0] vga_data_sl ; + wire vga_vs_sl, vga_hs_sl ; + scanlines_analogizer #(0) VGA_scanlines + ( + .clk(video_clk), + + .scanlines(SC_fx[1:0]), + //.din(de_emu ? {R_SL, G_SL,B_SL} : 24'd0), + .din({R_SL, G_SL,B_SL}), + .hs_in(Hsync_SL), + .vs_in(Vsync_SL), + .de_in(DE_SL), + .ce_in(CE_PIX_SL), + + .dout(vga_data_sl), + .hs_out(vga_hs_sl), + .vs_out(vga_vs_sl), + .de_out(), + .ce_out() + ); + end +endgenerate + + //infer tri-state buffers for cartridge data signals + //BK0 + assign cart_tran_bank0 = i_rst | ~i_ena2 ? 4'hf : ((CART_BK0_DIR) ? CART_BK0_OUT : 4'hZ); //on reset state set ouput value to 4'hf + assign cart_tran_bank0_dir = i_rst | ~i_ena2 ? 1'b1 : CART_BK0_DIR; //on reset state set pin dir to output + assign CART_BK0_IN = cart_tran_bank0; + //BK3 + assign cart_tran_bank3 = i_rst | ~i_ena2 ? 8'hzz : {Rout[5:0],HsyncOut,VsyncOut}; //on reset state set ouput value to 8'hZ + assign cart_tran_bank3_dir = i_rst | ~i_ena2 ? 1'b0 : 1'b1; //on reset state set pin dir to input + //BK2 + assign cart_tran_bank2 = i_rst | ~i_ena2 ? 8'hzz : {Bout[0],BLANKnOut,Gout[5:0]}; //on reset state set ouput value to 8'hZ + assign cart_tran_bank2_dir = i_rst | ~i_ena2 ? 1'b0 : 1'b1; //on reset state set pin dir to input + //BK1 + assign cart_tran_bank1 = i_rst | ~i_ena2 ? 8'hzz : {CART_BK1_OUT_P76,video_clk,Bout[5:1]}; //on reset state set ouput value to 8'hZ + assign cart_tran_bank1_dir = i_rst | ~i_ena2 ? 1'b0 : 1'b1; //on reset state set pin dir to input + //PIN30 + assign cart_tran_pin30 = i_rst | ~i_ena2 ? 1'bz : ((CART_PIN30_DIR) ? CART_PIN30_OUT : 1'bZ); //on reset state set ouput value to 4'hf + assign cart_tran_pin30_dir = i_rst | ~i_ena2 ? 1'b0 : CART_PIN30_DIR; //on reset state set pin dir to output + assign CART_PIN30_IN = cart_tran_pin30; + assign cart_pin30_pwroff_reset = i_rst | ~i_ena2 ? 1'b0 : 1'b1; //1'b1 (GPIO USE) + //PIN31 + assign cart_tran_pin31 = i_rst | ~i_ena2 ? 1'bz : ((CART_PIN31_DIR) ? CART_PIN31_OUT : 1'bZ); //on reset state set ouput value to 4'hf + assign cart_tran_pin31_dir = i_rst | ~i_ena2 ? 1'b0 : CART_PIN31_DIR; //on reset state set pin dir to input + assign CART_PIN31_IN = cart_tran_pin31; +endmodule \ No newline at end of file diff --git a/analogizer/openFPGA_Pocket_Analogizer_SNAC.sv b/analogizer/openFPGA_Pocket_Analogizer_SNAC.sv new file mode 100644 index 0000000..3ab185a --- /dev/null +++ b/analogizer/openFPGA_Pocket_Analogizer_SNAC.sv @@ -0,0 +1,500 @@ +//This module encapsulates all Analogizer adapter SNAC controllers +// Original work by @RndMnkIII. +// Date: 01/2024 +// Release: 1.0 + +// *** Analogizer R.1 adapter *** +//SNAC mappings: +//USB 3 Type A connector ______________________________________________________________________________________ +//PIN_NUMBER: / 1 2 3 4 5 6 7 8 9 \ +//PIN_NAME: | VBUS D- D+ GND RX- RX+ GND_D TX- TX+ | +//FUNCTION: | +5V OUT1 OUT2 GND IO3 IN4 IO5 IO6 IN7 | +// | A ^ ^ ^ | ^ ^ | | +// | N | | | | +--|-------|-------+ | +// | A +-----------|-------|--------------|-------+ | | +----------------+ | +// | L | +-|-------|--------------|------------+ +--------+ | | +// | O | | | | | +------------+ | | | +// | G | | | | | +->| B B |----|------+ | | +// | I | | | | +---|->| CONF. SW. |<---+ | | | +// | Z | | | +---|-------<----------|<-| A A |<----+ | | | +// | E | | | | | | +------------+ | | | | +// | R | | | | | +-->-+------>--------->----+ | | | +// | I| I| | | +-------+ | | | | +// | R N| N| +---------+ | B|A B OUT | | | +// | 1 4| I 7| IO3| OUT1| OUT2| IO3|IO5 +-----------------------------------+ | +// | | O IN| A| |O |O O|O |A IN | | +// | I| 5+----|-----|-----|U----|U---U|U ---|--------------------------+ | +// | ___N|___B|IN__|___IN|_____|T____|T___T|T____|_____ | +//POCKET | / V V V V ^ ^ ^ V \ | +//CARTRIDGE PIN #: \___| 2 3 4 5 ... 28 29 30 31 |_____________________________/ +// \____|____|____|_____|_____|_____|_____|_____|_____/ +//Pocket Pin Name: | | | | | | | | +//cart_tran_bank0[7] ---------------+ | | | | | | | cart_tran_bank0_dir=1'b0; //input +//cart_tran_bank0[6] --------------------+ | | | | | | +//cart_tran_bank0[5] -------------------------+ | | | | | +//cart_tran_bank0[4] -------------------------------+ | | | | +//cart_tran_bank1[6] -------------------------------------+ | | | cart_tran_bank1_dir=1'b1 //output +//cart_tran_bank1[7] -------------------------------------------+ | | +//cart_tran_pin30 -------------------------------------------------+ | cart_tran_pin30_dir=1'b1, cart_pin30_pwroff_reset=1'b1 (GPIO USE) +//cart_tran_pin31 -------------------------------------------------------+ cart_tran_pin31_dir=1'b0 / 1'b1 +//-------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------ +// C O N F I G U R A T I O N A || CONFIGURATION B +//-------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------ +// DEV TYPE 0 1 2 3 4 5 6 || 16 +// PIN_NAME SNAC DISABLED DB15 NES SNES PCENGINE(2BTN) PCENGINE(6BTN) PCENGINE(MULTITAP) || PSX +//USB3 SNAC || [NOT IMPLEMENTED] +//-------------------------------------------------------------------------------------------------------------------------------------------------------------------||------------------ +//VBUS +5V +5V +5V +5V +5V +5V || +5V +//D- OUT1 CLK(O) CLK_1(O) CLK_1(O) CLR(O)(*) CLR(O)(*) CLR(O)(*) || AT1(O) +//D+ OUT2 LAT(O) LAT(O) LAT(O) SEL(O)(*) SEL(O)(*) SEL(O)(*) || AT2(O) +//GND GND GND GND GND GND GND || GND +//RX- IO3 DAT(I) D0_1(I) D0_1(I) D2 (I)(*) D2 (I)(*) D2 (I)(*) || CLK(O) + +//RX+ IN4 D4_2(I) IO_2(I) D0 (I)(*) D0 (I)(*) D0 (I)(*) || DAT(I) +//GND_DRAIN IO5 CLK_2(O) CLK_2(O) || ACK(I) + +//TX- IO6 DAT(I)(1) D3_2(I) D3_2(I) D1 (I)(*) D1 (I)(*) D1 (I)(*) || CMD(O) + +//TX+ IN7 D0_2(I) D0_2(I) D3 (I)(*) D3 (I)(*) D3 (I)(*) D3 (I)(*) || IRQ10(I) +// +//(1) Alternate output of DAT (for male-to-male extension cables which cross Tx,Rx lines) + +//(*) Needs a specific cable harness for use MiSTer SNAC adapter with the Pocket: +// SNAC PCENGINE POCKET +// ADAPTER FUNCTION SNAC +// D- -> D0 -> RX+ IN4 +// D+ -> D1 -> TX- IO6 (IN) +// RX- -> D2 -> RX- IO3 (IN) +// RX+ -> CLR -> D- OUT1 +// GND_D -> D3 -> TX+ IN7 +// TX- -> SEL -> D+ OUT2 +`default_nettype none +`timescale 1ns / 1ps + +module openFPGA_Pocket_Analogizer_SNAC #(parameter MASTER_CLK_FREQ=50_000_000) +( + input wire i_clk, //Core Master Freq. + input wire i_rst, //Core general reset + input wire conf_AB, //0 conf. A(default), 1 conf. B (see graph above) + input wire [4:0] game_cont_type, //0-15 Conf. A, 16-31 Conf. B + //input wire [2:0] game_cont_sample_rate, //0 compatibility mode (slowest), 1 normal mode, 2 fast mode, 3 superfast mode + //PSX rumble interface joy1, joy2 + input [1:0] i_VIB_SW1, // Vibration SW VIB_SW[0] Small Moter OFF 0:ON 1: + //VIB_SW[1] Bic Moter OFF 0:ON 1(Dualshook Only) + input [7:0] i_VIB_DAT1, // Vibration(Bic Moter)Data 8'H00-8'HFF (Dualshook Only) + input [1:0] i_VIB_SW2, + input [7:0] i_VIB_DAT2, + output reg [15:0] p1_btn_state, + output reg [31:0] p1_joy_state, + output reg [15:0] p2_btn_state, + output reg [31:0] p2_joy_state, + output reg [15:0] p3_btn_state, + output reg [15:0] p4_btn_state, + output reg busy, + //SNAC Pocket cartridge port interface (see graph above) + output reg [7:4] CART_BK0_OUT, + input wire [7:4] CART_BK0_IN, + output reg CART_BK0_DIR, + output reg [7:6] CART_BK1_OUT_P76, + output reg CART_PIN30_OUT, + input wire CART_PIN30_IN, + output reg CART_PIN30_DIR, + output reg CART_PIN31_OUT, + input wire CART_PIN31_IN, + output reg CART_PIN31_DIR, + //debug + output wire [3:0] DBG_TX, + output wire o_stb +); + // + logic SNAC_OUT1 ; //cart_tran_bank1[6] D- + logic SNAC_OUT2 ; //cart_tran_bank1[7] D+ + logic SNAC_IO3_A ;//Conf.A: cart_tran_bank0[4] (in), Conf.B: pin30(out) RX- + logic SNAC_IO3_B ;//Conf.B: cart_tran_bank0[4] (in), Conf.B: pin30(out) RX- + logic SNAC_IN4 ; //cart_tran_bank0[7] RX+ + logic SNAC_IO5_A ;//Conf.A: pin30(out), Conf.B: cart_tran_bank1[6] GND_D + logic SNAC_IO5_B ;//Conf.A: pin30(out), Conf.B: cart_tran_bank1[6] GND_D + logic SNAC_IO6_A ;//Conf.A: pin31(in), Conf.B: pin31(out) TX- + logic SNAC_IO6_B ;//Conf.A: pin31(in), Conf.B: pin31(out) TX- + logic SNAC_IN7 ; //cart_tran_bank0[5] TX+ + + //calculate step sizes for fract clock enables + // localparam pce_compat_polling_freq = 20_000; // 20_000 / 5 = 4K samples/sec PCE + localparam pce_normal_polling_freq = 40_000; // 40_000 / 5 = 8K samples/sec PCE + localparam pce_fast_polling_freq = 80_000; // 80_000 / 5 = 16K samples/sec PCE + // localparam pce_very_fast_polling_freq = 100_000; // 100_000 / 5 = 20K samples/sec PCE + + // localparam Compat_60Hz_polling_freq = 1_080; // + // localparam Compat_120Hz_polling_freq = 2_160; // + localparam snes_compat_polling_freq = 50_000; // + // localparam serlatch_compat_polling_freq = 100_000; // 100_000 / 25 = 4K samples/sec DB15 100_000 / 18 = 5.55K samples/sec NES/SNES + localparam serlatch_normal_polling_freq = 200_000; // 200_000 / 25 = 8K samples/sec DB15 200_000 / 18 = 11.11K samples/sec NES/SNES + localparam serlatch_fast_polling_freq = 400_000; // 400_000 / 25 = 16K samples/sec DB15 400_000 / 18 = 22.22K samples/sec NES/SNES + // localparam serlatch_very_fast_polling_freq = 1_000_000; //1_000_000 / 25 = 32K samples/sec DB15 1_000_000 / 18 = 55.55K samples/sec NES/SNES + + localparam psx_normal_polling_freq = 125_000; + localparam psx_fast_polling_freq = 250_000; + localparam psx_ultra_fast_polling_freq = 500_000; + localparam psx_multitap_polling_freq = 1_000_000; + + // localparam uart_dbg_freq = 500_000 * 16; //115_200 * 16; + localparam uart_dbg_freq = 1_000_000; //115_200 * 16; + localparam [64:0] uart_dbg_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * uart_dbg_freq * 2) / 1000; + localparam [32:0] uart_dbg_pstep = uart_dbg_pstep_[32:0]; + + + //the FSM is clocked 2x the polling freq. + localparam [32:0] MAX_INT = 33'h0ffffffff; + // localparam [64:0] pce_compat_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * pce_compat_polling_freq * 2) / 1000; + // localparam [32:0] pce_compat_pstep = pce_compat_pstep_[32:0]; + localparam [64:0] pce_normal_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * pce_normal_polling_freq * 2) / 1000; + localparam [32:0] pce_normal_pstep = pce_normal_pstep_[32:0]; + localparam [64:0] pce_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * pce_fast_polling_freq * 2) / 1000; + localparam [32:0] pce_fast_pstep = pce_fast_pstep_[32:0]; + + localparam [64:0] psx_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * psx_fast_polling_freq * 2) / 1000; + localparam [32:0] psx_fast_pstep = psx_fast_pstep_[32:0]; + localparam [64:0] psx_normal_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * psx_normal_polling_freq * 2) / 1000; + localparam [32:0] psx_normal_pstep = psx_normal_pstep_[32:0]; + localparam [64:0] psx_ultra_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * psx_ultra_fast_polling_freq * 2) / 1000; + localparam [32:0] psx_ultra_fast_pstep = psx_ultra_fast_pstep_[32:0]; + localparam [64:0] psx_multitap_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * psx_multitap_polling_freq * 2) / 1000; + localparam [32:0] psx_multitap_pstep = psx_multitap_pstep_[32:0]; + // localparam [64:0] pce_very_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) *pce_very_fast_polling_freq * 2) / 1000; + // localparam [32:0] pce_very_fast_pstep = pce_very_fast_pstep_[32:0]; + + // localparam [64:0] serlatch_compat_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * serlatch_compat_polling_freq * 2) / 1000; + // localparam [32:0] serlatch_compat_pstep = serlatch_compat_pstep_[32:0]; + localparam [64:0] serlatch_normal_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * serlatch_normal_polling_freq * 2) / 1000; + localparam [32:0] serlatch_normal_pstep = serlatch_normal_pstep_[32:0]; + localparam [64:0] serlatch_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * serlatch_fast_polling_freq * 2) / 1000; + localparam [32:0] serlatch_fast_pstep = serlatch_fast_pstep_[32:0]; + // localparam [64:0] serlatch_very_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * serlatch_very_fast_polling_freq * 2) / 1000; + // localparam [32:0] serlatch_very_fast_pstep = serlatch_very_fast_pstep_[32:0]; + + localparam [64:0] snes_compat_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * snes_compat_polling_freq * 2) / 1000; + localparam [32:0] snes_compat_pstep = snes_compat_pstep_[32:0]; + + // localparam [64:0] Compat_60Hz_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * Compat_60Hz_polling_freq * 2) / 1000; + // localparam [32:0] Compat_60Hz_pstep = Compat_60Hz_pstep_[32:0]; + // localparam [64:0] Compat_120Hz_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * Compat_120Hz_polling_freq * 2) / 1000; + // localparam [32:0] Compat_120Hz_pstep = Compat_120Hz_pstep_[32:0]; + + //Supported game controller types + localparam GC_DISABLED = 5'h0; + localparam GC_DB15 = 5'h1; + localparam GC_NES = 5'h2; + localparam GC_SNES = 5'h3; + localparam GC_PCE_2BTN = 5'h4; + localparam GC_PCE_6BTN = 5'h5; + localparam GC_PCE_MULTITAP = 5'h6; + localparam GC_DB15_FAST = 5'h9; + localparam GC_SNES_SWAP = 5'hB; + localparam GC_PSX = 5'h10; //16 PSX 125KHz + localparam GC_PSX_FAST = 5'h11; //17 PSX 250KHz + localparam GC_PSX_ANALOG = 5'h12; //16 PSX 125KHz + localparam GC_PSX_ANALOG_FAST = 5'h13; //17 PSX 250KHz + + //Configuration: + localparam CONF_A = 1'b0; + localparam CONF_B = 1'b1; + + reg conf_AB_r; + reg [4:0] game_cont_type_r; + // reg [2:0] game_cont_sample_rate_r; + reg [32:0] strobe_step_size; + reg reset_on_change; + + always @(posedge i_clk) begin + //register SNAC settings + conf_AB_r <= conf_AB; + game_cont_type_r <= game_cont_type; + //game_cont_sample_rate_r <= game_cont_sample_rate; + + //detect change of SNAC settings and reset clock divider and set new settings + reset_on_change <= 1'b0; + //if(i_rst || (game_cont_type_r != game_cont_type) || (game_cont_sample_rate_r != game_cont_sample_rate)) begin + if(i_rst || (game_cont_type_r != game_cont_type)) begin + reset_on_change <= 1'b1; + end + end + + reg serlat_ena; + reg pce_ena; + reg psx_ena; + + always @(posedge i_clk) begin + case (game_cont_type) + GC_PSX, GC_PSX_ANALOG: begin + psx_ena <= 1'b1; + strobe_step_size <= psx_normal_pstep; + end + GC_PSX_FAST, GC_PSX_ANALOG_FAST: begin + psx_ena <= 1'b1; + strobe_step_size <= psx_fast_pstep; + end + GC_DB15: begin + serlat_ena <= 1'b1; + strobe_step_size <= serlatch_normal_pstep; + // case (game_cont_sample_rate) + // 0: begin strobe_step_size <= serlatch_compat_pstep; end + // 1: begin strobe_step_size <= serlatch_normal_pstep; end + // 2: begin strobe_step_size <= serlatch_fast_pstep; end + // // 3: begin strobe_step_size <= serlatch_very_fast_pstep; end + // // 4: begin strobe_step_size <= snes_compat_pstep; end + // // 5: begin strobe_step_size <= Compat_60Hz_pstep; end + // // 6: begin strobe_step_size <= Compat_120Hz_pstep; end + // default: begin strobe_step_size <= serlatch_compat_pstep ; end + // endcase + end + GC_DB15_FAST: begin + serlat_ena <= 1'b1; + strobe_step_size <= serlatch_fast_pstep; + end + GC_NES, GC_SNES, GC_SNES_SWAP: begin + serlat_ena <= 1'b1; + strobe_step_size <= snes_compat_pstep; + // case (game_cont_sample_rate) + // 0: begin strobe_step_size <= serlatch_compat_pstep ; end + // 1: begin strobe_step_size <= serlatch_normal_pstep; end + // 2: begin strobe_step_size <= serlatch_fast_pstep; end + // // 3: begin strobe_step_size <= serlatch_very_fast_pstep; end + // // 4: begin strobe_step_size <= snes_compat_pstep; end + // // 5: begin strobe_step_size <= Compat_60Hz_pstep; end + // // 6: begin strobe_step_size <= Compat_120Hz_pstep; end + // default: begin strobe_step_size <= serlatch_compat_pstep ; end + // endcase + end + GC_PCE_2BTN, GC_PCE_6BTN: begin + pce_ena <= 1'b1; + strobe_step_size <= pce_normal_pstep; + // case (game_cont_sample_rate) + // 0: begin strobe_step_size <= pce_compat_pstep; end + // 1: begin strobe_step_size <= pce_normal_pstep; end + // 2: begin strobe_step_size <= pce_fast_pstep; end + // 3: begin strobe_step_size <= pce_very_fast_pstep; end + // default: begin strobe_step_size <= pce_compat_pstep; end + // endcase + end + GC_PCE_MULTITAP: begin + pce_ena <= 1'b1; + strobe_step_size <= pce_fast_pstep; + end + + default: begin//disabled + serlat_ena <= 1'b0; + pce_ena <= 1'b0; + psx_ena <= 1'b0; + strobe_step_size <= 33'h0; + end + endcase + end + + always @(posedge i_clk) begin + case (conf_AB) + CONF_A: begin + CART_BK0_DIR <= 1'b0; //INPUT + {SNAC_IN4,SNAC_IN7,SNAC_IO3_A} <= {CART_BK0_IN[7],CART_BK0_IN[5],CART_BK0_IN[4]}; //OUTPUT + CART_BK1_OUT_P76 <= {SNAC_OUT2,SNAC_OUT1}; //OUTPUT + CART_PIN30_DIR <= 1'b1; //OUTPUT + CART_PIN30_OUT <= SNAC_IO5_A; + CART_PIN31_DIR <= 1'b0; //INPUT + SNAC_IO6_A <= CART_PIN31_IN; + end + CONF_B: begin + CART_BK0_DIR <= 1'b0; //INPUT + {SNAC_IN4,SNAC_IO5_B,SNAC_IN7} <= {CART_BK0_IN[7],CART_BK0_IN[6],CART_BK0_IN[5]}; //OUTPUT + CART_BK1_OUT_P76 <= {SNAC_OUT2,SNAC_OUT1}; //OUTPUT + CART_PIN30_DIR <= 1'b1; //OUTPUT + CART_PIN30_OUT <= SNAC_IO3_B; + CART_PIN31_DIR <= 1'b1; //OUTPUT + CART_PIN31_OUT <= SNAC_IO6_B; + end + endcase + end + + wire stb_clk ; + clock_divider_fract ckdiv( + .i_clk (i_clk), + .i_rst(reset_on_change), //reset on polling freq change + .i_step(strobe_step_size[31:0]), + .o_stb (stb_clk) + ); + + // wire dbg_clk_w; + // reg dbg_clk /* synthesis noprune */; + // clock_divider_fract dbgckdiv( + // .i_clk (i_clk), + // .i_rst(reset_on_change), //reset on polling freq change + // .i_step(uart_dbg_pstep[31:0]), + // .o_stb (dbg_clk_w) + // ); + + // always @(posedge i_clk) dbg_clk <= dbg_clk_w; + + assign o_stb = stb_clk; + + //PSX game controller for 1/2 players + wire [15:0] psx_key1, psx_key2; + wire [31:0] psx_joy1, psx_joy2; + wire PSX_SNAC_OUT1 ; + wire PSX_SNAC_OUT2 ; + analogizer_psx #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ)) psx ( + .i_clk(i_clk), + .i_rst(reset_on_change), + .i_ena(psx_ena), + .i_stb(stb_clk), + .key1(psx_key1), + .joy1(psx_joy1), + .key2(psx_key2), + .joy2(psx_joy2), + //PSX RUMBLE INTERFACE + .i_VIB_SW1(i_VIB_SW1), .i_VIB_DAT1(i_VIB_DAT1), .i_VIB_SW2(i_VIB_SW2), .i_VIB_DAT2(i_VIB_DAT2), + //PSX EXTERNAL INTERFACE + .PSX_CLK(SNAC_IO3_B), + .PSX_DAT(SNAC_IN4), + .PSX_CMD(SNAC_IO6_B), + .PSX_ATT1(PSX_SNAC_OUT1), + .PSX_ATT2(PSX_SNAC_OUT2), + .PSX_ACK(SNAC_IO5_B), + .DBG_TX(DBG_TX) + ); + //assign PSX_SNAC_OUT2 = 1'b1; + + //DB15/NES/SNES game controller + wire [15:0] sl_p1 ; + wire [15:0] sl_p2 ; + wire SERLAT_SNAC_OUT1 ; + wire SERLAT_SNAC_OUT2 ; + reg [1:0] i_D3_r; + reg [1:0] i_D4_r; + //wire SERLAT_SNAC_IO5_A /* synthesis keep */; + + //shift in D3 and D4 from SNAC_IN4 and SNAC_IO6_A for NES Zapper controller + always @(posedge i_clk) begin + i_D3_r <= {i_D3_r[0],SNAC_IO6_A}; + i_D4_r <= {i_D4_r[0],SNAC_IN4}; + end + serlatch_game_controller #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ)) slgc + ( + .i_clk(i_clk), + .i_rst(reset_on_change), + .game_controller_type(game_cont_type[3:0]), //0x1 DB15, 0x2 NES, 0x3 SNES, 0x9 DB15 FAST, 0XB SNES SWAP A,B<->X,Y + .i_stb(stb_clk), + .p1_btn_state(sl_p1), + .p2_btn_state(sl_p2), + .busy(), + //SNAC Game controller interface + .o_clk(SERLAT_SNAC_OUT1), //shared for 2 controllers + .o_clk2(SNAC_IO5_A), + .o_lat(SERLAT_SNAC_OUT2), //shared for 2 controllers + .i_dat1((game_cont_type == 5'h1 || game_cont_type == 5'h9) ? SNAC_IO3_A & SNAC_IO6_A : SNAC_IO3_A ), //data from controller 1 + .i_dat2(SNAC_IN7) //data from controller 2 + ); + + //PCENGINE game controller + wire [15:0] pce_p1 ; + wire PCE_SNAC_OUT1 ; + wire PCE_SNAC_OUT2 ; + + pcengine_game_controller #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ), .PULSE_CLR_LINE(1'b1)) pcegc1 + ( + .i_clk(i_clk), + .i_rst(reset_on_change), + .game_controller_type(game_cont_type[3:0]), //0X4 2btn, 0X5 6btn + .i_stb(stb_clk), + .player_btn_state(pce_p1), + .busy(), + //SNAC Game controller interface + .o_clr(PCE_SNAC_OUT1), //shared for 2 controllers + .o_sel(PCE_SNAC_OUT2), //shared for 2 controllers + .i_dat({SNAC_IN7,SNAC_IO3_A,SNAC_IO6_A,SNAC_IN4}) //data from controller + ); + +wire [15:0] pce_multitap_p1, pce_multitap_p2, pce_multitap_p3, pce_multitap_p4; +wire PCE_MULTITAP_SNAC_OUT1, PCE_MULTITAP_SNAC_OUT2; + +pcengine_game_controller_multitap #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ)) pcegmutitap +( + .i_clk(i_clk), + .i_rst(reset_on_change), + .game_controller_type(game_cont_type[3:0]), //0x6 multitap + .i_stb(stb_clk), + .player1_btn_state(pce_multitap_p1), + .player2_btn_state(pce_multitap_p2), + .player3_btn_state(pce_multitap_p3), + .player4_btn_state(pce_multitap_p4), + .player5_btn_state(), + .busy(), + //SNAC Game controller interface + .o_clr(PCE_MULTITAP_SNAC_OUT1), //shared for 2 controllers + .o_sel(PCE_MULTITAP_SNAC_OUT2), //shared for 2 controllers + .i_dat({SNAC_IN7,SNAC_IO3_A,SNAC_IO6_A,SNAC_IN4}) //data from controller +); + + always @(*) begin + p1_joy_state = 32'h80808080; //analog stick neutral position value + p2_joy_state = 32'h80808080; //analog stick neutral position value + + case(game_cont_type) + // GC_DISABLED: begin + // SNAC_OUT1 = 1'b0; + // SNAC_OUT2 = 1'b0; + // p1_btn_state = 16'h0; + // p2_btn_state = 16'h0; + // p3_btn_state = 16'h0; + // p4_btn_state = 16'h0; + // end + GC_DB15, GC_DB15_FAST, GC_SNES, GC_SNES_SWAP: begin + SNAC_OUT1 = SERLAT_SNAC_OUT1; + SNAC_OUT2 = SERLAT_SNAC_OUT2; + p1_btn_state = sl_p1; + p2_btn_state = sl_p2; + p3_btn_state = 16'h0; + p4_btn_state = 16'h0; + + end + //added special case for NES Zapper + GC_NES: begin + SNAC_OUT1 = SERLAT_SNAC_OUT1; + SNAC_OUT2 = SERLAT_SNAC_OUT2; + p1_btn_state = sl_p1; //{sl_p1[15:8], ~i_D4_r[1], ~i_D3_r[1], sl_p1[5:0]}; //insert D4 and D3 at 7 and 6 bit positions (X,Y buttons) + p2_btn_state = {sl_p2[15:8], ~i_D4_r[1], ~i_D3_r[1], sl_p2[5:0]}; + p3_btn_state = 16'h0; + p4_btn_state = 16'h0; + + end + GC_PCE_2BTN, GC_PCE_6BTN: begin + SNAC_OUT1 = PCE_SNAC_OUT1; + SNAC_OUT2 = PCE_SNAC_OUT2; + p1_btn_state = pce_p1; + p2_btn_state = 16'h0; + p3_btn_state = 16'h0; + p4_btn_state = 16'h0; + end + GC_PCE_MULTITAP: begin + SNAC_OUT1 = PCE_MULTITAP_SNAC_OUT1; + SNAC_OUT2 = PCE_MULTITAP_SNAC_OUT2; + p1_btn_state = pce_multitap_p1; + p2_btn_state = pce_multitap_p2; + p3_btn_state = pce_multitap_p3; + p4_btn_state = pce_multitap_p4; + end + GC_PSX, GC_PSX_ANALOG, GC_PSX_FAST, GC_PSX_ANALOG_FAST: begin + SNAC_OUT1 = PSX_SNAC_OUT1; + SNAC_OUT2 = PSX_SNAC_OUT2; + p1_btn_state = psx_key1; + p1_joy_state = psx_joy1; + p2_btn_state = psx_key2; + p2_joy_state = psx_joy2; + p3_btn_state = 16'h0; + p4_btn_state = 16'h0; + end + default: begin + SNAC_OUT1 = 1'b0; + SNAC_OUT2 = 1'b0; + p1_btn_state = 16'h0; + p2_btn_state = 16'h0; + p3_btn_state = 16'h0; + p4_btn_state = 16'h0; + end + endcase + end +endmodule \ No newline at end of file diff --git a/analogizer/pcengine_game_controller_multitap.v b/analogizer/pcengine_game_controller_multitap.v new file mode 100644 index 0000000..ff3c6ab --- /dev/null +++ b/analogizer/pcengine_game_controller_multitap.v @@ -0,0 +1,233 @@ +//pcengine_game_controller_multitap.v +//*********************************************************************** +//* Analogizer PCEngine SNAC openFPGA interface for the Analogue Pocket * +//*********************************************************************** +// By @RndMnkIII. +// Date: 01/2024 +// Release: 1.0 + +// Aquí he documentado el funcionamiento de los diferentes mandos de juegos a los que he ido dando soporte, basado en las capturas de datos +// realizadas con analizador lógico + generador de patrones: +// +// ************ +// * PCEngine * Tested up 100KHz clr to clr (500KHz step) +// ************ +// <--------- 2BTN --------> +// <----------------- 6BTN ----------------> +// STB | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | +// ......... +// CLR : :_______________________________ +// _______________ _______ +// SEL / \_______/ \_______ +// ________ _______ _______ _______ _______ +// DATA 1 \ LDRU X RS21 X 0 X 6543 +// ^ ^ ^ ^ +// SAMPLE | | | | +// 1 2 3 4 + +// NEED TO CHECK THIS -+ +// | +// V +// +// <--------- 2BTN -------> +// <----------------- 6BTN ------------------------> +// STB | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 | +// | SCAN1 | SCAN2 | +// ..... ..... +// CLR : :___________________: :___________________ +// ___________ ___________ +// SEL / \___________/ \___________ +// _________ _________ _________ _________ +// DATA ____/ LDRU X RS21 \___/ 0 X 6543 +// ^ ^ ^ ^ ^ ^ +// SAMPLE | | | | +// 1 2 3 4 +// TEST DATA 1 +// TEST DATA 2 +// POCKET INPUTS +// 1 P1 up DO +// 0 P1 down D2 +// 1 P1 left D3 +// 0 P1 right D1 +// 0 P1 y D1 +// 1 P1 x D0 +// 0 P1 b D1 +// 1 P1 a D0 +// 1 P1 l1 D2 +// 0 P1 r1 D3 +// 0 P1 l2 -------------------------- +// 0 P1 r2 -------------------------- +// 0 P1 l3 -------------------------- +// 0 P1 r3 -------------------------- +// 0 P1 select D2 +// 1 P1 start D3 +// X +//P1 1010 0101 1000 0001 +// A 5 8 1 +//gtkwave +//p1 1010 0101 1000 0001 +// A581 +// MULTITAP (x5 Controllers): +// CLR SEL Active Port Port 1 CLR Port 1 SEL Port 2 CLR Port 2 SEL Port 3 CLR Port 3 SEL Port 4 CLR Port 4 SEL Port 5 CLR Port 5 SEL +// 1 L H None H H H H H H H H H H +// 2 H H None H H H H H H H H H H +// 3 L H 1 L H H H H H H H H H +// 4 L L 1 L L H H H H H H H H +// 5 L H 2 H H L H H H H H H H +// 6 L L 2 H H L L H H H H H H +// 7 L H 3 H H H H L H H H H H +// 8 L L 3 H H H H L L H H H H +// 9 L H 4 H H H H H H L H H H +// 10 L L 4 H H H H H H L L H H +// 11 L H 5 H H H H H H H H L H +// 12 L L 5 H H H H H H H H L L +`default_nettype none + +module pcengine_game_controller_multitap #(parameter MASTER_CLK_FREQ=50_000_000) +( + input wire i_clk, + input wire i_rst, + input wire [3:0] game_controller_type, //0x4 2btn, 0x5 6btn, 0x6 multitap + input wire i_stb, + output reg [15:0] player1_btn_state, + output reg [15:0] player2_btn_state, + output reg [15:0] player3_btn_state, + output reg [15:0] player4_btn_state, + output reg [15:0] player5_btn_state, + output reg busy, + + //SNAC Game controller interface + output wire o_clr, + output wire o_sel, + input wire [3:0] i_dat //data from controller +); + //FSM states + parameter IDLE = 3'b001; + parameter CLR = 3'b010; + parameter PRE_CLR = 3'b011; + parameter DATA = 3'b100; + + //store module settings + reg [3:0] game_controller_type_r; + + reg [6:0] state ; + + reg [4:0] counter; + reg [4:0] scan_number; + reg [4:0] counter_top_value; + reg clr_internal; + reg sel_internal; + reg [11:0] pb1_r, pb2_r, pb3_r, pb4_r, pb5_r; + + wire sample_data; + + //always sample data at falling edge of o_clk starting and second clock pulse in latch phase. + assign sample_data = ~counter[0] && i_stb && (counter > 0) && (counter <= counter_top_value); + + always @(posedge i_clk) begin + game_controller_type_r <= game_controller_type; + + //detect any change on gamepad configuration and restart FSM at IDLE state. + if(i_rst || (game_controller_type != game_controller_type_r)) begin + state <= IDLE; + pb1_r <= 12'hfff; + pb2_r <= 12'hfff; + pb3_r <= 12'hfff; + pb4_r <= 12'hfff; + pb5_r <= 12'hfff; + end + else begin + if(i_stb) begin + case(state) + IDLE: + begin + //fetch data from last read + + //button order from first to last + //0 1 2 3 4 5 6 7 8 9 10 11 + //UP RIGHT DOWN LEFT I II SELECT RUN III IV V VI + //follow Pocket game controls order: D C B A E F + // up down left right btn_y btn_x btn_b btn_a btn_l1 btn_r1 btn_l2 btn_r2 btn_l3 btn_r3 select start + //player_btn_state <= ~{pb_r[0], pb_r[2], pb_r[3], pb_r[1], pb_r[9], pb_r[8], pb_r[5], pb_r[4], pb_r[10], pb_r[11], 1'b1, 1'b1, 1'b1, 1'b1,pb_r[6],pb_r[7]}; + + // START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP + player1_btn_state <= ~{pb1_r[7], pb1_r[6], 8'b11111111, pb1_r[5], pb1_r[4],pb1_r[1], pb1_r[3], pb1_r[2], pb1_r[0]}; + player2_btn_state <= ~{pb2_r[7], pb2_r[6], 8'b11111111, pb2_r[5], pb2_r[4],pb2_r[1], pb2_r[3], pb2_r[2], pb2_r[0]}; + player3_btn_state <= ~{pb3_r[7], pb3_r[6], 8'b11111111, pb3_r[5], pb3_r[4],pb3_r[1], pb3_r[3], pb3_r[2], pb3_r[0]}; + player4_btn_state <= ~{pb4_r[7], pb4_r[6], 8'b11111111, pb4_r[5], pb4_r[4],pb4_r[1], pb4_r[3], pb4_r[2], pb4_r[0]}; + player5_btn_state <= ~{pb5_r[7], pb5_r[6], 8'b11111111, pb5_r[5], pb5_r[4],pb5_r[1], pb5_r[3], pb5_r[2], pb5_r[0]}; + + counter <= 0; + scan_number <= 0; + counter_top_value <= 5'd19; + + sel_internal <= 1'b1; + clr_internal <= 1'b0; + busy <= 1'b1; + pb1_r <= 12'hfff; + pb2_r <= 12'hfff; + pb3_r <= 12'hfff; + pb4_r <= 12'hfff; + pb5_r <= 12'hfff; + state <= PRE_CLR; + end + PRE_CLR: begin + sel_internal <= 1'b1; + clr_internal <= 1'b1; + state <= CLR; + end + + CLR: + begin + counter <= counter + 1; + sel_internal <= 1'b1; + clr_internal <= 1'b0; + pb1_r[3:0] <= i_dat; + state <= DATA; + end + DATA: + begin + counter <= counter + 1; //should be start clocking at 3 + //following data samples are get in DATA phase. + if(counter[0]) begin + sel_internal <= ~sel_internal; + scan_number <= scan_number + 1; + end + + if(sample_data) begin//read button state + case(scan_number) + //0: pb1_r[3:0] <= i_dat; + 1: pb1_r[7:4] <= i_dat; + 2: pb2_r[3:0] <= i_dat; + 3: pb2_r[7:4] <= i_dat; + 4: pb3_r[3:0] <= i_dat; + 5: pb3_r[7:4] <= i_dat; + 6: pb4_r[3:0] <= i_dat; + 7: pb4_r[7:4] <= i_dat; + 8: pb5_r[3:0] <= i_dat; + 9: pb5_r[7:4] <= i_dat; + default: + begin + pb1_r <= pb1_r; + pb2_r <= pb2_r; + pb3_r <= pb3_r; + pb4_r <= pb4_r; + pb5_r <= pb5_r; + end + endcase + end + + //the gamepads buton state are fetched at the end of DATA phase 1101 0101 + if(scan_number == 9) begin + state <= IDLE; + busy <= 1'b0; + end + end + endcase + end + end + end + + assign o_clr = (game_controller_type_r == 4'h6) ? clr_internal : 1'b0; + assign o_sel = (game_controller_type_r == 4'h6) ? sel_internal : 1'b0; +endmodule \ No newline at end of file diff --git a/analogizer/pcengine_gc.v b/analogizer/pcengine_gc.v new file mode 100644 index 0000000..6563a96 --- /dev/null +++ b/analogizer/pcengine_gc.v @@ -0,0 +1,195 @@ +//pcengine_gamecontroller.v +//*********************************************************************** +//* Analogizer PCEngine SNAC openFPGA interface for the Analogue Pocket * +//*********************************************************************** +// By @RndMnkIII. +// Date: 01/2024 +// Release: 1.0 + +// Aquí he documentado el funcionamiento de los diferentes mandos de juegos a los que he ido dando soporte, basado en las capturas de datos +// realizadas con analizador lógico + generador de patrones: +// +// ************ +// * PCEngine * Tested up 100KHz clr to clr (500KHz step) +// ************ +// <--------- 2BTN --------> +// <----------------- 6BTN ----------------> +// STB | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | +// ......... +// CLR : :_______________________________ +// _______________ _______ +// SEL / \_______/ \_______ +// ________ _______ _______ _______ _______ +// DATA 1 \ LDRU X RS21 X 0 X 6543 +// ^ ^ ^ ^ +// SAMPLE | | | | +// 1 2 3 4 + +// NEED TO CHECK THIS -+ +// | +// V +// +// <--------- 2BTN -------> +// <----------------- 6BTN ------------------------> +// STB | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 | +// | SCAN1 | SCAN2 | +// ___ ___ +// CLR | |___________________| |___________________ +// ___________ ___________ +// SEL / \___________/ \___________ +// _________ _________ _________ _________ +// DATA ____/ LDRU X RS21 \___/ 0 X 6543 +// ^ ^ ^ ^ ^ ^ +// SAMPLE | | | | +// 1 2 3 4 +`default_nettype none + +module pcengine_game_controller #(parameter MASTER_CLK_FREQ=50_000_000, parameter PULSE_CLR_LINE=1'b0) +( + input wire i_clk, + input wire i_rst, + input wire [3:0] game_controller_type, //0X4 2btn,0X5 6btn + input wire i_stb, + output reg [15:0] player_btn_state, + output reg busy, + + //SNAC Game controller interface + output wire o_clr, + output wire o_sel, + input wire [3:0] i_dat //data from controller +); + + + //FSM states + parameter IDLE = 3'b001; + parameter CLR = 3'b010; + parameter DATA = 3'b100; + + //store module settings + reg [3:0] game_controller_type_r; + + wire pulse_clr = PULSE_CLR_LINE; + + reg [2:0] state ; + + reg [3:0] counter; + reg [3:0] scan_number; + reg [3:0] counter_top_value; + reg clr_internal; + reg sel_internal; + reg [11:0] pb_r; + + + wire latch_level,disable_clock_on_latch; + wire sample_data; + + reg btn6; + + //always sample data at falling edge of o_clk starting and second clock pulse in latch phase. + assign sample_data = ~counter[0] && i_stb && (counter > 0) && (counter <= counter_top_value); + + always @(posedge i_clk) begin + game_controller_type_r <= game_controller_type; + + //detect any change on gamepad configuration and restart FSM at IDLE state. + if(i_rst || (game_controller_type != game_controller_type_r)) begin + state <= IDLE; + pb_r <= 12'hfff; + end + else begin + if(i_stb) begin + case(state) + IDLE: + begin + //fetch data from last read + + //button order from first to last + //0 1 2 3 4 5 6 7 8 9 10 11 + //UP RIGHT DOWN LEFT I II SELECT RUN III IV V VI + //follow Pocket game controls order: D C B A E F + + + if(game_controller_type_r == 4'h5) begin + //6btn mapping + // START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP + // 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + player_btn_state <= ~{pb_r[7], pb_r[6], 4'b1111, pb_r[11], pb_r[10], pb_r[9], pb_r[8], pb_r[5], pb_r[4], pb_r[1], pb_r[3], pb_r[2], pb_r[0]}; + end + else if (game_controller_type_r == 4'h4) begin + //2btn mapping RUN+A = X, RUN+B = Y not implemented + // START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP + player_btn_state <= ~{pb_r[7], pb_r[6], 6'b111111, 1'b1, 1'b1, pb_r[5], pb_r[4], pb_r[1], pb_r[3], pb_r[2], pb_r[0]}; + end + else begin + player_btn_state <= 16'h0; + end + counter <= 0; + scan_number <= 0; + + // if (game_controller_type_r == 5'd4) counter_top_value <= 4'd4; + // else if(game_controller_type_r == 5'd5) counter_top_value <= 4'd8; + counter_top_value <= 4'd4; + sel_internal <= 1'b1; + clr_internal <= pulse_clr; + busy <= 1'b1; + //if (~btn6) pb_r <= 12'hfff; + state <= CLR; + end + CLR: + begin + counter <= counter + 1; + if (counter == 1) begin + state <= DATA; + sel_internal <= 1'b1; + clr_internal <= 1'b0; + end + end + DATA: + begin + counter <= counter + 1; //should be start clocking at 3 + //following data samples are get in DATA phase. + if(counter[0]) begin + sel_internal <= ~sel_internal; + scan_number <= scan_number + 1; + end + + if(sample_data) begin//read button state + case(scan_number) + 0: begin + if(i_dat == 4'b0000) begin + btn6 <= 1'b1; + //pb_r[3:0] <= pb_r[3:0]; + end + else begin + btn6 <= 1'b0; + pb_r[3:0] <= i_dat; + end + end + 1: begin + if(btn6) begin + pb_r[11:8] <= i_dat; + end + else begin + pb_r[7:4] <= i_dat; + end + //btn6 <= 1'b0; + end + // 3: pb_r[11:8] <= i_dat; + default: pb_r <= pb_r; + endcase + end + + //the gamepads buton state are fetched at the end of DATA phase + if(counter == counter_top_value) begin + state <= IDLE; + busy <= 1'b0; + end + end + endcase + end + end + end + + assign o_clr = (game_controller_type_r == 4'd0) ? 1'b0 : clr_internal; + assign o_sel = (game_controller_type_r == 4'd0) ? 1'b0 : sel_internal; +endmodule \ No newline at end of file diff --git a/analogizer/psPAD_top.v b/analogizer/psPAD_top.v new file mode 100644 index 0000000..e3ec1b6 --- /dev/null +++ b/analogizer/psPAD_top.v @@ -0,0 +1,664 @@ +//------------------------------------------------------------------- +// +// PLAYSTATION CONTROLLER(DUALSHOCK TYPE) INTERFACE TOP +// +// Version : 2.00 +// +// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved +// +// Important ! +// +// This program is freeware for non-commercial use. +// An author does no guarantee about this program. +// You can use this under your own risk. +// +// 2003.10.30 It is optimized . by K Degawa +// +//------------------------------------------------------------------- +`timescale 100ps/10ps + +//--------- SIMULATION ---------------------------------------------- +//`define SIMULATION_1 + +`ifdef SIMULATION_1 +`define Timer_siz 18 +`else +`define Timer_siz 12 +`endif +//------------------------------------------------------------------- +`define Dualshock + +module psPAD_top( + +I_CLK250K, // MAIN CLK 250KHz +I_RSTn, // MAIN RESET + +O_psCLK, // psCLK CLK OUT +O_psSEL, // psSEL OUT +O_psTXD, // psTXD OUT +I_psRXD, // psRXD IN +O_RXD_1, // RX DATA 1 (8bit) +O_RXD_2, // RX DATA 2 (8bit) +O_RXD_3, // RX DATA 3 (8bit) +O_RXD_4, // RX DATA 4 (8bit) +O_RXD_5, // RX DATA 5 (8bit) +O_RXD_6, // RX DATA 6 (8bit) +I_CONF_SW, // Dualshook Config ACTIVE-HI +I_MODE_SW, // Dualshook Mode Set DEGITAL PAD 0: ANALOG PAD 1: +I_MODE_EN, // Dualshook Mode Control OFF 0: ON 1: +I_VIB_SW, // Vibration SW VIB_SW[0] Small Moter OFF 0:ON 1: + // VIB_SW[1] Bic Moter OFF 0:ON 1(Dualshook Only) +I_VIB_DAT // Vibration(Bic Moter)Data 8'H00-8'HFF (Dualshook Only) + +); + +input I_CLK250K,I_RSTn; +input I_CONF_SW; +input I_MODE_SW,I_MODE_EN; +input [1:0]I_VIB_SW; +input [7:0]I_VIB_DAT; +input I_psRXD; +output O_psCLK; +output O_psSEL; +output O_psTXD; +output [7:0]O_RXD_1; +output [7:0]O_RXD_2; +output [7:0]O_RXD_3; +output [7:0]O_RXD_4; +output [7:0]O_RXD_5; +output [7:0]O_RXD_6; + +wire W_scan_seq_pls; +wire W_type; +wire [3:0]W_byte_cnt; +wire W_RXWT; +wire W_TXWT; +wire W_TXSET; +wire W_TXEN; +wire [7:0]W_TXD_DAT; +wire [7:0]W_RXD_DAT; +wire W_conf_ent; + +ps_pls_gan pls( + +.I_CLK(I_CLK250K), +.I_RSTn(I_RSTn), +.I_TYPE(W_type), // DEGITAL PAD 0: ANALOG PAD 1: + +.O_SCAN_SEQ_PLS(W_scan_seq_pls), +.O_RXWT(W_RXWT), +.O_TXWT(W_TXWT), +.O_TXSET(W_TXSET), +.O_TXEN(W_TXEN), +.O_psCLK(O_psCLK), +.O_psSEL(O_psSEL), +.O_byte_cnt(W_byte_cnt), + +//.Timer(O_Timer) +.Timer() + +); + +`ifdef Dualshock +txd_commnd cmd( +.I_CLK(W_TXSET), +.I_RSTn(I_RSTn), +.I_BYTE_CNT(W_byte_cnt), +.I_MODE({I_CONF_SW,~I_MODE_EN,I_MODE_SW}), +.I_VIB_SW(I_VIB_SW), +.I_VIB_DAT(I_VIB_DAT), +.I_RXD_DAT(W_RXD_DAT), +.O_TXD_DAT(W_TXD_DAT), +.O_TYPE(W_type), +.O_CONF_ENT(W_conf_ent) + +); + +`else +txd_commnd_EZ cmd( + +.I_CLK(W_TXSET), +.I_RSTn(I_RSTn), +.I_BYTE_CNT(W_byte_cnt), +.I_MODE(), +.I_VIB_SW(I_VIB_SW), +.I_VIB_DAT(), +.I_RXD_DAT(), +.O_TXD_DAT(W_TXD_DAT), +.O_TYPE(W_type), +.O_CONF_ENT(W_conf_ent) + +); + +`endif + +ps_txd txd( + +.I_CLK(I_CLK250K), +.I_RSTn(I_RSTn), +.I_WT(W_TXWT), +.I_EN(W_TXEN), +.I_TXD_DAT(W_TXD_DAT), +.O_psTXD(O_psTXD) + +); + +ps_rxd rxd( + +.I_CLK(O_psCLK), +.I_RSTn(I_RSTn), +.I_WT(W_RXWT), +.I_psRXD(I_psRXD), +.O_RXD_DAT(W_RXD_DAT) + +); + +//---------- RXD DATA DEC ---------------------------------------- +reg [7:0]O_RXD_1; +reg [7:0]O_RXD_2; +reg [7:0]O_RXD_3; +reg [7:0]O_RXD_4; +reg [7:0]O_RXD_5; +reg [7:0]O_RXD_6; + +reg W_rxd_mask; +always@(posedge W_scan_seq_pls) + W_rxd_mask <= ~W_conf_ent; + +always@(negedge W_RXWT) +begin + if(W_rxd_mask)begin + case(W_byte_cnt) + 3: O_RXD_1 <= W_RXD_DAT; + 4: O_RXD_2 <= W_RXD_DAT; + 5: O_RXD_3 <= W_RXD_DAT; + 6: O_RXD_4 <= W_RXD_DAT; + 7: O_RXD_5 <= W_RXD_DAT; + 8: O_RXD_6 <= W_RXD_DAT; + default:; + endcase + end +end + +endmodule + +`ifdef Dualshock +//.I_MODE({I_CONF_SW,~I_MODE_EN,I_MODE_SW}), +module txd_commnd_EZ( + +I_CLK, +I_RSTn, +I_BYTE_CNT, +I_MODE, +I_VIB_SW, +I_VIB_DAT, +I_RXD_DAT, +O_TXD_DAT, +O_TYPE, +O_CONF_ENT + +); + +input I_CLK,I_RSTn; +input [3:0]I_BYTE_CNT; +input [2:0]I_MODE; +input [1:0]I_VIB_SW; +input [7:0]I_VIB_DAT; +input [7:0]I_RXD_DAT; +output [7:0]O_TXD_DAT; +output O_TYPE; +output O_CONF_ENT; + +reg [7:0]O_TXD_DAT; + +assign O_TYPE = 1'b1; +assign O_CONF_ENT = 1'b0; +always@(posedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn)begin + O_TXD_DAT <= 8'h00; + end + else begin + case(I_BYTE_CNT) + 0:O_TXD_DAT <= 8'h01; + 1:O_TXD_DAT <= 8'h42; + 3:begin + if(I_VIB_SW) O_TXD_DAT <= 8'h40; + else O_TXD_DAT <= 8'h00; + end + 4:begin + if(I_VIB_SW) O_TXD_DAT <= 8'h01; + else O_TXD_DAT <= 8'h00; + end + default: O_TXD_DAT <= 8'h00; + endcase + end +end + +endmodule +`endif + +module txd_commnd( + +I_CLK, +I_RSTn, +I_BYTE_CNT, +I_MODE, +I_VIB_SW, +I_VIB_DAT, +I_RXD_DAT, +O_TXD_DAT, +O_TYPE, +O_CONF_ENT + +); + +input I_CLK,I_RSTn; +input [3:0]I_BYTE_CNT; +input [2:0]I_MODE; +input [1:0]I_VIB_SW; +input [7:0]I_VIB_DAT; +input [7:0]I_RXD_DAT; +output [7:0]O_TXD_DAT; +output O_TYPE; +output O_CONF_ENT; + +wire [1:0]pad_mode = I_MODE[1:0]; +wire ds_sw = I_MODE[2]; + +reg [7:0]O_TXD_DAT; +reg [2:0]conf_state; +reg conf_entry; +reg conf_ent_reg; +reg conf_done; +reg pad_status; +reg pad_id; + +assign O_TYPE = pad_id; +assign O_CONF_ENT = conf_entry; + +always@(posedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn) pad_id <= 1'b0; + else begin + if(I_BYTE_CNT==2)begin + case(I_RXD_DAT) //------ GET TYPE(Byte_SEQ) + 8'h23: pad_id <= 1'b1; + 8'h41: pad_id <= 1'b0; + 8'h53: pad_id <= 1'b1; + 8'h73: pad_id <= 1'b1; + 8'hE3: pad_id <= 1'b1; + 8'hF3: pad_id <= 1'b1; + default: pad_id <= 1'b0; + endcase + end + end +end + +always@(posedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn)begin + O_TXD_DAT <= 8'h00; + conf_entry <= 1'b0; + conf_ent_reg <= 1'b0; + conf_done <= 1'b1; + conf_state <= 0; + pad_status <= 0; + end + else begin +//---------- nomal mode -------------------------------------------------------- +//----------------- read_data_and_vibrate_ex 01,42,00,WW,PP(,00,00,00,00) +// --,ID,SS,XX,XX(,XX,XX,XX,XX) + if(~conf_entry)begin + case(I_BYTE_CNT) + 0:O_TXD_DAT <= 8'h01; + 1:O_TXD_DAT <= 8'h42; + 3:begin + if(I_RXD_DAT==8'h00) conf_ent_reg <= 1'b1; + if(pad_status)begin + if(I_VIB_SW[0]) O_TXD_DAT <= 8'h01; + else O_TXD_DAT <= 8'h00; + end + else begin + if(I_VIB_SW[0] | I_VIB_SW[1]) O_TXD_DAT <= 8'h40; + else O_TXD_DAT <= 8'h00; + end + end + 4:begin + if(pad_status)begin + if(I_VIB_SW[1]) O_TXD_DAT <= I_VIB_DAT; + else O_TXD_DAT <= 8'h00; + end + else begin + if(I_VIB_SW[0] | I_VIB_SW[1]) O_TXD_DAT <= 8'h01; + else O_TXD_DAT <= 8'h00; + end + if(pad_id==0)begin + if(conf_state == 0 && ds_sw) + conf_entry <= 1'b1; + if(conf_state == 7 && (pad_status&conf_ent_reg))begin + conf_state <= 0; + conf_entry <= 1'b1; + end + end + end + 8:begin + O_TXD_DAT <= 8'h00; + if(pad_id==1)begin + if(conf_state == 0 && ds_sw) + conf_entry <= 1'b1; + if(conf_state == 7 && (pad_status&conf_ent_reg))begin + conf_state <= 0; + conf_entry <= 1'b1; + end + end + end + default: O_TXD_DAT <= 8'h00; + endcase + end +//---------- confg mode -------------------------------------------------------- + else begin + case(conf_state) + //-------- config_mode_enter (43): 01,43,00,01,00(,00 x 4 or XX x 16) + // --,ID,SS,XX,XX(,XX x 4 or XX x 16) + 0:begin + case(I_BYTE_CNT) + 0:begin + O_TXD_DAT <= 8'h01; + conf_done <= 1'b0; + end + 1:O_TXD_DAT <= 8'h43; + 3:O_TXD_DAT <= 8'h01; + 4:begin + O_TXD_DAT <= 8'h00; + if(pad_id==0)begin + if(pad_status) conf_state <= 3; + else conf_state <= 1; + end + end + 8:begin + O_TXD_DAT <= 8'h00; + if(pad_id==1)begin + if(pad_status) conf_state <= 3; + else conf_state <= 1; + end + end + default:O_TXD_DAT <= 8'h00; + endcase + end + //-------- query_model_and_mode (45): 01,45,00,5A,5A,5A,5A,5A,5A + // FF,F3,5A,TT,02,MM,VV,01,00 + 1:begin + case(I_BYTE_CNT) + 0:O_TXD_DAT <= 8'h01; + 1:O_TXD_DAT <= 8'h45; + 2:begin + O_TXD_DAT <= 8'h00; + conf_done <= (I_RXD_DAT == 8'hF3)? 1'b0:1'b1; + end + 4:begin + O_TXD_DAT <= 8'h00; + if(I_RXD_DAT==8'h01 || I_RXD_DAT==8'h03) pad_status <= 1; + if(pad_id==0 && conf_done==1'b1)begin + conf_state <= 7; + conf_entry <= 1'b0; + end + end + 8:begin + O_TXD_DAT <= 8'h00; + conf_state <= 2; + if(pad_id==1 && conf_done==1'b1)begin + conf_state <= 7; + conf_entry <= 1'b0; + end + end + default:O_TXD_DAT <= 8'h00; + endcase + end + //-------- set_mode_and_lock (44): 01,44,00,XX,YY,00,00,00,00 + // --,F3,5A,00,00,00,00,00,00 + 2:begin + case(I_BYTE_CNT) + 0:O_TXD_DAT <= 8'h01; + 1:O_TXD_DAT <= 8'h44; + 3:O_TXD_DAT <= pad_mode[0] ? 8'h01:8'h00; + 4:O_TXD_DAT <= pad_mode[1] ? 8'h03:8'h00; + 8:begin + O_TXD_DAT <= 8'h00; + conf_state<= 3; + end + default:O_TXD_DAT <= 8'h00; + endcase + end + //-------- vibration_enable (4D): 01,4D,00,00,01,FF,FF,FF,FF + // --,F3,5A,XX,YY,FF,FF,FF,FF + 3:begin + case(I_BYTE_CNT) + 0:O_TXD_DAT <= 8'h01; + 1:O_TXD_DAT <= 8'h4D; + 2,3:O_TXD_DAT <= 8'h00; + 4:O_TXD_DAT <= 8'h01; + 8:begin + O_TXD_DAT <= 8'hFF; + conf_state<= 6; + end + default:O_TXD_DAT <= 8'hFF; + endcase + end + //-------- config_mode_exit (43): 01,43,00,00,5A,5A,5A,5A,5A + // --,F3,5A,00,00,00,00,00,00 + 6:begin + case(I_BYTE_CNT) + 0:O_TXD_DAT <= 8'h01; + 1:O_TXD_DAT <= 8'h43; + 2,3:O_TXD_DAT <= 8'h00; + 8:begin + O_TXD_DAT <= 8'h5A; + conf_state<= 7; + conf_entry<= 1'b0; + conf_done <= 1'b1; + conf_ent_reg<= 1'b0; + end + default:O_TXD_DAT <= 8'h5A; + endcase + end + default:; + endcase + end + end +end + +endmodule + +module ps_pls_gan( + +I_CLK, +I_RSTn, +I_TYPE, + +O_SCAN_SEQ_PLS, +O_RXWT, +O_TXWT, +O_TXSET, +O_TXEN, +O_psCLK, +O_psSEL, +O_byte_cnt, + +Timer + +); + +parameter Timer_size = `Timer_siz; + +input I_CLK,I_RSTn; +input I_TYPE; +output O_SCAN_SEQ_PLS; +output O_RXWT; +output O_TXWT; +output O_TXSET; +output O_TXEN; +output O_psCLK; +output O_psSEL; +output [3:0]O_byte_cnt; + +output [Timer_size-1:0]Timer; +reg [Timer_size-1:0]Timer; + +reg O_SCAN_SEQ_PLS; +reg RXWT; +reg TXWT; +reg TXSET; +reg psCLK_gate; +reg psSEL; +reg [3:0]O_byte_cnt; + +always@(posedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn) Timer <= 0; + else Timer <= Timer+1; +end + +always@(posedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn) + O_SCAN_SEQ_PLS <= 0; + else begin + if(Timer == 0) O_SCAN_SEQ_PLS <= 1; + else O_SCAN_SEQ_PLS <= 0; + end +end + +always@(posedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn) + begin + psCLK_gate <= 1; + RXWT <= 0; + TXWT <= 0; + TXSET <= 0; + end + else begin + case(Timer[4:0]) + 6: TXSET <= 1; + 8: TXSET <= 0; + 9: TXWT <= 1; + 11: TXWT <= 0; + 12: psCLK_gate <= 0; + 20: psCLK_gate <= 1; + 21: RXWT <= 1; + 23: RXWT <= 0; + default:; + endcase + end +end + +always@(posedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn) + psSEL <= 1; + else begin + if(O_SCAN_SEQ_PLS == 1) + psSEL <= 0; + else if((I_TYPE == 0)&&(Timer == 158)) + psSEL <= 1; + else if((I_TYPE == 1)&&(Timer == 286)) + psSEL <= 1; + end +end + +always@(posedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn) + O_byte_cnt <= 0; + else begin + if( O_SCAN_SEQ_PLS == 1) + O_byte_cnt <= 0; + else begin + if( Timer[4:0] == 5'b11111)begin + if(I_TYPE == 0 && O_byte_cnt == 5) + O_byte_cnt <= O_byte_cnt; + else if(I_TYPE == 1 && O_byte_cnt == 9) + O_byte_cnt <= O_byte_cnt; + else + O_byte_cnt <= O_byte_cnt+1; + end + end + end +end + +assign O_psCLK = psCLK_gate | I_CLK | psSEL; +assign O_psSEL = psSEL; +assign O_RXWT = ~psSEL&RXWT; +assign O_TXSET = ~psSEL&TXSET; +assign O_TXWT = ~psSEL&TXWT; +assign O_TXEN = ~psSEL&(~psCLK_gate); + +endmodule + +module ps_rxd( + +I_CLK, +I_RSTn, +I_WT, +I_psRXD, +O_RXD_DAT + +); + +input I_CLK,I_RSTn,I_WT; +input I_psRXD; +output [7:0]O_RXD_DAT; +reg [7:0]O_RXD_DAT; +reg [7:0]sp; + +always@(posedge I_CLK or negedge I_RSTn) + if(! I_RSTn) sp <= 1; + else sp <= { I_psRXD, sp[7:1]}; +always@(posedge I_WT or negedge I_RSTn) + if(! I_RSTn) O_RXD_DAT <= 1; + else O_RXD_DAT <= sp; + +endmodule + +module ps_txd( + +I_CLK, +I_RSTn, +I_WT, +I_EN, +I_TXD_DAT, +O_psTXD + +); + +input I_CLK,I_RSTn; +input I_WT,I_EN; +input [7:0]I_TXD_DAT; +output O_psTXD; +reg O_psTXD; +reg [7:0]ps; + +always@(negedge I_CLK or negedge I_RSTn) +begin + if(! I_RSTn)begin + O_psTXD <= 1; + ps <= 0; + end + else begin + if(I_WT) + ps <= I_TXD_DAT; + else begin + if(I_EN)begin + O_psTXD <= ps[0]; + ps <= {1'b1, ps[7:1]}; + end + else begin + O_psTXD <= 1'd1; + ps <= ps; + end + end + end +end + +endmodule \ No newline at end of file diff --git a/analogizer/psx_control.v b/analogizer/psx_control.v new file mode 100644 index 0000000..f66d48a --- /dev/null +++ b/analogizer/psx_control.v @@ -0,0 +1,123 @@ +module psx_control(clk_50mhz, + I_psRXD, + O_psCLK, + O_psSEL, + O_psTXD, + O_l1, + O_l2, + O_r1, + O_r2, + O_l3, + O_r3, + O_d_pad_up, + O_d_pad_down, + O_d_pad_left, + O_d_pad_right, + O_square, + O_triangle, + O_circle, + O_x, + O_select, + O_start, + O_analog1_left_right, + O_analog2_left_right, + O_analog1_up_down, + O_analog2_up_down, + switches + ); + +input clk_50mhz; // 50Mhz +input I_psRXD; +output O_psCLK; +output O_psSEL; +output O_psTXD; +output O_l1; +output O_l2; +output O_r1; +output O_r2; +output O_l3; +output O_r3; +output O_d_pad_up; +output O_d_pad_down; +output O_d_pad_left; +output O_d_pad_right; +output O_square; +output O_triangle; +output O_circle; +output O_x; +output O_select; +output O_start; +output [7:0]O_analog1_left_right; +output [7:0]O_analog2_left_right; +output [7:0]O_analog1_up_down; +output [7:0]O_analog2_up_down; +input [1:0]switches; + + +wire [7:0]data_to_psx1; +wire [7:0]data_to_psx2; +wire [7:0]data_to_psx3; +wire [7:0]data_to_psx4; +wire [7:0]data_to_psx5; +wire [7:0]data_to_psx6; + + +// BUTTONS PSX +assign O_d_pad_up=~data_to_psx1[4]; +assign O_d_pad_down=~data_to_psx1[6]; +assign O_d_pad_left=~data_to_psx1[5]; +assign O_d_pad_right=~data_to_psx1[7]; + +assign O_select=~data_to_psx1[0]; +assign O_start=~data_to_psx1[3]; +assign O_l3=~data_to_psx1[1]; +assign O_r3=~data_to_psx1[2]; +assign O_l1=~data_to_psx2[2]; +assign O_r1=~data_to_psx2[3]; +assign O_l2=~data_to_psx2[0]; +assign O_r2=~data_to_psx2[1]; +assign O_triangle=~data_to_psx2[4]; +assign O_square=~data_to_psx2[7]; +assign O_circle=~data_to_psx2[5]; +assign O_x=~data_to_psx2[6]; + +assign O_analog1_left_right=data_to_psx3[7:0]; +assign O_analog2_left_right=data_to_psx5[7:0]; +assign O_analog1_up_down=data_to_psx4[7:0]; +assign O_analog2_up_down=data_to_psx6[7:0]; + + +wire CLK_FSM_PSX; + +/*DIVISOR DE FRECUENCIA PARA GENERAR CLK DE LA FSM DEL DECODIFICADOR DE PSX*/ +pll pll_inst ( + .inclk0 ( clk_50mhz ), + .c0 ( CLK_FSM_PSX ), + .c1 ( ) + ); + + +psPAD_top psPAD_top_inst +( + .I_CLK250K(CLK_FSM_PSX) , // input I_CLK250K_sig + .I_RSTn(1'b1) , // input I_RSTn_sig + .O_psCLK(O_psCLK) , // output O_psCLK_sig + .O_psSEL(O_psSEL) , // output O_psSEL_sig + .O_psTXD(O_psTXD) , // output O_psTXD_sig + .I_psRXD(I_psRXD) , // input I_psRXD_sig + .O_RXD_1(data_to_psx1) , // output [7:0] O_RXD_1_sig + .O_RXD_2(data_to_psx2) , // output [7:0] O_RXD_2_sig + .O_RXD_3(data_to_psx3) , // output [7:0] O_RXD_3_sig + .O_RXD_4(data_to_psx4) , // output [7:0] O_RXD_4_sig + .O_RXD_5(data_to_psx5) , // output [7:0] O_RXD_5_sig + .O_RXD_6(data_to_psx6) , // output [7:0] O_RXD_6_sig + .I_CONF_SW(1'b1) , // input I_CONF_SW_sig + .I_MODE_SW(1'b1) , // input I_MODE_SW_sig + .I_MODE_EN(1'b1) , // input I_MODE_EN_sig + .I_VIB_SW(switches) , // input [1:0] I_VIB_SW_sig + .I_VIB_DAT(8'hff) // input [7:0] I_VIB_DAT_sig +); + + + +endmodule diff --git a/analogizer/scandoubler.v b/analogizer/scandoubler.v new file mode 100644 index 0000000..9437526 --- /dev/null +++ b/analogizer/scandoubler.v @@ -0,0 +1,289 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// AMR - generates and output a pixel clock with a reliable phase relationship with +// with the scandoubled hsync pulse. Allows the incoming data to be sampled more +// sparsely, reducing block RAM usage. ce_x1/x2 are replaced with a ce_divider +// which is the largest value the counter will reach before resetting - so 3'111 to +// divide clk_sys by 8, 3'011 to divide by 4, 3'101 to divide by six. + +// Also now has a bypass mode, in which the incoming data will be scaled to the output +// width but otherwise unmodified. Simplifies the rest of the video chain. + + +module scandoubler +( + // system interface + input clk_sys, + + input bypass, + + // Pixelclock + input [2:0] ce_divider, // 0 - clk_sys/4, 1 - clk_sys/2, 2 - clk_sys/3, 3 - clk_sys/4, etc. + output pixel_ena, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // shifter video interface + input hb_in, + input vb_in, + input hs_in, + input vs_in, + input [COLOR_DEPTH-1:0] r_in, + input [COLOR_DEPTH-1:0] g_in, + input [COLOR_DEPTH-1:0] b_in, + + // output interface + output hb_out, + output vb_out, + output hs_out, + output vs_out, + output [OUT_COLOR_DEPTH-1:0] r_out, + output [OUT_COLOR_DEPTH-1:0] g_out, + output [OUT_COLOR_DEPTH-1:0] b_out +); + +parameter HCNT_WIDTH = 9; // Resolution of scandoubler buffer +parameter COLOR_DEPTH = 6; // Bits per colour to be stored in the buffer +parameter HSCNT_WIDTH = 12; // Resolution of hsync counters +parameter OUT_COLOR_DEPTH = 6; // Bits per color outputted + +// --------------------- create output signals ----------------- +// latch everything once more to make it glitch free and apply scanline effect +reg scanline; +reg [OUT_COLOR_DEPTH-1:0] r; +reg [OUT_COLOR_DEPTH-1:0] g; +reg [OUT_COLOR_DEPTH-1:0] b; + +wire [COLOR_DEPTH*3-1:0] sd_mux = bypass ? {r_in, g_in, b_in} : sd_out[COLOR_DEPTH*3-1:0]; + +localparam m = OUT_COLOR_DEPTH/COLOR_DEPTH; +localparam n = OUT_COLOR_DEPTH%COLOR_DEPTH; + +always @(*) begin + if (n>0) begin + b = { {m{sd_mux[COLOR_DEPTH-1:0]}}, sd_mux[COLOR_DEPTH-1 -:n] }; + g = { {m{sd_mux[COLOR_DEPTH*2-1:COLOR_DEPTH]}}, sd_mux[COLOR_DEPTH*2-1 -:n] }; + r = { {m{sd_mux[COLOR_DEPTH*3-1:COLOR_DEPTH*2]}}, sd_mux[COLOR_DEPTH*3-1 -:n] }; + end else begin + b = { {m{sd_mux[COLOR_DEPTH-1:0]}} }; + g = { {m{sd_mux[COLOR_DEPTH*2-1:COLOR_DEPTH]}} }; + r = { {m{sd_mux[COLOR_DEPTH*3-1:COLOR_DEPTH*2]}} }; + end +end + + +reg [OUT_COLOR_DEPTH+6:0] r_mul; +reg [OUT_COLOR_DEPTH+6:0] g_mul; +reg [OUT_COLOR_DEPTH+6:0] b_mul; +reg hb_o; +reg vb_o; +reg hs_o; +reg vs_o; + +wire scanline_bypass = (!scanline) | (!(|scanlines)) | bypass; + +// More subtle variant of the scanlines effect. +// 0 00 -> 1000000 0x40 - bypass / inert mode +// 1 01 -> 0111010 0x3a - 25% +// 2 10 -> 0101110 0x2e - 50% +// 3 11 -> 0011010 0x1a - 75% + +wire [6:0] scanline_coeff = scanline_bypass ? + 7'b1000000 : {~(&scanlines),scanlines[0],1'b1,~scanlines[0],2'b10}; + +always @(posedge clk_sys) begin + if(ce_x2) begin + hs_o <= hs_sd; + vs_o <= vs_sd; + hb_o <= hb_sd; + vb_o <= vb_sd; + + // reset scanlines at every new screen + if(vs_o != vs_in) scanline <= 0; + + // toggle scanlines at begin of every hsync + if(hs_o && !hs_sd) scanline <= !scanline; + + r_mul<=r*scanline_coeff; + g_mul<=g*scanline_coeff; + b_mul<=b*scanline_coeff; + end +end + +wire [OUT_COLOR_DEPTH-1:0] r_o = r_mul[OUT_COLOR_DEPTH+5 -:OUT_COLOR_DEPTH]; +wire [OUT_COLOR_DEPTH-1:0] g_o = g_mul[OUT_COLOR_DEPTH+5 -:OUT_COLOR_DEPTH]; +wire [OUT_COLOR_DEPTH-1:0] b_o = b_mul[OUT_COLOR_DEPTH+5 -:OUT_COLOR_DEPTH]; + +// Output multiplexing +wire blank_out = hb_out | vb_out; +assign r_out = blank_out ? {OUT_COLOR_DEPTH{1'b0}} : bypass ? r : r_o; +assign g_out = blank_out ? {OUT_COLOR_DEPTH{1'b0}} : bypass ? g : g_o; +assign b_out = blank_out ? {OUT_COLOR_DEPTH{1'b0}} : bypass ? b : b_o; +assign hb_out = bypass ? hb_in : hb_o; +assign vb_out = bypass ? vb_in : vb_o; +assign hs_out = bypass ? hs_in : hs_o; +assign vs_out = bypass ? vs_in : vs_o; + + +// scan doubler output register +reg [COLOR_DEPTH*3-1:0] sd_out; + +// ================================================================== +// ======================== the line buffers ======================== +// ================================================================== + +// 2 lines of 2**HCNT_WIDTH pixels 3*COLOR_DEPTH bit RGB +(* ramstyle = "no_rw_check" *) reg [COLOR_DEPTH*3-1:0] sd_buffer[2*2**HCNT_WIDTH]; + +// use alternating sd_buffers when storing/reading data +reg line_toggle; + +// total hsync time (in 16MHz cycles), hs_total reaches 1024 +reg [HCNT_WIDTH-1:0] hcnt; +reg [HSCNT_WIDTH:0] hs_max; +reg [HSCNT_WIDTH:0] hs_rise; +reg [HCNT_WIDTH:0] hb_fall[2]; +reg [HCNT_WIDTH:0] hb_rise[2]; +reg [HCNT_WIDTH+1:0] vb_event[2]; +reg [HCNT_WIDTH+1:0] vs_event[2]; +reg [HSCNT_WIDTH:0] synccnt; + +// Input pixel clock, aligned with input sync: +wire[2:0] ce_divider_adj = |ce_divider ? ce_divider : 3'd3; // 0 = clk/4 for compatiblity +reg [2:0] ce_divider_in; +reg [2:0] ce_divider_out; + +reg [2:0] i_div; +wire ce_x1 = (i_div == ce_divider_in); + +always @(posedge clk_sys) begin + reg hsD, vsD; + reg vbD; + reg hbD; + + // Pixel logic on x1 clkena + if(ce_x1) begin + hcnt <= hcnt + 1'd1; + vsD <= vs_in; + vbD <= vb_in; + + sd_buffer[{line_toggle, hcnt}] <= {r_in, g_in, b_in}; + if (vbD ^ vb_in) vb_event[line_toggle] <= {1'b1, vb_in, hcnt}; + if (vsD ^ vs_in) vs_event[line_toggle] <= {1'b1, vs_in, hcnt}; + // save position of hblank + hbD <= hb_in; + if(!hbD && hb_in) hb_rise[line_toggle] <= {1'b1, hcnt}; + if( hbD && !hb_in) hb_fall[line_toggle] <= {1'b1, hcnt}; + end + + // Generate pixel clock + i_div <= i_div + 1'd1; + + if (i_div==ce_divider_adj) i_div <= 3'b000; + + synccnt <= synccnt + 1'd1; + hsD <= hs_in; + if(hsD && !hs_in) begin + // At hsync latch the ce_divider counter limit for the input clock + // and pass the previous input clock limit to the output stage. + // This should give correct output if the pixel clock changes mid-screen. + ce_divider_out <= ce_divider_in; + ce_divider_in <= ce_divider_adj; + hs_max <= {1'b0,synccnt[HSCNT_WIDTH:1]}; + hcnt <= 0; + synccnt <= 0; + i_div <= 3'b000; + end + + // save position of rising edge + if(!hsD && hs_in) hs_rise <= {1'b0,synccnt[HSCNT_WIDTH:1]}; + + // begin of incoming hsync + if(hsD && !hs_in) begin + line_toggle <= !line_toggle; + vb_event[!line_toggle] <= 0; + vs_event[!line_toggle] <= 0; + hb_rise[!line_toggle][HCNT_WIDTH] <= 0; + hb_fall[!line_toggle][HCNT_WIDTH] <= 0; + end + +end + +// ================================================================== +// ==================== output timing generation ==================== +// ================================================================== + +reg [HSCNT_WIDTH:0] sd_synccnt; +reg [HCNT_WIDTH-1:0] sd_hcnt; +reg vb_sd = 0; +reg hb_sd = 0; +reg hs_sd = 0; +reg vs_sd = 0; + +// Output pixel clock, aligned with output sync: +reg [2:0] sd_i_div; +wire ce_x2 = (sd_i_div == ce_divider_out) | (sd_i_div == {1'b0,ce_divider_out[2:1]}); + +// timing generation runs 32 MHz (twice the input signal analysis speed) +always @(posedge clk_sys) begin + reg hsD; + + // Output logic on x2 clkena + if(ce_x2) begin + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + + // read data from line sd_buffer + sd_out <= sd_buffer[{~line_toggle, sd_hcnt}]; + + // Handle VBlank event + if(vb_event[~line_toggle][HCNT_WIDTH+1] && sd_hcnt == vb_event[~line_toggle][HCNT_WIDTH-1:0]) vb_sd <= vb_event[~line_toggle][HCNT_WIDTH]; + // Handle VSync event + if(vs_event[~line_toggle][HCNT_WIDTH+1] && sd_hcnt == vs_event[~line_toggle][HCNT_WIDTH-1:0]) vs_sd <= vs_event[~line_toggle][HCNT_WIDTH]; + // Handle HBlank events + if(hb_rise[~line_toggle][HCNT_WIDTH] && sd_hcnt == hb_rise[~line_toggle][HCNT_WIDTH-1:0]) hb_sd <= 1; + if(hb_fall[~line_toggle][HCNT_WIDTH] && sd_hcnt == hb_fall[~line_toggle][HCNT_WIDTH-1:0]) hb_sd <= 0; + end + + sd_i_div <= sd_i_div + 1'd1; + if (sd_i_div==ce_divider_adj) sd_i_div <= 3'b000; + + // Framing logic on sysclk + sd_synccnt <= sd_synccnt + 1'd1; + hsD <= hs_in; + + if(sd_synccnt == hs_max || (hsD && !hs_in)) begin + sd_synccnt <= 0; + sd_hcnt <= 0; + hs_sd <= 0; + sd_i_div <= 3'b000; + end + + if(sd_synccnt == hs_rise) hs_sd <= 1; + +end + +wire ce_x4 = sd_i_div[0]; // Faster pixel_ena for higher subdivisions to prevent blending from becoming to coarse. + +assign pixel_ena = ce_divider_out > 3'd5 ? + bypass ? ce_x2 : ce_x4 : + bypass ? ce_x1 : ce_x2 ; + +endmodule \ No newline at end of file diff --git a/analogizer/scandoubler_2.v b/analogizer/scandoubler_2.v new file mode 100644 index 0000000..57bdd11 --- /dev/null +++ b/analogizer/scandoubler_2.v @@ -0,0 +1,211 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017-2021 Alexey Melnikov +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler_2 #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_vid, + input hq2x, + + // shifter video interface + input ce_pix, + input hs_in, + input vs_in, + input hb_in, + input vb_in, + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + + // output interface + output ce_pix_out, + output reg hs_out, + output vs_out, + output hb_out, + output vb_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +localparam DWIDTH = HALF_DEPTH ? 3 : 7; + +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg [7:0] pix_in_cnt = 0; +wire [7:0] pc_in = pix_in_cnt + 1'b1; +reg [7:0] pixsz, pixsz2, pixsz4 = 0; + +reg ce_x4i, ce_x1i; +always @(posedge clk_vid) begin + reg old_ce, valid, hs; + + if(~&pix_len) pix_len <= pl; + if(~&pix_in_cnt) pix_in_cnt <= pc_in; + + ce_x4i <= 0; + ce_x1i <= 0; + + // use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4. + if((pc_in == pixsz4) || (pc_in == pixsz2) || (pc_in == (pixsz2+pixsz4))) ce_x4i <= 1; + + old_ce <= ce_pix; + if(~old_ce & ce_pix) begin + if(valid & ~hb_in & ~vb_in) begin + pixsz <= pl; + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + end + pix_len <= 0; + valid <= 1; + end + + hs <= hs_in; + if((~hs & hs_in) || (pc_in >= pixsz)) begin + ce_x4i <= 1; + ce_x1i <= 1; + pix_in_cnt <= 0; + end + + if(hb_in | vb_in) valid <= 0; +end + +reg req_line_reset; +reg [DWIDTH:0] r_d, g_d, b_d; +always @(posedge clk_vid) begin + if(ce_x1i) begin + req_line_reset <= hb_in; + r_d <= r_in; + g_d <= g_in; + b_d <= b_in; + end +end + +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_vid), + + .ce_in(ce_x4i), + .inputpixel({b_d,g_d,r_d}), + .disable_hq2x(~hq2x), + .reset_frame(vb_in), + .reset_line(req_line_reset), + + .ce_out(ce_x4o), + .read_y(sd_line), + .hblank(hbo[0]&hbo[8]), + .outpixel({b_out,g_out,r_out}) +); + +reg [7:0] pix_out_cnt = 0; +wire [7:0] pc_out = pix_out_cnt + 1'b1; + +reg ce_x4o, ce_x2o; +always @(posedge clk_vid) begin + reg hs; + + if(~&pix_out_cnt) pix_out_cnt <= pc_out; + + ce_x4o <= 0; + ce_x2o <= 0; + + // use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4. + if((pc_out == pixsz4) || (pc_out == pixsz2) || (pc_out == (pixsz2+pixsz4))) ce_x4o <= 1; + if( pc_out == pixsz2) ce_x2o <= 1; + + hs <= hs_out; + if((~hs & hs_out) || (pc_out >= pixsz)) begin + ce_x2o <= 1; + ce_x4o <= 1; + pix_out_cnt <= 0; + end +end + +reg [1:0] sd_line; +reg [3:0] vbo; +reg [3:0] vso; +reg [8:0] hbo; +always @(posedge clk_vid) begin + + reg [31:0] hcnt; + reg [30:0] sd_hcnt; + reg [30:0] hs_start, hs_end; + reg [30:0] hde_start, hde_end; + + reg hs, hb; + + if(ce_x4o) begin + hbo[8:1] <= hbo[7:0]; + end + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + if(sd_hcnt == hde_start) begin + sd_hcnt <= 0; + vbo[3:1] <= vbo[2:0]; + end + + if(sd_hcnt == hs_end) begin + sd_line <= sd_line + 1'd1; + if(&vbo[3:2]) sd_line <= 1; + vso[3:1] <= vso[2:0]; + end + + if(sd_hcnt == hde_start)hbo[0] <= 0; + if(sd_hcnt == hde_end) hbo[0] <= 1; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_end) hs_out <= 0; + if(sd_hcnt == hs_start) hs_out <= 1; + + hs <= hs_in; + hb <= hb_in; + + hcnt <= hcnt + 1'd1; + if(hb && !hb_in) begin + hde_start <= hcnt[31:1]; + hbo[0] <= 0; + hcnt <= 0; + sd_hcnt <= 0; + vbo <= {vbo[2:0],vb_in}; + end + + if(!hb && hb_in) hde_end <= hcnt[31:1]; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_end <= hcnt[31:1]; + vso[0] <= vs_in; + end + + // save position of rising edge + if(!hs && hs_in) hs_start <= hcnt[31:1]; +end + +assign vs_out = vso[3]; +assign ce_pix_out = hq2x ? ce_x4o : ce_x2o; + +//Compensate picture shift after HQ2x +assign vb_out = vbo[3]; +assign hb_out = hbo[6]; + +endmodule diff --git a/analogizer/scanlines.v b/analogizer/scanlines.v new file mode 100644 index 0000000..0b8acd2 --- /dev/null +++ b/analogizer/scanlines.v @@ -0,0 +1,68 @@ +module scanlines #(parameter v2=0) +( + input clk, + + input [1:0] scanlines, + input [23:0] din, + input hs_in,vs_in, + input de_in,ce_in, + + output reg [23:0] dout, + output reg hs_out,vs_out, + output reg de_out,ce_out +); + +reg [1:0] scanline; +always @(posedge clk) begin + reg old_hs, old_vs; + + old_hs <= hs_in; + old_vs <= vs_in; + + if(old_hs && ~hs_in) begin + if(v2) begin + scanline <= scanline + 1'd1; + if (scanline == scanlines) scanline <= 0; + end + else scanline <= scanline ^ scanlines; + end + if(old_vs && ~vs_in) scanline <= 0; +end + +wire [7:0] r,g,b; +assign {r,g,b} = din; + +reg [23:0] d; +always @(*) begin + case(scanline) + 1: // reduce 25% = 1/2 + 1/4 + d = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, + {1'b0, g[7:1]} + {2'b00, g[7:2]}, + {1'b0, b[7:1]} + {2'b00, b[7:2]}}; + + 2: // reduce 50% = 1/2 + d = {{1'b0, r[7:1]}, + {1'b0, g[7:1]}, + {1'b0, b[7:1]}}; + + 3: // reduce 75% = 1/4 + d = {{2'b00, r[7:2]}, + {2'b00, g[7:2]}, + {2'b00, b[7:2]}}; + + default: d = {r,g,b}; + endcase +end + +always @(posedge clk) begin + reg [23:0] dout1, dout2; + reg de1,de2,vs1,vs2,hs1,hs2,ce1,ce2; + + dout <= dout2; dout2 <= dout1; dout1 <= d; + vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in; + hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in; + de_out <= de2; de2 <= de1; de1 <= de_in; + ce_out <= ce2; ce2 <= ce1; ce1 <= ce_in; +end + +endmodule \ No newline at end of file diff --git a/analogizer/scanlines_analogizer.v b/analogizer/scanlines_analogizer.v new file mode 100644 index 0000000..a76ee61 --- /dev/null +++ b/analogizer/scanlines_analogizer.v @@ -0,0 +1,68 @@ +module scanlines_analogizer #(parameter v2=0) +( + input clk, + + input [1:0] scanlines, + input [23:0] din, + input hs_in,vs_in, + input de_in,ce_in, + + output reg [23:0] dout, + output reg hs_out,vs_out, + output reg de_out,ce_out +); + +reg [1:0] scanline; +always @(posedge clk) begin + reg old_hs, old_vs; + + old_hs <= hs_in; + old_vs <= vs_in; + + if(old_hs && ~hs_in) begin + if(v2) begin + scanline <= scanline + 1'd1; + if (scanline == scanlines) scanline <= 0; + end + else scanline <= scanline ^ scanlines; + end + if(old_vs && ~vs_in) scanline <= 0; +end + +wire [7:0] r,g,b; +assign {r,g,b} = din; + +reg [23:0] d; +always @(*) begin + case(scanline) + 1: // reduce 25% = 1/2 + 1/4 + d = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, + {1'b0, g[7:1]} + {2'b00, g[7:2]}, + {1'b0, b[7:1]} + {2'b00, b[7:2]}}; + + 2: // reduce 50% = 1/2 + d = {{1'b0, r[7:1]}, + {1'b0, g[7:1]}, + {1'b0, b[7:1]}}; + + 3: // reduce 75% = 1/4 + d = {{2'b00, r[7:2]}, + {2'b00, g[7:2]}, + {2'b00, b[7:2]}}; + + default: d = {r,g,b}; + endcase +end + +always @(posedge clk) begin + reg [23:0] dout1, dout2; + reg de1,de2,vs1,vs2,hs1,hs2,ce1,ce2; + + dout <= dout2; dout2 <= dout1; dout1 <= d; + vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in; + hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in; + de_out <= de2; de2 <= de1; de1 <= de_in; + ce_out <= ce2; ce2 <= ce1; ce1 <= ce_in; +end + +endmodule \ No newline at end of file diff --git a/analogizer/serlatch_gc.v b/analogizer/serlatch_gc.v new file mode 100644 index 0000000..6b84da4 --- /dev/null +++ b/analogizer/serlatch_gc.v @@ -0,0 +1,367 @@ +//************************************************************** +//* Analogizer SNAC openFPGA interface for the Analogue Pocket * +//************************************************************** +// By @RndMnkIII. +// Date: 01/2024 +// Release: 1.0 + +// Aquí he documentado el funcionamiento de los diferentes mandos de juegos a los que he ido dando soporte, basado en las capturas de datos +// realizadas con analizador lógico + generador de patrones: +// +// ******** +// * DB15 * Tested up 1MHz +// ******** +// +// STB | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |32 |33 |34 |35 |36 |37 |38 |39 |40 |41 |42 |43 |44 |45 |46 |47 |48 |49 | +// ____ ___________________________________________________________________________________________________________________________________________________________________________________________ +// LATCH \_______/ +// ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ +// CLK / \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___ +// ___ ___________ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ +// DATA / \ P1 D X P1 C X P1 B X P1 A X P1 RG X P1 LF X P1 DW X P1 UP X P2 RG X P2 LF X P2 DW X P2 UP X P1 F X P1 E X P1 SELX P1 ST X P2 F X P2 E X P2 SELX P2 ST X P2 D X P2 C X P2B X P2 A +// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ +// SAMPLE | | | | | | | | | | | | | | | | | | | | | | | | +// 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +// TEST DATA 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +// TEST DATA 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +// POCKET INPUTS +// 1 P1 up X +// 0 P1 down X +// 1 P1 left X +// 0 P1 right X +// 0 P1 y X +// 1 P1 x X +// 0 P1 b X +// 1 P1 a X +// 1 P1 l1 X +// 0 P1 r1 X +// 0 P1 l2 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// 0 P1 r2 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// 0 P1 l3 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// 0 P1 r3 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// 0 P1 select X +// 1 P1 start X +// 1 P2 up X +// 0 P2 down X +// 1 P2 left X +// 0 P2 right X +// 0 P2 y X +// 1 P2 x X +// 0 P2 b X +// 1 P2 a X +// 1 P2 l1 X +// 0 P2 r1 X +// 0 P2 l2 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// 0 P2 r2 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// 0 P2 l3 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// 0 P2 r3 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +// 0 P2 select X +// 1 P2 start X +//P1 1010 0101 1000 0001 +// A 5 8 1 +//P2 1010 0101 1000 0001 +// A 5 8 1 +//gtkwave +//p1 1010 0101 1000 0001 +// A581 +//p2 1010 0101 1000 0001 +// A581 +// x +// 1111111 +// 6543210987654321 +// ******** +// * NES * Tested up 1MHz +// ******** +// STB | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |32 |33 |34 |35 | +// _______ +// LATCH ____/ \___________________________________________________________________________________________________________________________________ +// ..... ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ +// CLK ________.___.___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___ +// ____ ___________ _______ _______ _______ _______ _______ _______ _______ _______________________________________________________________________ +// DATA \ BTN A X BTN B X SELECTX START X UP X DOWN X LEFT X RIGHT / +// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ +// SAMPLE | | | | | | | | | | | | | | | | | +// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +// POCKET INPUTS +// P1 P2 +// 0 1 P1 up X +// 1 0 P1 down X +// 0 1 P1 left X +// 1 0 P1 right X +// 0 0 P1 y ------------------------------------------------------------------------------------------------------------------------------------ +// 0 0 P1 x ------------------------------------------------------------------------------------------------------------------------------------ +// 1 0 P1 b X +// 0 1 P1 a X +// 0 0 P1 l1 ------------------------------------------------------------------------------------------------------------------------------------ +// 0 0 P1 r1 ------------------------------------------------------------------------------------------------------------------------------------ +// 0 0 P1 l2 ------------------------------------------------------------------------------------------------------------------------------------ +// 0 0 P1 r2 ------------------------------------------------------------------------------------------------------------------------------------ +// 0 0 P1 l3 ---------------------------------------------------------------------------------------------------------------------------------- +// 0 0 P1 r3 ------------------------------------------------------------------------------------------------------------------------------------ +// 0 1 P1 select X +// 1 0 P1 start X +// P1 0101 0010 0000 0001 <- 0101_0101 B START DOWN RIGHT +// 5 2 0 1 +// P2 1010 0001 0000 0010 <- 1010_1010 A SELECT UP LEFT +// A 1 0 2 +// 1111111 +// 6543210987654321 +//gtkwave +// P1 5201 +// P2 A102 +// +// ******** +// * SNES * Tested up 200KHz +// ******** +// STB | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |32 |33 |34 |35 | +// _______ +// LATCH ____/ \___________________________________________________________________________________________________________________________________ +// ..... ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ +// CLK ________.___.___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___ +// __ _________ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ _______ +// DATA ___ / \ BTN_B X BTN_Y X SEL X START X UP X DOWN X LEFT X RIGHT X BTN_A X BTN_X X TG_L X TG_R X H X H X H X H \______ +// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ +// SAMPLE | | | | | | | | | | | | | | | | | +// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +// POCKET INPUTS +// 0 P1 up X +// 1 P1 down X +// 2 P1 left X +// 3 P1 right X +// 4 P1 y X +// 5 P1 x X +// 6 P1 b X +// 7 P1 a X +// 8 P1 l1 X +// 9 P1 r1 X +//10 P1 l2 ------------------------------------------------------------------------------------------------------------------------------------ +//11 P1 r2 ------------------------------------------------------------------------------------------------------------------------------------ +//12 P1 l3 ------------------------------------------------------------------------------------------------------------------------------------ +//13 P1 r3 ------------------------------------------------------------------------------------------------------------------------------------ +//14 P1 select X +//15 P1 start X +`default_nettype none + +module serlatch_game_controller #(parameter MASTER_CLK_FREQ=53_600_000) +( + input wire i_clk, + input wire i_rst, + input wire [3:0] game_controller_type, //0x0 DISABLED, 0x1 DB15, 0x2 NES, 0x3 SNES, 0x9 DB15 Fast, 0xB SNES SWAP A,B<->X,Y + input wire i_stb, + output reg [15:0] p1_btn_state, + output reg [15:0] p2_btn_state, + output reg busy, + + //SNAC Game controller interface + output wire o_clk, //for controller 1 + output wire o_clk2, //for controller 2 + output wire o_lat, //shared for 2 controllers + input wire i_dat1, //data from controller 1 + input wire i_dat2 //data from controller 2 +); + //FSM states + parameter IDLE = 3'b001; + parameter LATCH = 3'b010; + parameter DATA = 3'b100; + + //store module settings + reg [3:0] game_controller_type_r; + reg [2:0] state = IDLE; + + reg [5:0] counter; + //reg [4:0] btn_cnt; + reg [5:0] counter_top_value; + reg latch_internal; + reg clk_internal; + reg [23:0] bstat_r; + reg [15:0] p1b_r; + reg [15:0] p2b_r; + + wire latch_level ; + wire disable_clock_on_latch ; + wire sample_data ; + + //always sample data at falling edge of o_clk starting and second clock pulse in latch phase. + assign sample_data = ~counter[0] && i_stb && (counter > 1) && (counter <= counter_top_value); + + + always @(posedge i_clk) begin + //detect reset or any change on gamepad configuration and restart FSM at IDLE state. + if(i_rst || (game_controller_type != game_controller_type_r)) begin + state <= IDLE; + //clear internal register button state + p1b_r <= 16'hffff; + p2b_r <= 16'hffff; + bstat_r <= 24'hffffff; + end + + game_controller_type_r <= game_controller_type; + + if(i_stb) begin + case(state) + IDLE: + begin + //fetch data from last read + //set button status output + case(game_controller_type_r) + 4'h0: begin //DISABLED + p1_btn_state = 16'd0; + p2_btn_state = 16'd0; + end + 4'h1,4'h9: begin //DB15, DB15 FAST + // Pocket logic button order: + // [0] dpad_up + // [1] dpad_down + // [2] dpad_left + // [3] dpad_right + // [4] face_a + // [5] face_b + // [6] face_x + // [7] face_y + // [8] trig_l1 + // [9] trig_r1 + // [10] trig_l2 + // [11] trig_r2 + // [12] trig_l3 + // [13] trig_r3 + // [14] face_select + // [15] face_start + + //SNAC DB15 adapter button order from first to last + // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + //P1D,P1C,P1B,P1A,P1R,P1L,P1D,P1U,P2R,P2L,P2D,P2U,P1F,P1E,P1SEL,P1ST,P2F,P2E,P2SEL,P2ST,P2D,P2C,P2B,P2A + //follow Pocket game controls order: + //PLAYER1 START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP + p1_btn_state <= ~{bstat_r[15], bstat_r[14], 4'b1111, bstat_r[12], bstat_r[13], bstat_r[0], bstat_r[1], bstat_r[2], bstat_r[3], bstat_r[4], bstat_r[5], bstat_r[6], bstat_r[7]}; + + //PLAYER2 START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP + p2_btn_state <= ~{bstat_r[19], bstat_r[18], 4'b1111, bstat_r[16], bstat_r[17], bstat_r[20], bstat_r[21], bstat_r[22], bstat_r[23], bstat_r[8], bstat_r[9], bstat_r[10], bstat_r[11]}; + end + 4'h2: begin //NES + //SNAC NES adapter button order from first to last + // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + // A B SEL ST UP DW LF RG H H H H H H H H + + //follow Pocket game controls order: + // START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGHT LEFT DOWN UP + p1_btn_state <= ~{p1b_r[3],p1b_r[2], 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, p1b_r[1], p1b_r[0],p1b_r[7],p1b_r[6],p1b_r[5],p1b_r[4]}; + p2_btn_state <= ~{p2b_r[3],p2b_r[2], 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, p2b_r[1], p2b_r[0],p2b_r[7],p2b_r[6],p2b_r[5],p2b_r[4]}; + end + 4'h3: begin //SNES + //SNAC SNES adapter button order from first to last + // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + // B Y SEL ST UP DW LF RG A X LT LR H H H H + + //follow Pocket game controls order: + // START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGHT LEFT DOWN UP + p1_btn_state <= ~{p1b_r[3],p1b_r[2],1'b1, 1'b1, 1'b1, 1'b1, p1b_r[11], p1b_r[10], p1b_r[1], p1b_r[9], p1b_r[0], p1b_r[8],p1b_r[7],p1b_r[6], p1b_r[5],p1b_r[4]}; + p2_btn_state <= ~{p2b_r[3],p2b_r[2],1'b1, 1'b1, 1'b1, 1'b1, p2b_r[11], p2b_r[10], p2b_r[1], p2b_r[9], p2b_r[0], p2b_r[8],p2b_r[7],p2b_r[6], p2b_r[5],p2b_r[4]}; + + end + 4'hB: begin //SNES SWAP A,B <-> X,Y + //SNAC SNES adapter button order from first to last + // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + // B Y SEL ST UP DW LF RG A X LT LR H H H H + + //follow Pocket game controls order: + // START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGHT LEFT DOWN UP + p1_btn_state <= ~{p1b_r[3],p1b_r[2],1'b1, 1'b1, 1'b1, 1'b1, p1b_r[11], p1b_r[10], p1b_r[0], p1b_r[8], p1b_r[1], p1b_r[9],p1b_r[7],p1b_r[6], p1b_r[5],p1b_r[4]}; + p2_btn_state <= ~{p2b_r[3],p2b_r[2],1'b1, 1'b1, 1'b1, 1'b1, p2b_r[11], p2b_r[10], p2b_r[0], p2b_r[8], p2b_r[1], p2b_r[9],p2b_r[7],p2b_r[6], p2b_r[5],p2b_r[4]}; + + end + default: + begin //disabled + p1_btn_state <= 16'd0; + p2_btn_state <= 16'd0; + end + endcase + + //init counter and set initial LAT,CLK values on IDLE state + counter <= 6'd0; + + counter_top_value <= 6'd0; + if ((game_controller_type_r == 4'h1) || (game_controller_type_r == 4'h9)) counter_top_value <= 6'd48; + else if((game_controller_type_r == 4'h2) || (game_controller_type_r == 4'h3) || (game_controller_type_r == 4'hB)) counter_top_value <= 6'd34; + + latch_internal <= latch_level; + clk_internal <= disable_clock_on_latch ? 1'b0 : 1'b1; + state <= LATCH; + busy <= 1'b1; + p1b_r <= 16'hffff; + p2b_r <= 16'hffff; + bstat_r <= 24'hffffff; + end + LATCH: + begin + counter <= counter + 6'd1; + latch_internal <= ~latch_level; + clk_internal <= disable_clock_on_latch ? 1'b0 : ~clk_internal; + + //first sample of data is available in LATCH phase. + if(sample_data) begin//read button state + if((game_controller_type_r == 4'h1) || (game_controller_type_r == 4'h9)) begin //if is selected DB15,DB15 FAST all button state is store in one 24bit register + bstat_r[0] <= i_dat1; //3->0, 5->1, 7->2, 9->3, ... + // $display("DB15 [LATCH] BTN_CNT:%d i_dat1:%d", btn_cnt, i_dat1); + end + else begin + p1b_r[0] <= i_dat1; + p2b_r[0] <= i_dat2; + end + end + + if(counter == 6'd2) begin + state <= DATA; + latch_internal <= latch_level; + end + end + DATA: + begin + counter <= counter + 6'd1; //should be start clocking at 3 + clk_internal <= ~clk_internal; + //following data samples are get in DATA phase. + if(sample_data) begin//read button state + if((game_controller_type_r == 4'h1) || (game_controller_type_r == 4'h9) ) begin //if is selected DB15,DB15 FAST all button state is store in one 24bit register + bstat_r[((counter>>1)-1)] <= i_dat1; //3->0, 5->1, 7->2, 9->3, ... + //$display("DB15 [DATA] BTN_CNT:%d i_dat1:%d r_dat[%d]:%d", btn_cnt, i_dat1, btn_cnt,bstat_r[btn_cnt]); + end + else if((game_controller_type_r == 4'h2) || (game_controller_type_r == 4'h3) || (game_controller_type_r == 4'hB)) begin + p1b_r[((counter>>1)-1)] <= i_dat1; + p2b_r[((counter>>1)-1)] <= i_dat2; + end + end + + //the gamepads buton state are fetched at the end of DATA phase + if(counter == counter_top_value) begin + state <= IDLE; + busy <= 1'b0; + end + end + endcase + end + end + + //the DB15 SNAC interface uses active LOW latch signal, NES,SNES use active HIGH latch: + // ----- ------ ... + //DB15 LATCH |___| + // + // ___ + //NES,SNES LATCH _____| |_____ ... + + assign latch_level = ((game_controller_type_r == 4'h1) || (game_controller_type_r == 4'h9)) ? 1'b1 : 1'b0; //DB15, DB15 FAST + + //the NES,SNES SNAC interfaces disable clock signal while are in LATCH phase + //but internally the falling edge CLK is used for sample the button state + // ___ + //LATCH ______| |_________ ... + // _ _ _ + //o_clk | |_________| |_| |_ ... + // _ _ _ _ _ + //CLK | |_|X|_|X|_| |_| |_ ... + // ... 1 2 3 4 5 6 7 8 ... + assign disable_clock_on_latch = ((game_controller_type_r != 4'h1) && (game_controller_type_r != 4'h9)) ? 1'b1 : 1'b0; //en caso de que sea controlador NES,SNES + + //counter values: 36 for NES,SNES, 50 for DB15 + assign o_clk = (game_controller_type_r == 4'h0) ? 1'b0 : clk_internal; + assign o_clk2 = (game_controller_type_r == 4'h0) ? 1'b0 : clk_internal; + assign o_lat = (game_controller_type_r == 4'h0) ? 1'b0 : latch_internal; +endmodule \ No newline at end of file diff --git a/analogizer/sine_lut.mem b/analogizer/sine_lut.mem new file mode 100644 index 0000000..9d6aaa1 --- /dev/null +++ b/analogizer/sine_lut.mem @@ -0,0 +1,256 @@ +000 +006 +00C +012 +018 +01F +025 +02B +031 +037 +03D +044 +04A +04F +055 +05B +061 +067 +06D +072 +078 +07D +083 +088 +08D +092 +097 +09C +0A1 +0A6 +0AB +0AF +0B4 +0B8 +0BC +0C1 +0C5 +0C9 +0CC +0D0 +0D4 +0D7 +0DA +0DD +0E0 +0E3 +0E6 +0E9 +0EB +0ED +0F0 +0F2 +0F4 +0F5 +0F7 +0F8 +0FA +0FB +0FC +0FD +0FD +0FE +0FE +0FE +0FF +0FE +0FE +0FE +0FD +0FD +0FC +0FB +0FA +0F8 +0F7 +0F5 +0F4 +0F2 +0F0 +0ED +0EB +0E9 +0E6 +0E3 +0E0 +0DD +0DA +0D7 +0D4 +0D0 +0CC +0C9 +0C5 +0C1 +0BC +0B8 +0B4 +0AF +0AB +0A6 +0A1 +09C +097 +092 +08D +088 +083 +07D +078 +072 +06D +067 +061 +05B +055 +04F +04A +044 +03D +037 +031 +02B +025 +01F +018 +012 +00C +006 +000 +7F9 +7F3 +7ED +7E7 +7E0 +7DA +7D4 +7CE +7C8 +7C2 +7BB +7B5 +7B0 +7AA +7A4 +79E +798 +792 +78D +787 +782 +77C +777 +772 +76D +768 +763 +75E +759 +754 +750 +74B +747 +743 +73E +73A +736 +733 +72F +72B +728 +725 +722 +71F +71C +719 +716 +714 +712 +70F +70D +70B +70A +708 +707 +705 +704 +703 +702 +702 +701 +701 +701 +701 +701 +701 +701 +702 +702 +703 +704 +705 +707 +708 +70A +70B +70D +70F +712 +714 +716 +719 +71C +71F +722 +725 +728 +72B +72F +733 +736 +73A +73E +743 +747 +74B +750 +754 +759 +75E +763 +768 +76D +772 +777 +77C +782 +787 +78D +792 +798 +79E +7A4 +7AA +7B0 +7B5 +7BB +7C2 +7C8 +7CE +7D4 +7DA +7E0 +7E7 +7ED +7F3 +7F9 \ No newline at end of file diff --git a/analogizer/sync_fix.v b/analogizer/sync_fix.v new file mode 100644 index 0000000..014dd72 --- /dev/null +++ b/analogizer/sync_fix.v @@ -0,0 +1,28 @@ +module sync_fix +( + input clk, + + input sync_in, + output sync_out +); + +assign sync_out = sync_in ^ pol; + +reg pol; +always @(posedge clk) begin + integer pos = 0, neg = 0, cnt = 0; + reg s1,s2; + + s1 <= sync_in; + s2 <= s1; + + if(~s2 & s1) neg <= cnt; + if(s2 & ~s1) pos <= cnt; + + cnt <= cnt + 1; + if(s2 != s1) cnt <= 0; + + pol <= pos > neg; +end + +endmodule \ No newline at end of file diff --git a/analogizer/two_button_press_detector.v b/analogizer/two_button_press_detector.v new file mode 100644 index 0000000..c0c061b --- /dev/null +++ b/analogizer/two_button_press_detector.v @@ -0,0 +1,53 @@ +//Module to detect when two buttons are pressed for 2 seconds +module two_button_press_detector( + input wire clk, // System clock at 28.375160 MHz + input wire reset, // Reset signal + input wire button1, // First button input + input wire button2, // Second button input + output reg detection_done // Output signal when both buttons are pressed for 2 seconds +); + + parameter COUNT_MAX = 56750320; // Number of clock cycles for 2 seconds + reg [31:0] counter; // Counter for 2 seconds + + // State machine states + localparam IDLE = 0, + COUNTING = 1; + reg state; + + always @(posedge clk or posedge reset) begin + if (reset) begin + counter <= 0; + detection_done <= 0; + state <= IDLE; + end else begin + case (state) + IDLE: begin + if (button1 && button2) begin + counter <= 0; + state <= COUNTING; + end else begin + detection_done <= 0; + counter <= 0; + end + end + COUNTING: begin + if (button1 && button2) begin + if (counter < COUNT_MAX - 1) begin + counter <= counter + 1; + detection_done <= 0; + end else begin + detection_done <= 1; + state <= IDLE; // Reset back to IDLE after detection + end + end else begin + detection_done <= 0; + state <= IDLE; + counter <= 0; // Reset counter if buttons are released before 2 seconds + end + end + endcase + end + end + +endmodule \ No newline at end of file diff --git a/analogizer/uart_tx.v b/analogizer/uart_tx.v new file mode 100644 index 0000000..304c88a --- /dev/null +++ b/analogizer/uart_tx.v @@ -0,0 +1,147 @@ +////////////////////////////////////////////////////////////////////// +// File Downloaded from http://www.nandland.com +////////////////////////////////////////////////////////////////////// +// This file contains the UART Transmitter. This transmitter is able +// to transmit 8 bits of serial data, one start bit, one stop bit, +// and no parity bit. When transmit is complete o_Tx_done will be +// driven high for one clock cycle. +// +// Set Parameter CLKS_PER_BIT as follows: +// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART) +// Example: 10 MHz Clock, 115200 baud UART +// (10000000)/(115200) = 87 + + //48_000_000 /500_000 = 96 +module uart_tx + #(parameter CLKS_PER_BIT) + ( + input i_Clock, + input i_Tx_DV, + input [7:0] i_Tx_Byte, + output o_Tx_Active, + output reg o_Tx_Serial, + output o_Tx_Done + ); + + parameter s_IDLE = 3'b000; + parameter s_TX_START_BIT = 3'b001; + parameter s_TX_DATA_BITS = 3'b010; + parameter s_TX_STOP_BIT = 3'b011; + parameter s_CLEANUP = 3'b100; + + reg [2:0] r_SM_Main = 0; + reg [7:0] r_Clock_Count = 0; + reg [2:0] r_Bit_Index = 0; + reg [7:0] r_Tx_Data = 0; + reg r_Tx_Done = 0; + reg r_Tx_Active = 0; + + always @(posedge i_Clock) + begin + + case (r_SM_Main) + s_IDLE : + begin + o_Tx_Serial <= 1'b1; // Drive Line High for Idle + r_Tx_Done <= 1'b0; + r_Clock_Count <= 0; + r_Bit_Index <= 0; + + if (i_Tx_DV == 1'b1) + begin + r_Tx_Active <= 1'b1; + r_Tx_Data <= i_Tx_Byte; + r_SM_Main <= s_TX_START_BIT; + end + else + r_SM_Main <= s_IDLE; + end // case: s_IDLE + + + // Send out Start Bit. Start bit = 0 + s_TX_START_BIT : + begin + o_Tx_Serial <= 1'b0; + + // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish + if (r_Clock_Count < CLKS_PER_BIT-1) + begin + r_Clock_Count <= r_Clock_Count + 1; + r_SM_Main <= s_TX_START_BIT; + end + else + begin + r_Clock_Count <= 0; + r_SM_Main <= s_TX_DATA_BITS; + end + end // case: s_TX_START_BIT + + + // Wait CLKS_PER_BIT-1 clock cycles for data bits to finish + s_TX_DATA_BITS : + begin + o_Tx_Serial <= r_Tx_Data[r_Bit_Index]; + + if (r_Clock_Count < CLKS_PER_BIT-1) + begin + r_Clock_Count <= r_Clock_Count + 1; + r_SM_Main <= s_TX_DATA_BITS; + end + else + begin + r_Clock_Count <= 0; + + // Check if we have sent out all bits + if (r_Bit_Index < 7) + begin + r_Bit_Index <= r_Bit_Index + 1; + r_SM_Main <= s_TX_DATA_BITS; + end + else + begin + r_Bit_Index <= 0; + r_SM_Main <= s_TX_STOP_BIT; + end + end + end // case: s_TX_DATA_BITS + + + // Send out Stop bit. Stop bit = 1 + s_TX_STOP_BIT : + begin + o_Tx_Serial <= 1'b1; + + // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish + if (r_Clock_Count < CLKS_PER_BIT-1) + begin + r_Clock_Count <= r_Clock_Count + 1; + r_SM_Main <= s_TX_STOP_BIT; + end + else + begin + r_Tx_Done <= 1'b1; + r_Clock_Count <= 0; + r_SM_Main <= s_CLEANUP; + r_Tx_Active <= 1'b0; + end + end // case: s_Tx_STOP_BIT + + + // Stay here 1 clock + s_CLEANUP : + begin + r_Tx_Done <= 1'b1; + r_SM_Main <= s_IDLE; + end + + + default : + r_SM_Main <= s_IDLE; + + endcase + end + + assign o_Tx_Active = r_Tx_Active; + assign o_Tx_Done = r_Tx_Done; + +endmodule \ No newline at end of file diff --git a/analogizer/vga_out_sw.v b/analogizer/vga_out_sw.v new file mode 100644 index 0000000..612bfe2 --- /dev/null +++ b/analogizer/vga_out_sw.v @@ -0,0 +1,72 @@ +module vga_out +( + input wire clk, + input wire ypbpr_en, + + input wire hsync, + input wire vsync, + input wire csync, + input wire de, + + input wire [17:0] din, + output wire [17:0] dout, + + output reg hsync_o, + output reg vsync_o, + output reg csync_o, + output reg de_o +); + +wire [7:0] red = {din[17:12],2'b00}; +wire [7:0] green = {din[11:6],2'b00}; +wire [7:0] blue = {din[5:0],2'b00}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html + + +// Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +reg [7:0] y, pb, pr; +reg [17:0] rgb; +always @(posedge clk) begin + reg [18:0] y_1r, pb_1r, pr_1r; + reg [18:0] y_1g, pb_1g, pr_1g; + reg [18:0] y_1b, pb_1b, pr_1b; + reg [18:0] y_2, pb_2, pr_2; + reg [17:0] din1, din2; + reg hsync2, vsync2, csync2, de2; + reg hsync1, vsync1, csync1, de1; + + y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red; + pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0}); + pr_1r <= 19'd32768 + {red, 7'd0}; + + y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0}; + pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green; + pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0}; + + y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue; + pb_1b <= {blue, 7'd0}; + pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue; + + y_2 <= y_1r + y_1g + y_1b; + pb_2 <= pb_1r - pb_1g + pb_1b; + pr_2 <= pr_1r - pr_1g - pr_1b; + + y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8]; + pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8]; + pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8]; + + hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync; + vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync; + csync_o <= csync2; csync2 <= csync1; csync1 <= csync; + de_o <= de2; de2 <= de1; de1 <= de; + + rgb <= din2; din2 <= din1; din1 <= din; +end + +assign dout = ypbpr_en ? {pr[7:2], y[7:2], pb[7:2]} : rgb; //reduced to 6bits per component + +endmodule \ No newline at end of file diff --git a/analogizer/yc_out.sv b/analogizer/yc_out.sv new file mode 100644 index 0000000..960bd3b --- /dev/null +++ b/analogizer/yc_out.sv @@ -0,0 +1,275 @@ +//============================================================================ +// YC - Luma / Chroma Generation +// Copyright (C) 2022 Mike Simone +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ +/* +Colorspace +Y 0.299R' + 0.587G' + 0.114B' +U 0.492(B' - Y) = 504 (X 1024) +V 0.877(R' - Y) = 898 (X 1024) +*/ +////////////////////////////////////////////////////////// + +module yc_out +( + input clk, + input [39:0] PHASE_INC, + input PAL_EN, + + input hsync, + input vsync, + input csync, + + input [17:0] din, + output [15:0] dout, + + output reg hsync_o, + output reg vsync_o, + output reg csync_o +); + +wire [7:0] red = {din[17:12],2'b00}; +wire [7:0] green = {din[11:6],2'b00}; +wire [7:0] blue = {din[5:0],2'b00}; + +logic [9:0] red_1, blue_1, green_1, red_2, blue_2, green_2; + +logic signed [20:0] yr = 0, yb = 0, yg = 0; + +typedef struct { + logic signed [20:0] y; + logic signed [20:0] c; + logic signed [20:0] u; + logic signed [20:0] v; + logic hsync; + logic vsync; + logic csync; +} phase_t; + +localparam MAX_PHASES = 7'd8; + +phase_t phase[MAX_PHASES]; +reg unsigned [7:0] c, U, V; +reg unsigned [7:0] Y, C; + +reg [10:0] cburst_phase, cburst_length, cburst_start; // colorburst counter +reg unsigned [7:0] vref = 'd128; // Voltage reference point (Used for Chroma) +logic [7:0] chroma_LUT_COS; // Chroma cos LUT reference +logic [7:0] chroma_LUT_SIN; // Chroma sin LUT reference +logic [7:0] chroma_LUT_BURST; // Chroma colorburst LUT reference +logic [7:0] chroma_LUT = 8'd0; + +/* +THe following LUT table was calculated by Sin(2*pi*t/2^8) where t: 0 - 255 +*/ + +/************************************* + 8 bit Sine look up Table +**************************************/ +wire signed [10:0] chroma_SIN_LUT[256] = '{ +11'h000, 11'h006, 11'h00C, 11'h012, 11'h018, 11'h01F, 11'h025, 11'h02B, 11'h031, 11'h037, 11'h03D, 11'h044, 11'h04A, 11'h04F, +11'h055, 11'h05B, 11'h061, 11'h067, 11'h06D, 11'h072, 11'h078, 11'h07D, 11'h083, 11'h088, 11'h08D, 11'h092, 11'h097, 11'h09C, +11'h0A1, 11'h0A6, 11'h0AB, 11'h0AF, 11'h0B4, 11'h0B8, 11'h0BC, 11'h0C1, 11'h0C5, 11'h0C9, 11'h0CC, 11'h0D0, 11'h0D4, 11'h0D7, +11'h0DA, 11'h0DD, 11'h0E0, 11'h0E3, 11'h0E6, 11'h0E9, 11'h0EB, 11'h0ED, 11'h0F0, 11'h0F2, 11'h0F4, 11'h0F5, 11'h0F7, 11'h0F8, +11'h0FA, 11'h0FB, 11'h0FC, 11'h0FD, 11'h0FD, 11'h0FE, 11'h0FE, 11'h0FE, 11'h0FF, 11'h0FE, 11'h0FE, 11'h0FE, 11'h0FD, 11'h0FD, +11'h0FC, 11'h0FB, 11'h0FA, 11'h0F8, 11'h0F7, 11'h0F5, 11'h0F4, 11'h0F2, 11'h0F0, 11'h0ED, 11'h0EB, 11'h0E9, 11'h0E6, 11'h0E3, +11'h0E0, 11'h0DD, 11'h0DA, 11'h0D7, 11'h0D4, 11'h0D0, 11'h0CC, 11'h0C9, 11'h0C5, 11'h0C1, 11'h0BC, 11'h0B8, 11'h0B4, 11'h0AF, +11'h0AB, 11'h0A6, 11'h0A1, 11'h09C, 11'h097, 11'h092, 11'h08D, 11'h088, 11'h083, 11'h07D, 11'h078, 11'h072, 11'h06D, 11'h067, +11'h061, 11'h05B, 11'h055, 11'h04F, 11'h04A, 11'h044, 11'h03D, 11'h037, 11'h031, 11'h02B, 11'h025, 11'h01F, 11'h018, 11'h012, +11'h00C, 11'h006, 11'h000, 11'h7F9, 11'h7F3, 11'h7ED, 11'h7E7, 11'h7E0, 11'h7DA, 11'h7D4, 11'h7CE, 11'h7C8, 11'h7C2, 11'h7BB, +11'h7B5, 11'h7B0, 11'h7AA, 11'h7A4, 11'h79E, 11'h798, 11'h792, 11'h78D, 11'h787, 11'h782, 11'h77C, 11'h777, 11'h772, 11'h76D, +11'h768, 11'h763, 11'h75E, 11'h759, 11'h754, 11'h750, 11'h74B, 11'h747, 11'h743, 11'h73E, 11'h73A, 11'h736, 11'h733, 11'h72F, +11'h72B, 11'h728, 11'h725, 11'h722, 11'h71F, 11'h71C, 11'h719, 11'h716, 11'h714, 11'h712, 11'h70F, 11'h70D, 11'h70B, 11'h70A, +11'h708, 11'h707, 11'h705, 11'h704, 11'h703, 11'h702, 11'h702, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, +11'h702, 11'h702, 11'h703, 11'h704, 11'h705, 11'h707, 11'h708, 11'h70A, 11'h70B, 11'h70D, 11'h70F, 11'h712, 11'h714, 11'h716, +11'h719, 11'h71C, 11'h71F, 11'h722, 11'h725, 11'h728, 11'h72B, 11'h72F, 11'h733, 11'h736, 11'h73A, 11'h73E, 11'h743, 11'h747, +11'h74B, 11'h750, 11'h754, 11'h759, 11'h75E, 11'h763, 11'h768, 11'h76D, 11'h772, 11'h777, 11'h77C, 11'h782, 11'h787, 11'h78D, +11'h792, 11'h798, 11'h79E, 11'h7A4, 11'h7AA, 11'h7B0, 11'h7B5, 11'h7BB, 11'h7C2, 11'h7C8, 11'h7CE, 11'h7D4, 11'h7DA, 11'h7E0, +11'h7E7, 11'h7ED, 11'h7F3, 11'h7F9 +}; + +// reg signed [10:0] chroma_SIN_LUT[0:255] /* synthesis ramstyle = "M10K" */; +// initial begin +// $readmemh("sine_lut.mem", chroma_SIN_LUT); +// end + +// reg signed [10:0] chroma_SIN_LUT2[0:255] /* synthesis ramstyle = "M10K" */; +// initial begin +// $readmemh("sine_lut.mem", chroma_SIN_LUT2); +// end + +logic [39:0] phase_accum; +logic PAL_FLIP = 1'd0; +logic PAL_line_count = 1'd0; + +/************************************** + Generate Luma and Chroma Signals +***************************************/ + +always_ff @(posedge clk) begin + for (logic [3:0] x = 0; x < (MAX_PHASES - 1'd1); x = x + 1'd1) begin + phase[x + 1] <= phase[x]; + end + + // Color Averaging to help with color accuracy + red_1 <= red; + blue_1 <= blue; + red_2 <= red_1; + blue_2 <= blue_1; + + // Calculate Luma signal + + yr <= {red, 8'd0} + {red, 5'd0}+ {red, 4'd0} + {red, 1'd0}; + yg <= {green, 9'd0} + {green, 6'd0} + {green, 4'd0} + {green, 3'd0} + green; + yb <= {blue, 6'd0} + {blue, 5'd0} + {blue, 4'd0} + {blue, 2'd0} + blue; + phase[0].y <= yr + yg + yb; + + // Generate the LUT values using the phase accumulator reference. + phase_accum <= phase_accum + PHASE_INC; + chroma_LUT <= phase_accum[39:32]; + + // Adjust SINE carrier reference for PAL (Also adjust for PAL Switch) + if (PAL_EN) begin + if (PAL_FLIP) + chroma_LUT_BURST <= chroma_LUT + 8'd160; + else + chroma_LUT_BURST <= chroma_LUT + 8'd96; + end else // Adjust SINE carrier reference for NTSC + chroma_LUT_BURST <= chroma_LUT + 8'd128; + + // Prepare LUT values for sin / cos (+90 degress) + chroma_LUT_SIN <= chroma_LUT; + chroma_LUT_COS <= chroma_LUT + 8'd64; + + // Calculate for U, V - Bit Shift Multiple by u = by * 1024 x 0.492 = 504, v = ry * 1024 x 0.877 = 898 + phase[0].u <= $signed({2'b0 ,(blue_2)}) - $signed({2'b0 ,phase[0].y[17:10]}); + phase[0].v <= $signed({2'b0 ,(red_2)}) - $signed({2'b0 ,phase[0].y[17:10]}); + phase[1].u <= $signed({phase[0].u, 8'd0}) + $signed({phase[0].u, 7'd0}) + $signed({phase[0].u, 6'd0}) + $signed({phase[0].u, 5'd0}) + $signed({phase[0].u, 4'd0}) + $signed({phase[0].u, 3'd0}) ; + phase[1].v <= $signed({phase[0].v, 9'd0}) + $signed({phase[0].v, 8'd0}) + $signed({phase[0].v, 7'd0}) + $signed({phase[0].v, 1'd0}); + + phase[0].c <= vref; + phase[1].c <= phase[0].c; + phase[2].c <= phase[1].c; + phase[3].c <= phase[2].c; + + // Set Colorburst Length Based on Phase_Accum + // Since the colorburst length depends on the video clock freqency, this just sets the approprate count length to match the colorburst lengths closer to 9/10 cycles for NTSC/PAL. + + if (PHASE_INC[39:32] > (PAL_EN ? 8'd56 : 8'd45)) begin + cburst_length <= PAL_EN ? 10'd85 : 10'd90; + cburst_start <= 10'd40; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd37 : 8'd30)) begin + cburst_length <= PAL_EN ? 10'd108 : 10'd115; + cburst_start <= 10'd40; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd28 : 8'd22)) begin + cburst_length <= PAL_EN ? 10'd130 : 10'd141; + cburst_start <= 10'd40; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd18 : 8'd15)) begin + cburst_length <= PAL_EN ? 10'd173 : 10'd186; + cburst_start <= 10'd60; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd16 : 8'd13)) begin + cburst_length <= PAL_EN ? 10'd195 : 10'd211; + cburst_start <= 10'd60; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd14 : 8'd11)) begin + cburst_length <= PAL_EN ? 10'd258 : 10'd276; + cburst_start <= 10'd100; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd12 : 8'd10)) begin + cburst_length <= PAL_EN ? 10'd281 : 10'd301; + cburst_start <= 10'd100; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd11 : 8'd9)) begin + cburst_length <= PAL_EN ? 10'd323 : 10'd346; + cburst_start <= 10'd120; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd10 : 8'd8)) begin + cburst_length <= PAL_EN ? 10'd346 : 10'd371; + cburst_start <= 10'd120; + end else if (PHASE_INC[39:32] > (PAL_EN ? 8'd9 : 8'd7)) begin + cburst_length <= PAL_EN ? 10'd368 : 10'd397; + cburst_start <= 10'd120; + end else begin + cburst_length <= PAL_EN ? 10'd391 : 10'd422; + cburst_start <= 10'd120; + end + + if (hsync) begin // Reset colorburst counter, as well as the calculated cos / sin values. + cburst_phase <= 'd0; + phase[2].u <= 21'b0; + phase[2].v <= 21'b0; + phase[4].c <= phase[3].c; + + if (PAL_line_count) begin + PAL_FLIP <= ~PAL_FLIP; + PAL_line_count <= ~PAL_line_count; + end + end else begin // Generate Colorburst for 9 cycles + if (cburst_phase >= cburst_start && cburst_phase <= cburst_length) begin // Start the color burst signal at 40 samples or 0.9 us + // COLORBURST SIGNAL GENERATION (9 CYCLES ONLY or between count 40 - 240) + phase[2].u <= $signed({chroma_SIN_LUT[chroma_LUT_BURST],5'd0}); + phase[2].v <= 21'b0; + + // Division to scale down the results to fit 8 bit. + if (PAL_EN) + phase[3].u <= $signed(phase[2].u[20:8]) + $signed(phase[2].u[20:10]) + $signed(phase[2].u[20:14]); + else + phase[3].u <= $signed(phase[2].u[20:8]) + $signed(phase[2].u[20:11]) + $signed(phase[2].u[20:12]) + $signed(phase[2].u[20:13]); + + phase[3].v <= phase[2].v; + end else if (cburst_phase > cburst_length) begin // MODULATE U, V for chroma + /* + U,V are both multiplied by 1024 earlier to scale for the decimals in the YUV colorspace conversion. + U and V are both divided by 2^10 which introduce chroma subsampling of 4:1:1 (25% or from 8 bit to 6 bit) + */ + phase[2].u <= $signed((phase[1].u)>>>10) * $signed(chroma_SIN_LUT[chroma_LUT_SIN]); + phase[2].v <= $signed((phase[1].v)>>>10) * $signed(chroma_SIN_LUT[chroma_LUT_COS]); + + // Divide U*sin(wt) and V*cos(wt) to fit results to 8 bit + phase[3].u <= $signed(phase[2].u[20:9]) + $signed(phase[2].u[20:10]) + $signed(phase[2].u[20:14]); + phase[3].v <= $signed(phase[2].v[20:9]) + $signed(phase[2].v[20:10]) + $signed(phase[2].u[20:14]); + end + + // Stop the colorburst timer as its only needed for the initial pulse + if (cburst_phase <= 'd400) + cburst_phase <= cburst_phase + 9'd1; + + // Calculate for chroma (Note: "PAL SWITCH" routine flips V * COS(Wt) every other line) + if (PAL_EN) begin + if (PAL_FLIP) + phase[4].c <= vref + phase[3].u - phase[3].v; + else + phase[4].c <= vref + phase[3].u + phase[3].v; + PAL_line_count <= 1'd1; + end else + phase[4].c <= vref + phase[3].u + phase[3].v; + + end + // Adjust sync timing correctly + phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; + phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; + phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; + phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; + hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; + phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y; + + // Set Chroma / Luma output + //reduce to 6 bits + C <= phase[4].c[7:0]; + Y <= phase[5].y[17:10]; +end + +assign dout = {C, Y}; + +endmodule diff --git a/build.ps1 b/build.ps1 new file mode 100644 index 0000000..1ed080a --- /dev/null +++ b/build.ps1 @@ -0,0 +1,30 @@ +if (($args.count -ne 1) -or ($args[0] -eq "")) { + Write-Output "Expected build type arg" + exit 1 +} + +$build_type = $args[0] + +# Tested with Quartus 21.1 +quartus_sh -t generate.tcl $build_type + +$exitcode = $LASTEXITCODE +if ($exitcode -ne 0) { + Write-Output "Build failed with $exitcode" + exit $exitcode +} + +$output_file = "NTSC_SET1.rev" + +if (($build_type -eq "NTSC_SET1")) { + $output_file = "NTSC_SET1.rev" +} elseif (($build_type -eq "NTSC_SET2")) { + $output_file = "NTSC_SET2.rev" +} elseif (($build_type -eq "PAL_SET1")) { + $output_file = "PAL_SET1.rev" +}elseif (($build_type -eq "PAL_SET2")) { + $output_file = "PAL_SET2.rev" +} + +.\tools\reverse_bits.exe .\projects\output_files\nes_pocket.rbf ".\core_bitstreams\$output_file"; + diff --git a/core_bitstreams/NTSC_SET1.rev b/core_bitstreams/NTSC_SET1.rev new file mode 100644 index 0000000..e9c023d Binary files /dev/null and b/core_bitstreams/NTSC_SET1.rev differ diff --git a/core_bitstreams/NTSC_SET2.rev b/core_bitstreams/NTSC_SET2.rev new file mode 100644 index 0000000..0dfd254 Binary files /dev/null and b/core_bitstreams/NTSC_SET2.rev differ diff --git a/core_bitstreams/PAL_SET1.rev b/core_bitstreams/PAL_SET1.rev new file mode 100644 index 0000000..417006d Binary files /dev/null and b/core_bitstreams/PAL_SET1.rev differ diff --git a/core_bitstreams/PAL_SET2.rev b/core_bitstreams/PAL_SET2.rev new file mode 100644 index 0000000..280702a Binary files /dev/null and b/core_bitstreams/PAL_SET2.rev differ diff --git a/generate.tcl b/generate.tcl new file mode 100644 index 0000000..54fd5c4 --- /dev/null +++ b/generate.tcl @@ -0,0 +1,51 @@ +# Run with quartus_sh -t generate.tcl + +# Load Quartus II Tcl Project package +package require ::quartus::project + +# Required for compilation +package require ::quartus::flow + +if { $argc != 1 } { + puts "Exactly 1 argument required" + exit +} + +project_open projects/nes_pocket.qpf + +if { [lindex $argv 0] == "NTSC_SET1" } { + puts "NTSC_SET1" + set_parameter -name USE_PAL_PLL -entity core_top '0 + set_parameter -name USE_MMAPPER_SET1 -entity cart_top '1 + set_parameter -name USE_MMAPPER_SET2 -entity cart_top '0 + set_parameter -name USE_PAL_PLL -entity nes_pll_01 '0 +} elseif { [lindex $argv 0] == "NTSC_SET2" } { + puts "NTSC_SET2" + set_parameter -name USE_PAL_PLL -entity core_top '0 + set_parameter -name USE_MMAPPER_SET1 -entity cart_top '0 + set_parameter -name USE_MMAPPER_SET2 -entity cart_top '1 + set_parameter -name USE_PAL_PLL -entity nes_pll_01 '0 +} elseif { [lindex $argv 0] == "PAL_SET1" } { + puts "PAL_SET1" + set_parameter -name USE_PAL_PLL -entity core_top '1 + set_parameter -name USE_MMAPPER_SET1 -entity cart_top '1 + set_parameter -name USE_MMAPPER_SET2 -entity cart_top '0 + set_parameter -name USE_PAL_PLL -entity nes_pll_01 '1 +} elseif { [lindex $argv 0] == "PAL_SET2" } { + puts "PAL_SET2" + set_parameter -name USE_PAL_PLL -entity core_top '1 + set_parameter -name USE_MMAPPER_SET1 -entity cart_top '0 + set_parameter -name USE_MMAPPER_SET2 -entity cart_top '1 + set_parameter -name USE_PAL_PLL -entity nes_pll_01 '1 +} else { + puts "Unknown bitstream type [lindex $argv 0]" + project_close + exit +} + +# save changes to .qsf +export_assignments + +execute_flow -compile + +project_close \ No newline at end of file diff --git a/loader/data.json b/loader/data.json new file mode 100644 index 0000000..c6b1275 --- /dev/null +++ b/loader/data.json @@ -0,0 +1,25 @@ +{ + "data": { + "magic": "APF_VER_1", + "data_slots": [ + { + "name": "Cartridge", + "id": 0, + "filename": "Lagrange Point (Japan).nes", + "required": true, + "parameters": "0x109", + "extensions": ["nes"], + "address": "0x10000000" + }, + { + "name": "Cartridge", + "id": 1, + "filename": "Super Mario Bros. 3 (USA).nes", + "required": true, + "parameters": "0x109", + "extensions": ["nes"], + "address": "0x10000000" + } + ] + } +} diff --git a/loader/nes_loader.asm b/loader/nes_loader.asm new file mode 100644 index 0000000..62da064 --- /dev/null +++ b/loader/nes_loader.asm @@ -0,0 +1,426 @@ +//Chip32 loader code for Analogizer NES Core +//RndMnkIII. 25/02/2025 : initial code - load bitstream based on NES ROM header +// 06/03/2025 : load NTSC/PAL bitstream based on iNES 2.0 ROM header. If not load NTSC by default. +//This code is based on the work of @agg23 openFPGA SNES core: https://github.com/agg23/openfpga-SNES +// Pseudocode: +// Check that is a iNES2.0 HEADER +// If it is a iNES2.0 Header Read the System Type Code: NTSC,PAL,Multisystem,Dendy(as PAL but compatible with NTSC ROMs) +// set the SysType to he readed code +// Load by default core NTSC +// If is MultiSystem read the FPGA space user setting for System Preference: if is Auto>NTSC, Auto>PAL or Auto>Dendy and assign type to NTSC,PAL or Dendy +// If is NTSC,PAL or Dendy and user setting Auto>... Choose the one from header setting. If the user setting is Force NTSC,PAL or Dendy, ignore header +// setting and assign the System Type based on User preference. +// If the header is not a iNES2.0 HEADER choose by default NTSC. If the user setting is Force NTSC,PAL or Dendy assign the System Type based on User preference. +arch chip32.vm +output "nes_loader.bin", create + +constant DEBUG = 1 + +//NES Cartridge data slot (see data.json core file) +constant rom_dataslot = 0 + +//Save state data slot +constant save_dataslot = 10 +constant pal_dataslot = 11 +constant analogizer_dataslot = 20 + + +//number of mapper codes to check in the data table +constant num_audio_mappers = 9 + +// Host init command +constant put_core_reset = 0x4000 +constant core_take_out_reset = 0x4001 +constant host_init = 0x4002 + +//Addresses +constant is_nes20_mapper = 0x1000 +constant rom_mapper_value = 0x1004 +constant mmapper_set_value = 0x1008 + +//cpu_ppu_timing header[12][1:0] +// 00 RP2C02 ("NTSC NES") +// 01 RP2C07 ("Licensed PAL NES") +// 10 Multiple-region +// 11 UA6538 ("Dendy") +constant cpu_ppu_timing = 0x100C +constant is_nes_head = 0x1010 +constant dirty_nes_head = 0x1014 +constant nes20mapper = 0x1018 +constant load_header_area = 0x1A00 +constant load_analogizer_cfg_area = 0x1B00 + + +// Error vector (0x0) +jp error_handler + +// Init vector (0x2) +jp start + +/// Includes /// +include "util.asm" +align(2) + +// data (word size) +audio_mapper_codes: +//hex:5,13,14,18,1A,1F,45,55,D2 +dw 5,19,20,24,26,31,69,85,210 +//dw 5,19,547,24,26,31,69,85,210 //for testing only + +start: +ld r1,#rom_dataslot //populate data slot +open r1,r2 + +//Load header values into memory +ld r1,#0 +seek() +ld r1,#0x10 // Load 0x10 bytes, the NES/NES2 header size +ld r2,#load_header_area // Read into read_space memory +read() +close +log_string("Loaded header data") +ld.l r3,(load_header_area) + +//Check that is a valid NES header +cmp r3,#0x1A53454E // Compare against 0xFFFF +jp nz, error_invalid_nes_header // If not equal, skip +log_string("Seems a iNES header...") +ld r10,#0 +//check header[7][3:2] == 2'b10 +ld.b r4,(load_header_area + 7) +lsr r4,#2 +and r4,#2 +jp z,is_dirty +log_string("Seems a iNES 2.0 header...") +ld r10,#1 //Uses R10 as iNES2.0 check + +is_dirty: + //check is not ines2.0 + bit r10,#1 + jp nz, calculate_code + + log_string("Checking header[9][7:1] != 0...") + //check header[9][7:1] != 0 + ld.b r4,(load_header_area + 9) + and r4,#0xFE //mask bits 7-1 + cmp r4,#0 //check if all bits are zero + jp z, is_dirty_chk2 + ld r11,#1 ////Uses R11 as dirty check + jp calculate_code +is_dirty_chk2: +log_string("Checking header[10]!= 0...") + //check header[10]!= 0 + ld.b r4,(load_header_area + 10) + cmp r4,#0 //check if all bits are zero + jp z, is_dirty_chk3 + ld r11,#1 ////Uses R11 as dirty check + jp calculate_code +is_dirty_chk3: +log_string("Checking header[11]!= 0...") + //check header[11]!= 0 + ld.b r4,(load_header_area + 11) + cmp r4,#0 //check if all bits are zero + jp z, is_dirty_chk4 + ld r11,#1 ////Uses R11 as dirty check + jp calculate_code +is_dirty_chk4: +log_string("Checking header[12]!= 0...") + //check header[12]!= 0 + ld.b r4,(load_header_area + 12) + cmp r4,#0 //check if all bits are zero + jp z, is_dirty_chk5 + ld r11,#1 ////Uses R11 as dirty check + jp calculate_code +is_dirty_chk5: +log_string("Checking header[13]!= 0...") + //check header[13]!= 0 + ld.b r4,(load_header_area + 13) + cmp r4,#0 //check if all bits are zero + jp z, is_dirty_chk6 + ld r11,#1 ////Uses R11 as dirty check + jp calculate_code +is_dirty_chk6: +log_string("Checking header[14]!= 0...") + //check header[14]!= 0 + ld.b r4,(load_header_area + 14) + cmp r4,#0 //check if all bits are zero + jp z, is_dirty_chk7 + ld r11,#1 ////Uses R11 as dirty check + jp calculate_code +is_dirty_chk7: +log_string("Checking header[15s]!= 0...") + //check header[15]!= 0 + ld.b r4,(load_header_area + 15) + cmp r4,#0 //check if all bits are zero + jp z, calculate_code + ld r11,#1 ////Uses R11 as dirty check + +calculate_code: + ld.b r3,(load_header_area + 6) + ld.b r4,(load_header_area + 7) + ld.b r5,(load_header_area + 8) //used for ines2.0 mapper value (16bits) + ld r6,#0 //temp register to store mapper code + + //check is dirty + bit r11,#1 + jp nz, calculate_code2 + log_string("Calculate code for clean header...") + + //is not dirty + ld r6,r4 //load header[7] + and r6,#0xF0 //mask upper nibble of header[7] + and r3,#0xF0 //mask upper nibble of header[6] + lsr r3,#4 //shift header[6] + or r6,r3 // {header[7][7:4], header[6][7:4]} + jp calculate_code3 + +calculate_code2: + //is dirty + log_string("Calculate code for dirty header...") + and r3,#0xF0 //mask upper nibble of header[6] + lsr r3,#4 //shift header[6] + or r6,r3 // {4'b0000, header[6][7:4]} + +calculate_code3: + //check is ines2.0 + bit r10,#1 + jp z, store_mapper_value + + log_string("Calculate code for ines2.0 header...") + //shift left 8 bits + and r5,#3 + asl r5,#8 + or r6,r5 //combine with already stored value + +store_mapper_value: + ld r7,#rom_mapper_value + ld.w (r7),r6 + +check_mmapper_code: + //use r3 as counter, init to 0 + //r4 #num_audio_mappers + //r5 base: #audio_mapper_codes (word) + //r6 current checked code address + //r7 current checked code (word) + //r8 tmp for mapper code address + //r9 mapper code value (word) + //r12 mapper set: 0 block1, 1 block2 + + log_string("Checking mapper code...") + + ld r3,#0 + ld r12,#0 //by default mapper set block1 + ld r4,#num_audio_mappers + ld r6,#audio_mapper_codes + ld r8,#rom_mapper_value + ld.w r9,(r8) + +check_mapper_code_loop: + cmp r4,r3 //check if all cores were already checked + jp z, analogizer_conf_file_chk + + ld.w r7,(r6) //load the current code to check + cmp r7,r9 //if are equal assign set2 mapper and exit loop + jp z, block_set2 + //increase counter and address + add r3,#1 //increase code count + add r6,#2 //advance 2 bytes (1 word) + jp check_mapper_code_loop + +block_set2: + log_string("Mapper is set Block2 (audio mapper)...") + ld r12,#1 //mapper set block2 (audio mappers) + +//*** Analogizer configuration code *** +analogizer_conf_file_chk: + ld r1,#analogizer_dataslot //populate data slot + + //check if exist + queryslot r1 + jp nz,check_system + //the file exist, then proceed to load the configuration data + open r1,r2 + + //Load analogizer configuration into memory + ld r1,#0 + seek2() + ld r1,#0x4 // Load 0x4 bytes + ld r2,#load_analogizer_cfg_area // Read into read_space memory + read2() + close + + log_string("Loaded Analogizer configuration data") + + //for simulator testing only, disable on real system + //ld r3,#0x000588A2 + //ld.l (load_analogizer_cfg_area),r3 // bits[19:16]: 0 Auto>NTSC, 1 Auto>PAL, 2 Auto>Dendy, 3 Force NTSC, 4 Force PAL, 5 Force Dendy + + //regional settigs bit[19:16] from Analogizer Config (AC) are stored into r4 + ld.l r4,(load_analogizer_cfg_area) + ld r3,#16 //number of positions to shift + lsr r4,r3 //right shift + and r4,#0xF //mask the lower 4 bits + +check_system: + //AC -> r4 + //ROM_TYPE -> r6 + //SYS_TYPE -> r5 + log_string("*** Checking system ***") + + //store SYS_TYPE into r5 + ld r5,#0 //default SYS_TYPE is NTSC + + //check is ines2.0 + cmp r10,#1 + jp nz, load_core //core #0 or #1 based on mapper value + + //load ROM_TYPE into r6 + ld.b r6,(load_header_area + 0xC) //System for iNES2.0 + and r6,#3 //use two lower bits + + //*** Start the configuration of SYS_TYPE *** + log_string("*** Start the configuration of SYS_TYPE ***") + + //If AC is "Force NTSC" + cmp r4,#3 + jp z, set_AC_to_NTSC + + //If AC is "Force PAL" + cmp r4,#4 + jp z, set_AC_to_PAL + + //If AC is "Force Dendy" + cmp r4,#5 + jp z, set_AC_to_Dendy + + //now starts the auto detect behaviour + //If ROM_TYPE is NTSC + cmp r6,#0 + jp z, set_AC_to_NTSC + + //If ROM_TYPE is PAL + cmp r6,#1 + jp z, set_AC_to_PAL + + //If ROM_TYPE is Dendy + cmp r6,#3 + jp z, set_AC_to_Dendy + + //If ROM_TYPE is Multi-Region, then needs to dissambiguate + cmp r6,#2 + jp nz, AC_already_set + + //If AC is "Auto>NTSC" (is the default value and SYS_TYPE don't need to change) + cmp r4,#0 + jp z, set_AC_to_NTSC + + //If AC is "Auto>PAL" + cmp r4,#1 + jp z, set_AC_to_PAL + + //If AC is "Auto>Dendy" + cmp r4,#2 + jp z, set_AC_to_Dendy + jp AC_already_set + +set_AC_to_NTSC: + ld r5,#0 + jp AC_already_set + +set_AC_to_PAL: + ld r5,#1 + jp AC_already_set + +set_AC_to_Dendy: + ld r5,#2 + jp AC_already_set + +AC_already_set: + ld r8,r5 //copy SYS_TYPE to to r8 + and r8,#1 //take bit 0 on r8: 0 NTSC/Dendy, 1 PAL + asl r8,#1 //multiply by 2 + or r12,r8 //add r8 to r12 now the bitstream to load is encoded into r12 + +load_core: + //load the core based on mapper code selection and region setting + core r12 //core #0 NTSC Block 1, core #1 NTSC Block 2 (audio mappers), core #2 PAL/Dendy Block 1, core #3 PAL/Dendy Block 2 + +load_settings: + //load assets files + ld r1,#rom_dataslot + loadf r1 // Load ROM + + ld r1,#save_dataslot + loadf r1 // Load Save + + ld r1,#pal_dataslot + loadf r1 // Load Palettes + + ld r1,#analogizer_dataslot + loadf r1 // Load Analogizer settings + + //Send SYS_TYPE to the CORE at address 0x330 + ld r8,#0x330 + pmpw r8,r5 + + //send ROM_TYPE + //ld r8,#0x334 + //pmpw r8,r6 + + //send AC + //ld r8,#0x338 + //pmpw r8,r4 + + //send iNES2.0 + //ld r8,#0x33C + //pmpw r8,r10 + + // Start core + ld r0,#host_init + host r0,r0 + exit 0 + +invalid_nes_header: +close +exit 1 + +error_handler: +ld r14,#test_err_msg + +print: +printf r14 +exit 1 + +error_invalid_nes_header: +ld r14,#invalid_nes_header_msg +printf r14 +exit 1 + +test_err_msg: +db "Error",0 +align(2) + +invalid_nes_header_msg: +db "Invalid NES header",0 +align(2) + + + + + + + + + + + + + + + + + + + + + diff --git a/loader/nes_loader.bin b/loader/nes_loader.bin new file mode 100644 index 0000000..84ba2b2 Binary files /dev/null and b/loader/nes_loader.bin differ diff --git a/loader/util.asm b/loader/util.asm new file mode 100644 index 0000000..f26f255 --- /dev/null +++ b/loader/util.asm @@ -0,0 +1,75 @@ +/// Util Functions /// + +// Seek function +// Input: location - r1 +// Clobbers Z +macro seek() { + seek r1 + jp z, seek_end + + // Failed to seek + ld r14,#seek_err + printf r14 + hex.l r1 + exit 1 + + seek_end: +} + +// Read function +// Input: length - r1 +// Input: ouput memory address - r2 +// Clobbers Z +macro read() { + read r2,r1 + jp z, read_end + + // Failed to read + ld r14,#read_err + printf r14 + hex.l r1 + exit 1 + + read_end: +} + +macro align(size) { + while (pc() % {size}) { + db 0 + } +} + +macro log_string(value) { + if DEBUG { + ld r15,#+ + printf r15 + jp ++ + + +; + db {value},0 + align(2) + +; + } +} + +macro log_hex(value) { + if DEBUG { + ld r15,#{value} + hex.l r15 + } +} + +macro log_dec(value) { + if DEBUG { + ld r15,#{value} + dec.l r15 + } +} + +/// Messages /// + +seek_err: +db "Seek fail 0x",0 + +read_err: +db "Read fail length 0x",0 diff --git a/pkg/pocket/Cores/agg23.NES/core.json b/pkg/pocket/Cores/agg23.NES/core.json index ca109ce..3625a2e 100644 --- a/pkg/pocket/Cores/agg23.NES/core.json +++ b/pkg/pocket/Cores/agg23.NES/core.json @@ -3,14 +3,15 @@ "magic": "APF_VER_1", "metadata": { "platform_ids": [ - "nes" + "nes", + "analogizer" ], "shortname": "NES", "description": "Nintendo Entertainment System and Famicom. Nintendo's first home console", "author": "agg23", "url": "https://github.com/agg23/openFPGA-NES", - "version": "1.0.1", - "date_release": "2024-09-16" + "version": "1.0.3", + "date_release": "2025-03-22" }, "framework": { "target_product": "Analogue Pocket", @@ -22,14 +23,30 @@ }, "hardware": { "link_port": false, - "cartridge_adapter": -1 - } + "cartridge_adapter": 0 + }, + "chip32_vm": "nes_loader.bin" }, "cores": [ { - "name": "default", + "name": "NTSC_SET1", "id": 0, - "filename": "nes.rev" + "filename": "NTSC_SET1.rev" + }, + { + "name": "NTSC_SET2", + "id": 1, + "filename": "NTSC_SET2.rev" + }, + { + "name": "PAL_SET1", + "id": 2, + "filename": "PAL_SET1.rev" + }, + { + "name": "PAL_SET2", + "id": 3, + "filename": "PAL_SET2.rev" } ] } diff --git a/pkg/pocket/Cores/agg23.NES/data.json b/pkg/pocket/Cores/agg23.NES/data.json index 98dfd03..93048b6 100644 --- a/pkg/pocket/Cores/agg23.NES/data.json +++ b/pkg/pocket/Cores/agg23.NES/data.json @@ -29,7 +29,19 @@ "extensions": ["pal"], "size_maximum": "0xC0", "address": "0x10000000" - } + }, + { + "name": "Analogizer config", + "id": 20, + "required": false, + "parameters": "0x1000000", + "filename": "analogizer.bin", + "extensions": [ + "bin" + ], + "address": "0xF7000000", + "nonvolatile": false + } ] } } diff --git a/pkg/pocket/Cores/agg23.NES/interact.json b/pkg/pocket/Cores/agg23.NES/interact.json index 937843f..7a5e7c2 100644 --- a/pkg/pocket/Cores/agg23.NES/interact.json +++ b/pkg/pocket/Cores/agg23.NES/interact.json @@ -10,6 +10,17 @@ "address": "0x50", "value": 1 }, + { + "name": "Enable Analogizer", + "id": 31, + "type": "check", + "enabled": true, + "address": "0x31C", + "persist": true, + "writeonly": true, + "defaultval": 0, + "value": 1 + }, { "name": "Use Multitap", "id": 20, @@ -27,6 +38,26 @@ "type": "action", "enabled": false }, + { + "name": "Video Dejitter", + "id": 44, + "type": "list", + "enabled": true, + "persist": true, + "writeonly": true, + "address": "0x32C", + "defaultval": 0, + "options": [ + { + "value": 0, + "name": "Enabled" + }, + { + "value": 1, + "name": "Disabled" + } + ] + }, { "name": "Hide Overscan", "id": 40, @@ -167,13 +198,26 @@ { "name": "Use Zapper", "id": 81, - "type": "check", + "type": "list", "enabled": true, - "address": "0x304", "persist": true, "writeonly": true, + "address": "0x304", "defaultval": 0, - "value": 1 + "options": [ + { + "value": 0, + "name": "Off" + }, + { + "value": 1, + "name": "Emulated Zapper (Stick)" + }, + { + "value": 2, + "name": "SNAC Zapper" + } + ] }, { "name": "D-Pad Aim Speed", diff --git a/pkg/pocket/Cores/agg23.NES/nes_loader.bin b/pkg/pocket/Cores/agg23.NES/nes_loader.bin new file mode 100644 index 0000000..84ba2b2 Binary files /dev/null and b/pkg/pocket/Cores/agg23.NES/nes_loader.bin differ diff --git a/platform/pocket/pocket.tcl b/platform/pocket/pocket.tcl index e06701e..d394109 100644 --- a/platform/pocket/pocket.tcl +++ b/platform/pocket/pocket.tcl @@ -38,7 +38,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" # ============================================================================== # Signal Tap Assignments # ============================================================================== -set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name ENABLE_SIGNALTAP OFF # ============================================================================== # Pin & Location Assignments diff --git a/projects/nes_pocket.qsf b/projects/nes_pocket.qsf index 847fc54..9b10870 100644 --- a/projects/nes_pocket.qsf +++ b/projects/nes_pocket.qsf @@ -10,7 +10,7 @@ # Project-Wide Assignments # ============================================================================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1 -set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" set_global_assignment -name TOP_LEVEL_ENTITY apf_top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top @@ -22,14 +22,14 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files # ============================================================================== set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SEED 1 +set_global_assignment -name SEED 2 set_global_assignment -name SMART_RECOMPILE ON # ============================================================================== # Analysis & Synthesis Assignments # ============================================================================== set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON -set_global_assignment -name MUX_RESTRUCTURE OFF +set_global_assignment -name MUX_RESTRUCTURE ON set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON set_global_assignment -name SAFE_STATE_MACHINE ON @@ -56,9 +56,6 @@ set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" # Platform/Core Assignments # ============================================================================== source ../platform/pocket/pocket.tcl -set_global_assignment -name QIP_FILE nes_pocket.qip -set_global_assignment -name SDC_FILE nes_pocket.sdc -set_global_assignment -name QIP_FILE ../rtl/nes.qip # ============================================================================== @@ -66,4 +63,26 @@ set_global_assignment -name QIP_FILE ../rtl/nes.qip set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name QIP_FILE ../analogizer/analogizer.qip +set_global_assignment -name QIP_FILE ../platform/pocket/apf.qip +set_global_assignment -name QIP_FILE ../target/pocket/core.qip +set_global_assignment -name QIP_FILE nes_pocket.qip +set_global_assignment -name SDC_FILE nes_pocket.sdc +set_global_assignment -name QIP_FILE ../rtl/nes.qip +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS +set_global_assignment -name IGNORE_PARTITIONS ON +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON +set_parameter -name USE_MMAPPER_SET1 '1 -entity cart_top +set_parameter -name USE_MMAPPER_SET2 '0 -entity cart_top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_parameter -name USE_PAL_PLL '1 -entity core_top +set_parameter -name USE_PAL_PLL '1 -entity nes_pll_01 \ No newline at end of file diff --git a/rtl/cart.sv b/rtl/cart.sv index 24f7b85..cfbad67 100644 --- a/rtl/cart.sv +++ b/rtl/cart.sv @@ -14,8 +14,11 @@ // CHR-VRAM = 1100 // CPU-RAM = 1110 // CARTRAM = 1111 - -module cart_top ( +//SET1 mapper codes: +// +//SET2 mapper codes:5,69,24,26,85,210,19,20,31,69 +module cart_top +( input clk, input ce, // M2 input cpu_ce, // CPU Phi1 clock (several mappers use m2 inverted) @@ -76,6 +79,16 @@ module cart_top ( output [7:0] Savestate_MAPRAMReadData ); +parameter USE_MMAPPER_SET1 = 1'b0; +parameter USE_MMAPPER_SET2 = 1'b1; //all audio mappers +initial begin + $info("%%%%%%%%%%%%%%%%%%%%%%%%%%%%"); + $info("cart.sv: Selected System PLL"); + $info("USE_MMAPPER_SET1 %d", USE_MMAPPER_SET1); + $info("USE_MMAPPER_SET2 %d", USE_MMAPPER_SET2); + $info("%%%%%%%%%%%%%%%%%%%%%%%%%%%%"); +end + tri0 prg_allow_b, vram_a10_b, vram_ce_b, chr_allow_b, irq_b; tri0 [21:0] prg_addr_b, chr_addr_b; tri0 [15:0] flags_out_b, audio_out_b; @@ -121,36 +134,40 @@ MMC0 mmc0( // Notes : // // Games : Simon's Quest // //*****************************************************************************// -MMC1 mmc1( - .clk (clk), - .ce (ce), - .enable (me[171] | me[155] | me[1]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[0]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + MMC1 mmc1( + .clk (clk), + .ce (ce), + .enable (me[171] | me[155] | me[1]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[0]) + ); + end +endgenerate //*****************************************************************************// // Name : Tepples // @@ -159,38 +176,42 @@ MMC1 mmc1( // Notes : This mapper relies on open bus and bus conflict behavior. // // Games : Donkey Kong // //*****************************************************************************// -wire mapper28_en = me[0] | me[2] | me[3] | me[7] | me[94] | me[97] | me[180] | me[185] | me[28]; -Mapper28 map28( - .clk (clk), - .ce (ce), - .enable (mapper28_en & ~reset), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_dout_b (chr_dout_b), // Special port - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[1]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + wire mapper28_en = me[0] | me[2] | me[3] | me[7] | me[94] | me[97] | me[180] | me[185] | me[28]; + Mapper28 map28( + .clk (clk), + .ce (ce), + .enable (mapper28_en & ~reset), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_dout_b (chr_dout_b), // Special port + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[1]) + ); + end +endgenerate //*****************************************************************************// // Name : UNROM 512 // @@ -199,36 +220,40 @@ Mapper28 map28( // Notes : Homebrew mapper // // Games : ? // //*****************************************************************************// -Mapper30 map30( - .clk (clk), - .ce (ce), - .enable (me[30]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[26]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper30 map30( + .clk (clk), + .ce (ce), + .enable (me[30]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[26]) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 32 // @@ -237,36 +262,40 @@ Mapper30 map30( // Notes : // // Games : Image Fight // //*****************************************************************************// -Mapper32 map32( - .clk (clk), - .ce (ce), - .enable (me[32]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[28]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper32 map32( + .clk (clk), + .ce (ce), + .enable (me[32]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[28]) + ); + end +endgenerate //*****************************************************************************// // Name : MMC2 // @@ -275,39 +304,43 @@ Mapper32 map32( // Notes : Working // // Games : Mike Tyson's Punch-Out // //*****************************************************************************// -MMC2 mmc2( - .clk (clk), - .ce (ce), - .enable (me[9]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special ports - .chr_ain_o (chr_ain_orig), - .paused (paused), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[6]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + MMC2 mmc2( + .clk (clk), + .ce (ce), + .enable (me[9]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special ports + .chr_ain_o (chr_ain_orig), + .paused (paused), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[6]) + ); + end +endgenerate //*****************************************************************************// // Name : MMC3 // @@ -317,44 +350,49 @@ MMC2 mmc2( // Notes : While currently working well, this mapper could use a full review. // // Games : Crystalis, Battletoads // //*****************************************************************************// -wire mmc3_en = me[118] | me[119] | me[47] | me[206] | me[112] | me[88] | me[154] | me[95] - | me[76] | me[80] | me[82] | me[207] | me[48] | me[33] | me[37] | me[74] | me[191] - | me[192] | me[194] | me[195] | me[196] | me[4] | me[189] | me[268]; - -MMC3 mmc3 ( - .clk (clk), - .ce (ce), - .enable (mmc3_en), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special ports - .chr_ain_o (chr_ain_orig), - .m2_inv (cpu_ce), - .paused (paused), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[2]) -); +generate + //if (USE_MMAPPER_SET1 == 1'b1) begin + if (USE_MMAPPER_SET1 == 1'b1) begin + wire mmc3_en = me[118] | me[119] | me[47] | me[206] | me[112] | me[88] | me[154] | me[95] + | me[76] | me[80] | me[82] | me[207] | me[48] | me[33] | me[37] | me[74] | me[191] + | me[192] | me[194] | me[195] | me[196] | me[4] | me[189] | me[268]; + + MMC3 mmc3 ( + .clk (clk), + .ce (ce), + .enable (mmc3_en), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special ports + .chr_ain_o (chr_ain_orig), + .m2_inv (cpu_ce), + .paused (paused), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[2]) + ); + end +endgenerate //*****************************************************************************// // Name : MMC4 // @@ -363,39 +401,43 @@ MMC3 mmc3 ( // Notes : // // Games : Fire Emblem // //*****************************************************************************// -MMC4 mmc4( - .clk (clk), - .ce (ce), - .enable (me[10]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special ports - .chr_ain_o (chr_ain_orig), - .paused (paused), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[7]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + MMC4 mmc4( + .clk (clk), + .ce (ce), + .enable (me[10]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special ports + .chr_ain_o (chr_ain_orig), + .paused (paused), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[7]) + ); + end +endgenerate //*****************************************************************************// // Name : MMC5 // @@ -404,6 +446,8 @@ MMC4 mmc4( // Notes : Uses expansion audio and PPU hacks. Could use a thorough review. // // Games : Castlevania III, Just Breed // //*****************************************************************************// +generate + if (USE_MMAPPER_SET2 == 1'b1) begin MMC5 mmc5( .clk (clk), .ce (ce), @@ -449,6 +493,8 @@ MMC5 mmc5( .Savestate_MAPRAMWriteData(Savestate_MAPRAMWriteData), .Savestate_MAPRAMReadData (SaveStateRAM_wired_or[1]) ); + end +endgenerate //*****************************************************************************// // Name : CPROM // @@ -457,29 +503,33 @@ MMC5 mmc5( // Notes : // // Games : Videomation // //*****************************************************************************// -Mapper13 map13( - .clk (clk), - .ce (ce), - .enable (me[13]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper13 map13( + .clk (clk), + .ce (ce), + .enable (me[13]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 15 // @@ -488,29 +538,33 @@ Mapper13 map13( // Notes : // // Games : Bao Xiao San Guo // //*****************************************************************************// -Mapper15 map15( - .clk (clk), - .ce (ce), - .enable (me[15]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper15 map15( + .clk (clk), + .ce (ce), + .enable (me[15]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Bandai 16 // @@ -522,42 +576,47 @@ Mapper15 map15( wire map16_prg_write, map16_ovr; wire [7:0] map16_data_out; wire [17:0] map16_mapper_addr; -Mapper16 map16( - .clk (clk), - .ce (ce), - .enable (me[159] | me[153] | me[16]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special Ports - .mapper_addr(map16_mapper_addr), - .mapper_data_in(mapper_data_in), - .mapper_data_out(map16_data_out), - .mapper_prg_write(map16_prg_write), - .mapper_ovr(map16_ovr), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[5]) -); +generate + //if (USE_MMAPPER_SET1 == 1'b1) begin + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper16 map16( + .clk (clk), + .ce (ce), + .enable (me[159] | me[153] | me[16]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special Ports + .mapper_addr(map16_mapper_addr), + .mapper_data_in(mapper_data_in), + .mapper_data_out(map16_data_out), + .mapper_prg_write(map16_prg_write), + .mapper_ovr(map16_ovr), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[5]) + ); + end +endgenerate //*****************************************************************************// // Name : Jaleco 18 // @@ -566,36 +625,40 @@ Mapper16 map16( // Notes : // // Games : Pizza Pop!, Plasma Ball, USA Ice Hockey in FC // //*****************************************************************************// -Mapper18 map18( - .clk (clk), - .ce (ce), - .enable (me[18]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[27]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper18 map18( + .clk (clk), + .ce (ce), + .enable (me[18]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[27]) + ); + end +endgenerate //*****************************************************************************// // Name : BNROM // @@ -604,36 +667,40 @@ Mapper18 map18( // Notes : // // Games : Mashou, Deadly Towers // //*****************************************************************************// -Mapper34 map34( - .clk (clk), - .ce (ce), - .enable (me[34]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[31]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper34 map34( + .clk (clk), + .ce (ce), + .enable (me[34]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[31]) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 41 // @@ -642,29 +709,33 @@ Mapper34 map34( // Notes : // // Games : Caltron 6-in-1 // //*****************************************************************************// -Mapper41 map41( - .clk (clk), - .ce (ce), - .enable (me[41]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper41 map41( + .clk (clk), + .ce (ce), + .enable (me[41]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 42 // @@ -673,29 +744,33 @@ Mapper41 map41( // Notes : Used for converted FDS carts. // // Games : Love Warrior Nicol, Green Beret (unl) // //*****************************************************************************// -Mapper42 map42( - .clk (clk), - .ce (ce), - .enable (me[42]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper42 map42( + .clk (clk), + .ce (ce), + .enable (me[42]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Irem H3001 // @@ -704,36 +779,40 @@ Mapper42 map42( // Notes : // // Games : Spartan X 2, Daiku no Gen-san 2 // //*****************************************************************************// -Mapper65 map65( - .clk (clk), - .ce (ce), - .enable (me[65]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[29]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper65 map65( + .clk (clk), + .ce (ce), + .enable (me[65]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[29]) + ); + end +endgenerate //*****************************************************************************// // Name : GxROM // @@ -742,37 +821,41 @@ Mapper65 map65( // Notes : // // Games : Doraemon, Dragon Power, Sidewinder (145), Taiwan Mahjong 16 (149) // //*****************************************************************************// -wire mapper66_en = me[11] | me[38] | me[46] | me[86] | me[87] | me[101] | me[140] | me[66] | me[145] | me[149]; -Mapper66 map66( - .clk (clk), - .ce (ce), - .enable (mapper66_en), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[3]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + wire mapper66_en = me[11] | me[38] | me[46] | me[86] | me[87] | me[101] | me[140] | me[66] | me[145] | me[149]; + Mapper66 map66( + .clk (clk), + .ce (ce), + .enable (mapper66_en), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[3]) + ); + end +endgenerate //*****************************************************************************// // Name : Sunsoft-3 // @@ -781,36 +864,40 @@ Mapper66 map66( // Notes : // // Games : Fantasy Zone II, Mito Koumon // //*****************************************************************************// -Mapper67 map67( - .clk (clk), - .ce (ce), - .enable (me[67] | me[190]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[20]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper67 map67( + .clk (clk), + .ce (ce), + .enable (me[67] | me[190]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[20]) + ); + end +endgenerate //*****************************************************************************// // Name : Sunsoft-4 // @@ -819,36 +906,40 @@ Mapper67 map67( // Notes : // // Games : After Burner (J), Majaraja // //*****************************************************************************// -Mapper68 map68( - .clk (clk), - .ce (ce), - .enable (me[68]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[21]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper68 map68( + .clk (clk), + .ce (ce), + .enable (me[68]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[21]) + ); + end +endgenerate //*****************************************************************************// // Name : Sunsoft FME-7 // @@ -857,36 +948,40 @@ Mapper68 map68( // Notes : Audio needs better mixing/processing // // Games : Gimmick!, Barcode World, Hebereke // //*****************************************************************************// -Mapper69 map69( - .clk (clk), - .ce (ce), - .enable (me[69]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (ss5b_audio), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[12]) -); +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + Mapper69 map69( + .clk (clk), + .ce (ce), + .enable (me[69]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (ss5b_audio), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[12]) + ); + end +endgenerate //*****************************************************************************// // Name : Codemasters/Camerica // @@ -895,36 +990,40 @@ Mapper69 map69( // Notes : // // Games : Micro Machines, Big Nose the Caveman // //*****************************************************************************// -Mapper71 map71( - .clk (clk), - .ce (ce), - .enable (me[71] | me[232]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[8]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper71 map71( + .clk (clk), + .ce (ce), + .enable (me[71] | me[232]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[8]) + ); + end +endgenerate //*****************************************************************************// // Name : Jaleco JF-17 // @@ -933,36 +1032,40 @@ Mapper71 map71( // Notes : // // Games : Pro Tennis (J), Pinball Quest (J), Pro Soccer (J) // //*****************************************************************************// -Mapper72 map72( - .clk (clk), - .ce (ce), - .enable (me[92] | me[72]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[30]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper72 map72( + .clk (clk), + .ce (ce), + .enable (me[92] | me[72]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[30]) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 77 // @@ -971,36 +1074,40 @@ Mapper72 map72( // Notes : // // Games : Napoleon Senki // //*****************************************************************************// -Mapper77 map77( - .clk (clk), - .ce (ce), - .enable (me[77]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[32]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper77 map77( + .clk (clk), + .ce (ce), + .enable (me[77]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[32]) + ); + end +endgenerate //*****************************************************************************// // Name : Holy Diver // @@ -1009,36 +1116,40 @@ Mapper77 map77( // Notes : Submapper 1 Requires NES 2.0 // // Games : Holy Diver, Uchuusent // //*****************************************************************************// -Mapper78 map78( - .clk (clk), - .ce (ce), - .enable (me[152] | me[70] | me[78]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[33]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper78 map78( + .clk (clk), + .ce (ce), + .enable (me[152] | me[70] | me[78]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[33]) + ); + end +endgenerate //*****************************************************************************// // Name : NINA // @@ -1048,36 +1159,40 @@ Mapper78 map78( // Games : Tiles of Fate, Dudes with Attitude, Krazy Kreatures, // // Twin Eagle (146), Mahjong World (148), Jovial Race (133) // //*****************************************************************************// -Mapper79 map79( - .clk (clk), - .ce (ce), - .enable (me[79] | me[113] | me[133] | me[146] | me[148]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[4]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper79 map79( + .clk (clk), + .ce (ce), + .enable (me[79] | me[113] | me[133] | me[146] | me[148]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[4]) + ); + end +endgenerate //*****************************************************************************// // Name : Cony/Yoko (unlicensed) // @@ -1086,29 +1201,33 @@ Mapper79 map79( // Notes : No user ability to control dipswitch setting // // Games : Fatal Fury 2, World Heroes 2, Dragon Ball Party // //*****************************************************************************// -Mapper83 map83( - .clk (clk), - .ce (ce), - .enable (me[83]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper83 map83( + .clk (clk), + .ce (ce), + .enable (me[83]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Sunsoft // @@ -1117,36 +1236,40 @@ Mapper83 map83( // Notes : // // Games : Tenka no Goikenban // //*****************************************************************************// -Mapper89 map89( - .clk (clk), - .ce (ce), - .enable (me[89] | me[93] | me[184]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[34]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper89 map89( + .clk (clk), + .ce (ce), + .enable (me[89] | me[93] | me[184]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[34]) + ); + end +endgenerate //*****************************************************************************// // Name : Magic Dragon // @@ -1155,29 +1278,33 @@ Mapper89 map89( // Notes : // // Games : Magic Dragon // //*****************************************************************************// -Mapper107 map107( - .clk (clk), - .ce (ce), - .enable (me[107]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper107 map107( + .clk (clk), + .ce (ce), + .enable (me[107]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : GTROM // @@ -1186,36 +1313,40 @@ Mapper107 map107( // Notes : No LED or self-reflash support // // Games : Super Homebrew War, Candelabra: Estoscerro, more homebrew // //*****************************************************************************// -Mapper111 map111( - .clk (clk), - .ce (ce), - .enable (me[111]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[25]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper111 map111( + .clk (clk), + .ce (ce), + .enable (me[111]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[25]) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 165 // @@ -1224,33 +1355,37 @@ Mapper111 map111( // Notes : Possibly merge-able with MMC3, only used for one bootleg game // // Games : Fire Emblem (unl) // //*****************************************************************************// -Mapper165 map165( - .clk (clk), - .ce (ce), - .enable (me[165]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special ports - .chr_ain_o (chr_ain_orig), - .m2_inv (cpu_ce), - .paused (paused) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper165 map165( + .clk (clk), + .ce (ce), + .enable (me[165]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special ports + .chr_ain_o (chr_ain_orig), + .m2_inv (cpu_ce), + .paused (paused) + ); + end +endgenerate //*****************************************************************************// // Name : Magic Floor // @@ -1259,31 +1394,35 @@ Mapper165 map165( // Notes : Appears unused in modern packs? // // Games : Magic Floor // //*****************************************************************************// -Mapper218 map218( - .clk (clk), - .ce (ce), - .enable (me[218]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) - // savestates - // savestates support - but no state in mapper needs saving -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper218 map218( + .clk (clk), + .ce (ce), + .enable (me[218]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + // savestates + // savestates support - but no state in mapper needs saving + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 227 // @@ -1292,29 +1431,33 @@ Mapper218 map218( // Notes : // // Games : 1200-in-1, 600-in-1, Bio Hazard // //*****************************************************************************// -Mapper227 map227( - .clk (clk), - .ce (ce), - .enable (me[227]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper227 map227( + .clk (clk), + .ce (ce), + .enable (me[227]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Active Enterprises // @@ -1323,29 +1466,33 @@ Mapper227 map227( // Notes : // // Games : Cheetamen // //*****************************************************************************// -Mapper228 map228( - .clk (clk), - .ce (ce), - .enable (me[228]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper228 map228( + .clk (clk), + .ce (ce), + .enable (me[228]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Maxi 15 // @@ -1356,29 +1503,33 @@ Mapper228 map228( // the system itself is not behaving correctly. // // Games : Maxi-15 Pack (unl) // //*****************************************************************************// -Mapper234 map234( - .clk (clk), - .ce (ce), - .enable (me[234]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_from_ram), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper234 map234( + .clk (clk), + .ce (ce), + .enable (me[234]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_from_ram), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 246 // @@ -1387,29 +1538,33 @@ Mapper234 map234( // Notes : // // Games : Feng Shen Bang // //*****************************************************************************// +generate + if (USE_MMAPPER_SET1 == 1'b1) begin Mapper246 map246( - .clk (clk), - .ce (ce), - .enable (me[246]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); + .clk (clk), + .ce (ce), + .enable (me[246]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : RAMBO1 (Tengen MMC3) // @@ -1418,38 +1573,42 @@ Mapper246 map246( // Notes : Consider merging with MMC3 // // Games : Rolling Thunder, Klax, Skull and Crossbones, Alien Syndrome (158) // //*****************************************************************************// -Rambo1 rambo1( - .clk (clk), - .ce (ce), - .enable (me[64] | me[158]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special ports - .chr_ain_o (chr_ain_orig), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[24]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Rambo1 rambo1( + .clk (clk), + .ce (ce), + .enable (me[64] | me[158]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special ports + .chr_ain_o (chr_ain_orig), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[24]) + ); + end +endgenerate //*****************************************************************************// // Name : NesEvent // @@ -1458,30 +1617,33 @@ Rambo1 rambo1( // Notes : This wraps the MMC1 mapper, consider merging more elegantly // // Games : Nintendo World Championships 1990 (start hack) // //*****************************************************************************// -NesEvent nesev( - .clk (clk), - .ce (ce), - .enable (me[105]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); - +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + NesEvent nesev( + .clk (clk), + .ce (ce), + .enable (me[105]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Konami VRC-1 // @@ -1490,36 +1652,40 @@ NesEvent nesev( // Notes : // // Games : King Kong 2, Exciting Boxing, Tetsuwan Atom // //*****************************************************************************// -VRC1 vrc1( - .clk (clk), - .ce (ce), - .enable (me[75]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[18]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + VRC1 vrc1( + .clk (clk), + .ce (ce), + .enable (me[75]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[18]) + ); + end +endgenerate //*****************************************************************************// // Name : Konami VRC-3 // @@ -1528,36 +1694,40 @@ VRC1 vrc1( // Notes : // // Games : Salamander (j) // //*****************************************************************************// -VRC3 vrc3( - .clk (clk), - .ce (ce), - .enable (me[73]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[19]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + VRC3 vrc3( + .clk (clk), + .ce (ce), + .enable (me[73]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[19]) + ); + end +endgenerate //*****************************************************************************// // Name : Konami VRC2/4 // @@ -1566,36 +1736,40 @@ VRC3 vrc3( // Notes : // // Games : Wai Wai World 2, Twinbee 3, Contra (j), Gradius II (j) // //*****************************************************************************// -VRC24 vrc24( - .clk (clk), - .ce (ce), - .enable (me[21] | me[22] | me[23] | me[25] | me[27]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[9]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + VRC24 vrc24( + .clk (clk), + .ce (ce), + .enable (me[21] | me[22] | me[23] | me[25] | me[27]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[9]) + ); + end +endgenerate //*****************************************************************************// // Name : Konami VRC5 // @@ -1604,48 +1778,52 @@ VRC24 vrc24( // Notes : // // Games : Konami Q-Ta (Space School and Space College (J)) // //*****************************************************************************// -VRC5 vrc5( - .clk (clk), - .ce (ce), - .enable (me[547]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special ports - .chr_din (chr_din), - .chr_write (chr_write), - .chr_dout_b (chr_dout_b), - .paused (paused), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[36]), - - .Savestate_MAPRAMactive (Savestate_MAPRAMactive), - .Savestate_MAPRAMAddr (Savestate_MAPRAMAddr[10:0]), - .Savestate_MAPRAMRdEn (Savestate_MAPRAMRdEn), - .Savestate_MAPRAMWrEn (Savestate_MAPRAMWrEn), - .Savestate_MAPRAMWriteData(Savestate_MAPRAMWriteData), - .Savestate_MAPRAMReadData (SaveStateRAM_wired_or[2]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + VRC5 vrc5( + .clk (clk), + .ce (ce), + .enable (me[547]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special ports + .chr_din (chr_din), + .chr_write (chr_write), + .chr_dout_b (chr_dout_b), + .paused (paused), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[36]), + + .Savestate_MAPRAMactive (Savestate_MAPRAMactive), + .Savestate_MAPRAMAddr (Savestate_MAPRAMAddr[10:0]), + .Savestate_MAPRAMRdEn (Savestate_MAPRAMRdEn), + .Savestate_MAPRAMWrEn (Savestate_MAPRAMWrEn), + .Savestate_MAPRAMWriteData(Savestate_MAPRAMWriteData), + .Savestate_MAPRAMReadData (SaveStateRAM_wired_or[2]) + ); + end +endgenerate //*****************************************************************************// // Name : Konami VRC-6 // @@ -1654,36 +1832,40 @@ VRC5 vrc5( // Notes : External audio needs to be mixed correctly. // // Games : Akamajou Densetsu, Esper Dream 2, Mouryou Senki Madara // //*****************************************************************************// -VRC6 vrc6( - .clk (clk), - .ce (ce), - .enable (me[24] | me[26]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (vrc6_audio), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[10]) -); +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + VRC6 vrc6( + .clk (clk), + .ce (ce), + .enable (me[24] | me[26]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (vrc6_audio), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[10]) + ); + end +endgenerate //*****************************************************************************// // Name : Konami VRC-7 // @@ -1692,100 +1874,112 @@ VRC6 vrc6( // Notes : Audio mixing needs evaluation // // Games : Lagrange Point, Tiny Toon Aventures 2 (j) // //*****************************************************************************// -VRC7 vrc7( - .clk (clk), - .ce (ce), - .enable (me[85]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (vrc7_audio), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + VRC7 vrc7( + .clk (clk), + .ce (ce), + .enable (me[85]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (vrc7_audio), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Namco 163 // // Mappers: 19, 210 // // Status : Needs Evaluation // // Notes : This mapper requires submappers for correct operation // -// Games : Digital Devil Story, Battle Fleet, Famista // -//*****************************************************************************// -N163 n163( - .clk (clk), - .ce (ce), - .enable (me[210] | me[19]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (n163_audio), - .audio_b (audio_out_b), - // Special ports - .audio_dout (n163_data), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[14]) -); - -//*****************************************************************************// -// Name : Waixing 162 // -// Mappers: 162 // -// Status : Working // -// Notes : // -// Games : Zelda - San Shen Zhi Li // -//*****************************************************************************// -Mapper162 map162( - .clk (clk), - .ce (ce), - .enable (me[162]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +// Games : Digital Devil Story, Battle Fleet, Famista // +//*****************************************************************************// +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + N163 n163( + .clk (clk), + .ce (ce), + .enable (me[210] | me[19]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (n163_audio), + .audio_b (audio_out_b), + // Special ports + .audio_dout (n163_data), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[14]) + ); + end +endgenerate + +//*****************************************************************************// +// Name : Waixing 162 // +// Mappers: 162 // +// Status : Working // +// Notes : // +// Games : Zelda - San Shen Zhi Li // +//*****************************************************************************// +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper162 map162( + .clk (clk), + .ce (ce), + .enable (me[162]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Nanjing 163 // @@ -1794,32 +1988,35 @@ Mapper162 map162( // Notes : // // Games : Final Fantasy VII (163), Pokemon Yellow (163) // //*****************************************************************************// -Nanjing map163( - .clk (clk), - .ce (ce), - .enable (me[163]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special Ports - .paused (paused) -); - +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Nanjing map163( + .clk (clk), + .ce (ce), + .enable (me[163]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special Ports + .paused (paused) + ); + end +endgenerate //*****************************************************************************// // Name : Waixing 164 // @@ -1828,29 +2025,33 @@ Nanjing map163( // Notes : // // Games : Final Fantasy V // //*****************************************************************************// -Mapper164 map164( - .clk (clk), - .ce (ce), - .enable (me[164]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper164 map164( + .clk (clk), + .ce (ce), + .enable (me[164]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Sachen 8259 // @@ -1860,36 +2061,40 @@ Mapper164 map164( // Games : The Great Wall (137), Silver Eagle (138), Hell Fighter (139), // // Super Cart 6 - 6 in 1(141), Strategist (150), Poker III (243) // //*****************************************************************************// -Sachen8259 sachen( - .clk (clk), - .ce (ce), - .enable (me[137] | me[138] | me[139] | me[141] | me[150] | me[243]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[22]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Sachen8259 sachen( + .clk (clk), + .ce (ce), + .enable (me[137] | me[138] | me[139] | me[141] | me[150] | me[243]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[22]) + ); + end +endgenerate //*****************************************************************************// // Name : Sachen JV001 // @@ -1899,36 +2104,40 @@ Sachen8259 sachen( // Games : Wei Lai Xiao Zi (136), Chinese Kungfu (147), Creatom (132), // // F-15 City War (173), Mahjong Block (172), Strike Wolf (36) // //*****************************************************************************// -SachenJV001 sachenj( - .clk (clk), - .ce (ce), - .enable (me[136] | me[147] | me[132] | me[173] | me[172] | me[36]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[23]) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + SachenJV001 sachenj( + .clk (clk), + .ce (ce), + .enable (me[136] | me[147] | me[132] | me[173] | me[172] | me[36]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[23]) + ); + end +endgenerate //*****************************************************************************// // Name : Sachen NROM // @@ -1937,31 +2146,35 @@ SachenJV001 sachenj( // Notes : // // Games : Dancing Blocks, Magical Mathematics // //*****************************************************************************// -SachenNROM sachenn( - .clk (clk), - .ce (ce), - .enable (me[143]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) - // savestates - // savestates support - but no state in mapper needs saving -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + SachenNROM sachenn( + .clk (clk), + .ce (ce), + .enable (me[143]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + // savestates + // savestates support - but no state in mapper needs saving + ); + end +endgenerate //*****************************************************************************// // Name : JY Company // @@ -1971,39 +2184,44 @@ SachenNROM sachenn( // Games : Aladdin (90), Power Rangers 3 (209), Warioland II (35), // // Tiny Toon Adventures 6 (211) // //*****************************************************************************// -JYCompany jycompany( - .clk (clk), - .ce (ce), - .enable (me[90] | me[209] | me[211] | me[35]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special ports - .paused (paused), - .chr_ain_o (chr_ain_orig), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[35]) -); +generate + //if (USE_MMAPPER_SET1 == 1'b1) begin + if (USE_MMAPPER_SET1 == 1'b1) begin + JYCompany jycompany( + .clk (clk), + .ce (ce), + .enable (me[90] | me[209] | me[211] | me[35]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special ports + .paused (paused), + .chr_ain_o (chr_ain_orig), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[35]) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 91 // @@ -2014,30 +2232,34 @@ JYCompany jycompany( // Mario & Sonic 2, Mario Rider, // // 1995 Super HIK 4-in-1 (JY-016), 1995 Super HiK 4-in-1 (JY-017) // //*****************************************************************************// -Mapper91 map91( - .clk (clk), - .ce (ce), - .enable (me[91]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - .chr_ain_o (chr_ain_orig) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper91 map91( + .clk (clk), + .ce (ce), + .enable (me[91]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + .chr_ain_o (chr_ain_orig) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 225 // @@ -2046,31 +2268,33 @@ Mapper91 map91( // Notes : Defining 225 as with 74'670 (4-nybble RAM) and 255 as without // // Games : 64-in-1 (225), 110-in-1 (255 - with glitched menu selection) // //*****************************************************************************// -Mapper225 map225( - .clk (clk), - .ce (ce), - .enable (me[225] | me[255]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b) -); - - +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper225 map225( + .clk (clk), + .ce (ce), + .enable (me[225] | me[255]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 413 // @@ -2079,34 +2303,38 @@ Mapper225 map225( // Notes : // // Games : Super Russian Roulette // //*****************************************************************************// -Mapper413 map413 ( - .clk (clk), - .ce (ce), - .enable (me[413]), - .flags (flags), - .prg_ain (prg_ain), - .prg_aout_b (prg_addr_b), - .prg_read (prg_read), - .prg_write (prg_write), - .prg_din (prg_din), - .prg_dout_b (prg_dout_b), - .prg_allow_b(prg_allow_b), - .chr_ain (chr_ain), - .chr_aout_b (chr_addr_b), - .chr_read (chr_read), - .chr_allow_b(chr_allow_b), - .vram_a10_b (vram_a10_b), - .vram_ce_b (vram_ce_b), - .irq_b (irq_b), - .flags_out_b(flags_out_b), - .audio_in (audio_in), - .audio_b (audio_out_b), - // Special ports - .chr_ain_o (chr_ain_orig), - .prg_aoute (prg_aoute_m413), - .m2_inv (cpu_ce), - .paused (paused) -); +generate + if (USE_MMAPPER_SET1 == 1'b1) begin + Mapper413 map413 ( + .clk (clk), + .ce (ce), + .enable (me[413]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (audio_in), + .audio_b (audio_out_b), + // Special ports + .chr_ain_o (chr_ain_orig), + .prg_aoute (prg_aoute_m413), + .m2_inv (cpu_ce), + .paused (paused) + ); + end +endgenerate //*****************************************************************************// // Name : FDS // @@ -2116,37 +2344,41 @@ Mapper413 map413 ( // Games : Bio Miracle for audio, Various unlicensed games for compatibility. // //*****************************************************************************// tri0 [1:0] fds_diskside; -// MapperFDS mapfds( -// .clk (clk), -// .ce (ce), -// .enable (me[20]), -// .flags (flags), -// .prg_ain (prg_ain), -// .prg_aout_b (prg_addr_b), -// .prg_read (prg_read), -// .prg_write (prg_write), -// .prg_din (prg_din), -// .prg_dout_b (prg_dout_b), -// .prg_allow_b(prg_allow_b), -// .chr_ain (chr_ain), -// .chr_aout_b (chr_addr_b), -// .chr_read (chr_read), -// .chr_allow_b(chr_allow_b), -// .vram_a10_b (vram_a10_b), -// .vram_ce_b (vram_ce_b), -// .irq_b (irq_b), -// .flags_out_b(flags_out_b), -// .audio_in (fds_audio), -// .audio_b (audio_out_b), -// // Special ports -// .prg_dbus (prg_from_ram), -// .audio_dout (fds_data), -// .diskside_b (fds_diskside), -// .max_diskside (max_diskside), -// .fds_busy (fds_busy), -// .fds_eject_btn (fds_eject), -// .fds_auto_eject_en (fds_auto_eject) -// ); +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + MapperFDS mapfds( + .clk (clk), + .ce (ce), + .enable (me[20]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (fds_audio), + .audio_b (audio_out_b), + // Special ports + .prg_dbus (prg_from_ram), + .audio_dout (fds_data), + .diskside_b (fds_diskside), + .max_diskside (max_diskside), + .fds_busy (fds_busy), + .fds_eject_btn (fds_eject), + .fds_auto_eject_en (fds_auto_eject) + ); + end +endgenerate //*****************************************************************************// // Name : Mapper 31 // @@ -2156,155 +2388,187 @@ tri0 [1:0] fds_diskside; // Games : Famicompo Pico 2014, NSF 1.0 // //*****************************************************************************// wire [5:0] exp_audioe; -// NSF nsfplayer( -// .clk (clk), -// .ce (ce), -// .enable (me[31]), -// .flags (flags), -// .prg_ain (prg_ain), -// .prg_aout_b (prg_addr_b), -// .prg_read (prg_read), -// .prg_write (prg_write), -// .prg_din (prg_din), -// .prg_dout_b (prg_dout_b), -// .prg_allow_b(prg_allow_b), -// .chr_ain (chr_ain), -// .chr_aout_b (chr_addr_b), -// .chr_read (chr_read), -// .chr_dout_b (chr_dout_b), // Special port -// .chr_allow_b(chr_allow_b), -// .vram_a10_b (vram_a10_b), -// .vram_ce_b (vram_ce_b), -// .irq_b (irq_b), -// .flags_out_b(flags_out_b), -// .audio_in (exp_audioe[5] ? ss5b_audio : -// exp_audioe[4] ? n163_audio : -// exp_audioe[3] ? mmc5_audio : -// exp_audioe[2] ? fds_audio : -// exp_audioe[1] ? vrc7_audio : -// exp_audioe[0] ? vrc6_audio : -// audio_in), -// .exp_audioe (exp_audioe), // Expansion Enabled (0x0=None, 0x1=VRC6, 0x2=VRC7, 0x4=FDS, 0x8=MMC5, 0x10=N163, 0x20=SS5B -// .audio_b (audio_out_b), -// .fds_din (fds_data) -// ); + +//was commented by agg23 +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + NSF nsfplayer( + .clk (clk), + .ce (ce), + .enable (me[31]), + .flags (flags), + .prg_ain (prg_ain), + .prg_aout_b (prg_addr_b), + .prg_read (prg_read), + .prg_write (prg_write), + .prg_din (prg_din), + .prg_dout_b (prg_dout_b), + .prg_allow_b(prg_allow_b), + .chr_ain (chr_ain), + .chr_aout_b (chr_addr_b), + .chr_read (chr_read), + .chr_dout_b (chr_dout_b), // Special port + .chr_allow_b(chr_allow_b), + .vram_a10_b (vram_a10_b), + .vram_ce_b (vram_ce_b), + .irq_b (irq_b), + .flags_out_b(flags_out_b), + .audio_in (exp_audioe[5] ? ss5b_audio : + exp_audioe[4] ? n163_audio : + exp_audioe[3] ? mmc5_audio : + exp_audioe[2] ? fds_audio : + exp_audioe[1] ? vrc7_audio : + exp_audioe[0] ? vrc6_audio : + audio_in), + .exp_audioe (exp_audioe), // Expansion Enabled (0x0=None, 0x1=VRC6, 0x2=VRC7, 0x4=FDS, 0x8=MMC5, 0x10=N163, 0x20=SS5B + .audio_b (audio_out_b), + .fds_din (fds_data) + ); + end +endgenerate wire [15:0] ss5b_audio; -SS5b_mixed snd_5bm ( - .clk(clk), - .ce(ce), - .enable(me[69] | (me[31] && exp_audioe[5])), - .wren(prg_write), - .addr_in(prg_ain), - .data_in(prg_din), - .audio_in(audio_in), - .audio_out(ss5b_audio), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[13]) -); +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + SS5b_mixed snd_5bm ( + .clk(clk), + .ce(ce), + .enable(me[69] | (me[31] && exp_audioe[5])), + .wren(prg_write), + .addr_in(prg_ain), + .data_in(prg_din), + .audio_in(audio_in), + .audio_out(ss5b_audio), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[13]) + ); + end +endgenerate wire [15:0] n163_audio; wire [7:0] n163_data; -namco163_mixed snd_n163 ( - .clk(clk), - .ce(ce), - .submapper(flags[24:21]), - .enable(me[19] | (me[31] && exp_audioe[4])), - .wren(prg_write), - .addr_in(prg_ain), - .data_in(prg_din), - .data_out(n163_data), - .audio_in(audio_in), - .audio_out(n163_audio), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[15]), - - .Savestate_MAPRAMactive (Savestate_MAPRAMactive), - .Savestate_MAPRAMAddr (Savestate_MAPRAMAddr[6:0]), - .Savestate_MAPRAMRdEn (Savestate_MAPRAMRdEn), - .Savestate_MAPRAMWrEn (Savestate_MAPRAMWrEn), - .Savestate_MAPRAMWriteData(Savestate_MAPRAMWriteData), - .Savestate_MAPRAMReadData (SaveStateRAM_wired_or[0]) -); +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + namco163_mixed snd_n163 ( + .clk(clk), + .ce(ce), + .submapper(flags[24:21]), + .enable(me[19] | (me[31] && exp_audioe[4])), + .wren(prg_write), + .addr_in(prg_ain), + .data_in(prg_din), + .data_out(n163_data), + .audio_in(audio_in), + .audio_out(n163_audio), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[15]), + + .Savestate_MAPRAMactive (Savestate_MAPRAMactive), + .Savestate_MAPRAMAddr (Savestate_MAPRAMAddr[6:0]), + .Savestate_MAPRAMRdEn (Savestate_MAPRAMRdEn), + .Savestate_MAPRAMWrEn (Savestate_MAPRAMWrEn), + .Savestate_MAPRAMWriteData(Savestate_MAPRAMWriteData), + .Savestate_MAPRAMReadData (SaveStateRAM_wired_or[0]) + ); + end +endgenerate wire [15:0] mmc5_audio; wire [7:0] mmc5_data; -mmc5_mixed snd_mmc5 ( - .clk(clk), - .ce(ce), - .enable(me[5] | (me[31] && exp_audioe[3])), - .wren(prg_write), - .rden(prg_read), - .addr_in(prg_ain), - .data_in(prg_din), - .data_out(mmc5_data), - .audio_in(audio_in), - .audio_out(mmc5_audio), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[17]) -); + +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + mmc5_mixed snd_mmc5 ( + .clk(clk), + .ce(ce), + .enable(me[5] | (me[31] && exp_audioe[3])), + .wren(prg_write), + .rden(prg_read), + .addr_in(prg_ain), + .data_in(prg_din), + .data_out(mmc5_data), + .audio_in(audio_in), + .audio_out(mmc5_audio), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[17]) + ); + end +endgenerate wire [15:0] fds_audio; wire [7:0] fds_data; -// fds_mixed snd_fds ( -// .clk(clk), -// .ce(ce), -// .enable(me[20] | (me[31] && exp_audioe[2])), -// .wren(prg_write), -// .addr_in(prg_ain), -// .data_in(prg_din), -// .data_out(fds_data), -// .audio_in(audio_in), -// .audio_out(fds_audio) -// ); +//was commented by agg23 +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + fds_mixed snd_fds ( + .clk(clk), + .ce(ce), + .enable(me[20] | (me[31] && exp_audioe[2])), + .wren(prg_write), + .addr_in(prg_ain), + .data_in(prg_din), + .data_out(fds_data), + .audio_in(audio_in), + .audio_out(fds_audio) + ); + end +endgenerate wire [15:0] vrc7_audio; -// vrc7_mixed snd_vrc7 ( -// .clk(clk), -// .ce(ce), -// .enable(me[85] | (me[31] && exp_audioe[1])), -// .wren(prg_write), -// .addr_in(prg_ain), -// .data_in(prg_din), -// .audio_in(audio_in), -// .audio_out(vrc7_audio) -// ); - +//was commented by agg23 +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + vrc7_mixed snd_vrc7 ( + .clk(clk), + .ce(ce), + .enable(me[85] | (me[31] && exp_audioe[1])), + .wren(prg_write), + .addr_in(prg_ain), + .data_in(prg_din), + .audio_in(audio_in), + .audio_out(vrc7_audio) + ); + end +endgenerate wire [15:0] vrc6_audio; -vrc6_mixed snd_vrc6 ( - .clk(clk), - .ce(ce), - .enable(me[24] | me[26] | (me[31] && exp_audioe[0])), - .wren(prg_write), - .addr_invert(me[26]), - .addr_in(prg_ain), - .data_in(prg_din), - .audio_in(audio_in), - .audio_out(vrc6_audio), - // savestates - .SaveStateBus_Din (SaveStateBus_Din ), - .SaveStateBus_Adr (SaveStateBus_Adr ), - .SaveStateBus_wren (SaveStateBus_wren), - .SaveStateBus_rst (SaveStateBus_rst ), - .SaveStateBus_load (SaveStateBus_load ), - .SaveStateBus_Dout (SaveStateBus_wired_or[11]) -); +generate + if (USE_MMAPPER_SET2 == 1'b1) begin + vrc6_mixed snd_vrc6 ( + .clk(clk), + .ce(ce), + .enable(me[24] | me[26] | (me[31] && exp_audioe[0])), + .wren(prg_write), + .addr_invert(me[26]), + .addr_in(prg_ain), + .data_in(prg_din), + .audio_in(audio_in), + .audio_out(vrc6_audio), + // savestates + .SaveStateBus_Din (SaveStateBus_Din ), + .SaveStateBus_Adr (SaveStateBus_Adr ), + .SaveStateBus_wren (SaveStateBus_wren), + .SaveStateBus_rst (SaveStateBus_rst ), + .SaveStateBus_load (SaveStateBus_load ), + .SaveStateBus_Dout (SaveStateBus_wired_or[11]) + ); + end +endgenerate wire [1023:0] me; @@ -2347,16 +2611,16 @@ localparam SAVESTATE_MODULES = 37; wire [63:0] SaveStateBus_wired_or[0:SAVESTATE_MODULES-1]; assign SaveStateBus_Dout = SaveStateBus_wired_or[ 0] | SaveStateBus_wired_or[ 1] | SaveStateBus_wired_or[ 2] | SaveStateBus_wired_or[ 3] | SaveStateBus_wired_or[ 4] | - SaveStateBus_wired_or[ 5] | SaveStateBus_wired_or[ 6] | SaveStateBus_wired_or[ 7] | SaveStateBus_wired_or[ 8] | SaveStateBus_wired_or[ 9] | - SaveStateBus_wired_or[10] | SaveStateBus_wired_or[11] | SaveStateBus_wired_or[12] | SaveStateBus_wired_or[13] | SaveStateBus_wired_or[14] | - SaveStateBus_wired_or[15] | SaveStateBus_wired_or[16] | SaveStateBus_wired_or[17] | SaveStateBus_wired_or[18] | SaveStateBus_wired_or[19] | - SaveStateBus_wired_or[20] | SaveStateBus_wired_or[21] | SaveStateBus_wired_or[22] | SaveStateBus_wired_or[23] | SaveStateBus_wired_or[24] | - SaveStateBus_wired_or[25] | SaveStateBus_wired_or[26] | SaveStateBus_wired_or[27] | SaveStateBus_wired_or[28] | SaveStateBus_wired_or[29] | - SaveStateBus_wired_or[30] | SaveStateBus_wired_or[31] | SaveStateBus_wired_or[32] | SaveStateBus_wired_or[33] | SaveStateBus_wired_or[34] | - SaveStateBus_wired_or[35] | SaveStateBus_wired_or[36]; + SaveStateBus_wired_or[ 5] | SaveStateBus_wired_or[ 6] | SaveStateBus_wired_or[ 7] | SaveStateBus_wired_or[ 8] | SaveStateBus_wired_or[ 9] | + SaveStateBus_wired_or[10] | SaveStateBus_wired_or[11] | SaveStateBus_wired_or[12] | SaveStateBus_wired_or[13] | SaveStateBus_wired_or[14] | + SaveStateBus_wired_or[15] | SaveStateBus_wired_or[16] | SaveStateBus_wired_or[17] | SaveStateBus_wired_or[18] | SaveStateBus_wired_or[19] | + SaveStateBus_wired_or[20] | SaveStateBus_wired_or[21] | SaveStateBus_wired_or[22] | SaveStateBus_wired_or[23] | SaveStateBus_wired_or[24] | + SaveStateBus_wired_or[25] | SaveStateBus_wired_or[26] | SaveStateBus_wired_or[27] | SaveStateBus_wired_or[28] | SaveStateBus_wired_or[29] | + SaveStateBus_wired_or[30] | SaveStateBus_wired_or[31] | SaveStateBus_wired_or[32] | SaveStateBus_wired_or[33] | SaveStateBus_wired_or[34] | + SaveStateBus_wired_or[35] | SaveStateBus_wired_or[36]; localparam SAVESTATERAM_MODULES = 3; -wire [7:0] SaveStateRAM_wired_or[0:SAVESTATE_MODULES-1]; +wire [7:0] SaveStateRAM_wired_or[0:SAVESTATERAM_MODULES-1]; assign Savestate_MAPRAMReadData = SaveStateRAM_wired_or[0] | SaveStateRAM_wired_or[1] | SaveStateRAM_wired_or[2]; endmodule diff --git a/rtl/mappers/FDS.sv b/rtl/mappers/FDS.sv index aeced3a..c128b9b 100644 --- a/rtl/mappers/FDS.sv +++ b/rtl/mappers/FDS.sv @@ -514,7 +514,7 @@ end wire [15:0] audio_exp_f; -IIR_filter #( +iir_filter #( .coeff_x (2.15/1.140404269e+03), .coeff_x0 (1), .coeff_x1 (0), @@ -797,4 +797,4 @@ end else if (~old_m2 & m2) begin end // if m2 end -endmodule +endmodule \ No newline at end of file diff --git a/rtl/mappers/MMC5.sv b/rtl/mappers/MMC5.sv index e0c9a20..89a9486 100644 --- a/rtl/mappers/MMC5.sv +++ b/rtl/mappers/MMC5.sv @@ -425,10 +425,11 @@ always @(posedge clk) begin end // The "in-frame" flag is cleared when 3 CPU cycles pass without a PPU read having occurred - if (ce) begin + //MMC5: fix chr_read detection with async ce (CV3 PAL) (#360) + if (~paused) begin if (chr_read) begin ppu_no_rd_read_cnt <= 0; - end else if (ppu_in_frame) begin + end else if (ce & ppu_in_frame) begin ppu_no_rd_read_cnt <= ppu_no_rd_read_cnt + 1'b1; if (ppu_no_rd_read_cnt == 2'd2) begin ppu_in_frame <= 0; @@ -782,4 +783,4 @@ eReg_SavestateV #(SSREG_INDEX_SNDMAP5, 64'h0000000000000000) iREG_SAVESTATE_MAP1 assign SaveStateBus_Dout = enable ? SaveStateBus_Dout_active : 64'h0000000000000000; -endmodule +endmodule \ No newline at end of file diff --git a/rtl/nes.v b/rtl/nes.v index 2eb9f58..3fa5e5f 100644 --- a/rtl/nes.v +++ b/rtl/nes.v @@ -93,6 +93,7 @@ module NES( input [4:0] audio_channels, // Enabled audio channels input ex_sprites, input [1:0] mask, + input dejitter_timing, // Access signals for the SDRAM. output [24:0] cpumem_addr, @@ -296,7 +297,7 @@ always @(posedge clk) begin if (|faux_pixel_cnt) faux_pixel_cnt <= faux_pixel_cnt - 1'b1; - if (((skip_pixel && ~corepause_active) || (skip_pixel_pause && corepause_active)) && (faux_pixel_cnt == 0)) begin + if ((((skip_pixel && ~corepause_active) || (skip_pixel_pause && corepause_active)) && (faux_pixel_cnt == 0)) && !dejitter_timing) begin freeze_clocks <= 1'b1; faux_pixel_cnt <= {div_ppu_n - 1'b1, 1'b0} + 1'b1; end diff --git a/rtl/nes_top.sv b/rtl/nes_top.sv index 555561b..ff3dc47 100644 --- a/rtl/nes_top.sv +++ b/rtl/nes_top.sv @@ -56,15 +56,19 @@ module nes_top ( input wire p4_dpad_down, input wire p4_dpad_left, input wire p4_dpad_right, + + //Analogizer SNAC Zapper (always on P2 port) + input wire SNAC_Zapper_Trigger, + input wire SNAC_Zapper_Light, // Settings input wire hide_overscan, input wire [1:0] mask_vid_edges, input wire allow_extra_sprites, input wire [2:0] selected_palette, - + input dejitter_timing, input wire multitap_enabled, - input wire lightgun_enabled, + input wire [1:0] lightgun_enabled, //added bit one to check for Analogizer SNAC Zapper input wire [7:0] lightgun_dpad_aim_speed, input wire [2:0] turbo_speed, @@ -219,6 +223,7 @@ module nes_top ( .cycle (cycle), .scanline (scanline), .mask (mask_vid_edges), + .dejitter_timing(dejitter_timing), // User Input .joypad_out (joypad_out), .joypad_clock (joypad_clock), @@ -366,7 +371,7 @@ module nes_top ( wire paddle_btn = 0; wire [4:0] joypad1_data = {2'b0, mic, paddle_en & paddle_btn, joypad_bits[0]}; // Upper 4 bits are other peripherals - wire [4:0] joypad2_data = {trigger, light, 2'b0, joypad_bits2[0]}; + wire [4:0] joypad2_data = {(lightgun_enabled[1] ? SNAC_Zapper_Trigger : trigger), (lightgun_enabled[1] ? SNAC_Zapper_Light : light), 2'b0, joypad_bits2[0]}; //Added check for Analogizer SNAC Zapper wire [7:0] nes_joy_A = { p1_dpad_right, @@ -418,7 +423,7 @@ module nes_top ( zapper zap ( .clk(clk_ppu_21_47), - .reset(reset_nes | ~lightgun_enabled), + .reset(reset_nes | ~lightgun_enabled[0]), .dpad_up(p1_dpad_up), .dpad_down(p1_dpad_down), .dpad_left(p1_dpad_left), @@ -852,7 +857,7 @@ module nes_top ( .load_color_index(pal_index), .emphasis(emphasis), // Zapper - .reticle(lightgun_enabled ? reticle : 2'b00), + .reticle(lightgun_enabled[0] ? reticle : 2'b00), .pal_video(pal_video), // .ce_pix(ce_pix), diff --git a/target/pocket/core.qip b/target/pocket/core.qip index 8073d44..bbef8f2 100644 --- a/target/pocket/core.qip +++ b/target/pocket/core.qip @@ -1,4 +1,4 @@ -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "core_top.v"] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "core_top.sv"] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "core_bridge_cmd.v"] set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "core_constraints.sdc"] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "data_loader.sv"] @@ -10,5 +10,4 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path set_global_assignment -name SIGNALTAP_FILE [file join $::quartus(qip_path) "stp1.stp"] set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_audio_pll.qip"] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase.qip"] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "pll_reconfig.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "nes_pll.qip"] diff --git a/target/pocket/core_constraints.sdc b/target/pocket/core_constraints.sdc index 6479252..9873d50 100644 --- a/target/pocket/core_constraints.sdc +++ b/target/pocket/core_constraints.sdc @@ -9,7 +9,8 @@ set_clock_groups -asynchronous \ -group { clk_74a } \ -group { clk_74b } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|*[0].*|divclk \ - ic|mp1|mf_pllbase_inst|altera_pll_i|*[1].*|divclk } \ + ic|mp1|mf_pllbase_inst|altera_pll_i|*[1].*|divclk \ + ic|mp1|mf_pllbase_inst|altera_pll_i|*[4].*|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|*[2].*|divclk } \ -group { ic|mp1|mf_pllbase_inst|altera_pll_i|*[3].*|divclk } \ -group { ic|audio_mixer|audio_pll|mf_audio_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \ diff --git a/target/pocket/core_top.v b/target/pocket/core_top.sv similarity index 51% rename from target/pocket/core_top.v rename to target/pocket/core_top.sv index 5125ab3..c6bd7c3 100644 --- a/target/pocket/core_top.v +++ b/target/pocket/core_top.sv @@ -6,8 +6,11 @@ `default_nettype none -module core_top ( +//Using old style scandoubler code reduces resources usage (don´t implement HQ2x) +`define USE_OLD_STYLE_SCANDOUBLER 1'b1 +module core_top +( // // physical connections // @@ -224,6 +227,14 @@ module core_top ( ); + + +parameter USE_PAL_PLL = 1'b0; +initial begin + $info("*** core_top ***"); + $info("USE_PAL_PLL %d", USE_PAL_PLL); +end + // not using the IR port, so turn off both the LED, and // disable the receive circuit to save power assign port_ir_tx = 0; @@ -234,19 +245,19 @@ module core_top ( // cart is unused, so set all level translators accordingly // directions are 0:IN, 1:OUT - assign cart_tran_bank3 = 8'hzz; - assign cart_tran_bank3_dir = 1'b0; - assign cart_tran_bank2 = 8'hzz; - assign cart_tran_bank2_dir = 1'b0; - assign cart_tran_bank1 = 8'hzz; - assign cart_tran_bank1_dir = 1'b0; - assign cart_tran_bank0 = 4'hf; - assign cart_tran_bank0_dir = 1'b1; - assign cart_tran_pin30 = 1'b0; // reset or cs2, we let the hw control it by itself - assign cart_tran_pin30_dir = 1'bz; - assign cart_pin30_pwroff_reset = 1'b0; // hardware can control this - assign cart_tran_pin31 = 1'bz; // input - assign cart_tran_pin31_dir = 1'b0; // input +// assign cart_tran_bank3 = 8'hzz; +// assign cart_tran_bank3_dir = 1'b0; +// assign cart_tran_bank2 = 8'hzz; +// assign cart_tran_bank2_dir = 1'b0; +// assign cart_tran_bank1 = 8'hzz; +// assign cart_tran_bank1_dir = 1'b0; +// assign cart_tran_bank0 = 4'hf; +// assign cart_tran_bank0_dir = 1'b1; +// assign cart_tran_pin30 = 1'b0; // reset or cs2, we let the hw control it by itself +// assign cart_tran_pin30_dir = 1'bz; +// assign cart_pin30_pwroff_reset = 1'b0; // hardware can control this +// assign cart_tran_pin31 = 1'bz; // input +// assign cart_tran_pin31_dir = 1'b0; // input // link port is input only assign port_tran_so = 1'bz; @@ -295,73 +306,84 @@ module core_top ( assign aux_scl = 1'bZ; assign vpll_feed = 1'bZ; + + localparam [7:0] ADDRESS_ANALOGIZER_CONFIG = 8'hF7; // for bridge write data, we just broadcast it to all bus devices // for bridge read data, we have to mux it // add your own devices here + wire [31:0] analogizer_bridge_rd_data; + always @(*) begin - casex (bridge_addr) - default: begin - bridge_rd_data <= 0; - end - 32'hF8xxxxxx: begin - bridge_rd_data <= cmd_bridge_rd_data; - end - endcase + casex (bridge_addr[31:24]) + default: begin bridge_rd_data <= 0; end + ADDRESS_ANALOGIZER_CONFIG: begin bridge_rd_data <= analogizer_bridge_rd_data; end + 8'hF8: begin bridge_rd_data <= cmd_bridge_rd_data; end + endcase - if (bridge_addr[31:28] == 4'h2) begin - bridge_rd_data <= sd_read_data; - end else if (bridge_addr[31:28] == 4'h4) begin - bridge_rd_data <= save_state_bridge_read_data; + if (bridge_addr[31:28] == 4'h2) begin + bridge_rd_data <= sd_read_data; + end else if (bridge_addr[31:28] == 4'h4) begin + bridge_rd_data <= save_state_bridge_read_data; + end end - end + wire only_interact_addr = ~(|bridge_addr[31:12]); //true if all zero + always @(posedge clk_74a) begin if (reset_delay > 0) begin reset_delay <= reset_delay - 1; end - if (bridge_wr) begin - casex (bridge_addr) - 32'h050: begin + if (bridge_wr && only_interact_addr) begin + casex (bridge_addr[11:0]) + 12'h050: begin reset_delay <= 32'h100000; end - // 32'h054: begin - // region <= bridge_wr_data[1:0]; - // end - 32'h200: begin + 12'h31C: begin + //reset the core if Analogizer was enabled, this resets also Analogizer and ensures proper initialization + // if (!analogizer_ena && bridge_wr_data[0]) reset_delay <= 32'h100000; + analogizer_ena <= bridge_wr_data[0]; //Global switch for Analogizer enable/disable + end + 12'h330: begin + region <= bridge_wr_data[1:0]; //When Chip32 loader writes the region to the Core + end + 12'h32C: begin + video_dejitter <= bridge_wr_data[0]; + end + 12'h200: begin hide_overscan <= bridge_wr_data[0]; end - 32'h204: begin + 12'h204: begin mask_vid_edges <= bridge_wr_data[1:0]; end - 32'h208: begin + 12'h208: begin allow_extra_sprites <= bridge_wr_data[0]; end - 32'h20C: begin + 12'h20C: begin selected_palette <= bridge_wr_data[2:0]; end - 32'h210: begin + 12'h210: begin square_pixels <= bridge_wr_data[0]; end - 32'h300: begin + 12'h300: begin multitap_enabled <= bridge_wr_data[0]; end - 32'h304: begin - lightgun_enabled <= bridge_wr_data[0]; + 12'h304: begin + lightgun_enabled <= bridge_wr_data[1:0]; //Modified to add support for Analogizer SNAC Zapper lightgun end - 32'h308: begin + 12'h308: begin lightgun_dpad_aim_speed <= bridge_wr_data[7:0]; end - 32'h30C: begin + 12'h30C: begin swap_controllers <= bridge_wr_data[0]; end - 32'h310: begin + 12'h310: begin turbo_speed <= bridge_wr_data[2:0]; end endcase end end - + // // host/target command handler // @@ -627,7 +649,7 @@ module core_top ( wire [31:0] cont1_joy_s; synch_3 #( - .WIDTH(32) + .WIDTH(16) ) cont1_s ( cont1_key, cont1_key_s, @@ -635,7 +657,7 @@ module core_top ( ); synch_3 #( - .WIDTH(32) + .WIDTH(16) ) cont2_s ( cont2_key, cont2_key_s, @@ -643,7 +665,7 @@ module core_top ( ); synch_3 #( - .WIDTH(32) + .WIDTH(16) ) cont3_s ( cont3_key, cont3_key_s, @@ -651,7 +673,7 @@ module core_top ( ); synch_3 #( - .WIDTH(32) + .WIDTH(16) ) cont4_s ( cont4_key, cont4_key_s, @@ -667,81 +689,376 @@ module core_top ( ); // Settings + //reg [2:0] system_type = 0; + reg analogizer_ena = 0; reg [1:0] region = 0; + reg video_dejitter = 0; reg hide_overscan = 0; reg [1:0] mask_vid_edges = 0; reg square_pixels = 0; - reg allow_extra_sprites = 0; - reg [2:0] selected_palette = 0; - wire external_reset = reset_delay > 0; + reg allow_extra_sprites = 0; + reg [2:0] selected_palette = 0; + wire external_reset = reset_delay > 0; - reg multitap_enabled = 0; - reg lightgun_enabled = 0; - reg [7:0] lightgun_dpad_aim_speed = 0; + reg multitap_enabled = 0; + reg [1:0] lightgun_enabled = 0; + reg [7:0] lightgun_dpad_aim_speed = 0; - reg [2:0] turbo_speed = 0; - reg swap_controllers = 0; + reg [2:0] turbo_speed = 0; + reg swap_controllers = 0; - wire [1:0] region_s; + // wire [1:0] region_s; + // wire video_dejitter_s; - wire hide_overscan_s; - wire [1:0] mask_vid_edges_s; - wire square_pixels_s; - wire allow_extra_sprites_s; - wire [2:0] selected_palette_s; + // wire hide_overscan_s; + // wire [1:0] mask_vid_edges_s; + // wire square_pixels_s; + // wire allow_extra_sprites_s; + // wire [2:0] selected_palette_s; wire external_reset_s; + wire analogizer_ena_s; + + // wire multitap_enabled_s; + // wire [1:0] lightgun_enabled_s; + // wire [7:0] lightgun_dpad_aim_speed_s; + + // wire [2:0] turbo_speed_s; + // wire swap_controllers_s; + + // synch_3 #( + // .WIDTH(27) + // ) settings_s ( + // { + // region, // 2 + // video_dejitter, // 1 + // hide_overscan, // 1 + // mask_vid_edges, // 2 + // square_pixels, // 1 + // allow_extra_sprites, // 1 + // selected_palette, // 3 + // external_reset, // 1 + // multitap_enabled, // 1 + // lightgun_enabled, // 2 + // lightgun_dpad_aim_speed, // 8 + // turbo_speed, // 3 + // swap_controllers // 1 + // }, + // { + // region_s, + // video_dejitter_s, + // hide_overscan_s, + // mask_vid_edges_s, + // square_pixels_s, + // allow_extra_sprites_s, + // selected_palette_s, + // external_reset_s, + // multitap_enabled_s, + // lightgun_enabled_s, + // lightgun_dpad_aim_speed_s, + // turbo_speed_s, + // swap_controllers_s + // }, + // clk_ppu_21_47 + // ); - wire multitap_enabled_s; - wire lightgun_enabled_s; - wire [7:0] lightgun_dpad_aim_speed_s; + //synch_3 #(.WIDTH(1)) settings_s (external_reset, external_reset_s,clk_ppu_21_47); - wire [2:0] turbo_speed_s; - wire swap_controllers_s; - synch_3 #( - .WIDTH(24) - ) settings_s ( - { - region, - hide_overscan, - mask_vid_edges, - square_pixels, - allow_extra_sprites, - selected_palette, - external_reset, - multitap_enabled, - lightgun_enabled, - lightgun_dpad_aim_speed, - turbo_speed, - swap_controllers - }, - { - region_s, - hide_overscan_s, - mask_vid_edges_s, - square_pixels_s, - allow_extra_sprites_s, - selected_palette_s, - external_reset_s, - multitap_enabled_s, - lightgun_enabled_s, - lightgun_dpad_aim_speed_s, - turbo_speed_s, - swap_controllers_s - }, - clk_ppu_21_47 - ); + //synchronize signals with clk_ppu_21_47 clock + reg [1:0] ext_reset_r = 0; + reg [1:0] analogizer_ena_r = 0; + always @(posedge clk_ppu_21_47) begin + ext_reset_r <= {ext_reset_r[0],external_reset}; + analogizer_ena_r <= {analogizer_ena_r[0],analogizer_ena}; + end + assign external_reset_s = ext_reset_r[1]; + assign analogizer_ena_s = analogizer_ena_r[1]; reg [1:0] prev_region = 0; always @(posedge clk_ppu_21_47) begin - prev_region <= region_s; + prev_region <= region; end reg [31:0] reset_delay = 0; - wire hide_overscan_with_region = hide_overscan_s && region_s == 2'b0; + wire hide_overscan_with_region = hide_overscan && region == 2'b0; + +/*[ANALOGIZER_HOOK_BEGIN]*/ +//reg analogizer_ena; +wire [4:0] snac_game_cont_type; +wire [3:0] snac_cont_assignment; +wire pocket_blank_screen; +//reg analogizer_osd_out; + + //create aditional switch to blank Pocket screen. + wire [23:0] video_rgb_pocket; + //If Analogizer is disabled globally then show the video output on the Pocket screen + assign video_rgb_pocket = (pocket_blank_screen && !analogizer_ena_s) ? 24'h000000: video_rgb_nes; + +//switch between Analogizer SNAC and Pocket Controls for P1-P4 (P3,P4 when uses PCEngine Multitap) + wire [15:0] p1_btn, p2_btn, p3_btn, p4_btn; + wire [31:0] p1_joy, p2_joy; + reg [31:0] p1_joystick, p2_joystick; + reg [15:0] p1_controls, p2_controls, p3_controls, p4_controls; + +wire snac_is_analog = (snac_game_cont_type == 5'h12) || (snac_game_cont_type == 5'h13); +wire [31:0] neutral_joystick = 32'h80808080; + +always @(posedge clk_ppu_21_47) begin + reg [31:0] p1_pocket_btn, p1_pocket_joy; + reg [31:0] p2_pocket_btn, p2_pocket_joy; + reg [31:0] p3_pocket_btn; + reg [31:0] p4_pocket_btn; + + //If Analogizer is disabled globally then use Pocket default controllers + if((snac_game_cont_type == 5'h0) || !analogizer_ena_s) begin //SNAC is disabled + p1_controls <= cont1_key_s; + p1_joystick <= cont1_joy_s; + p2_controls <= cont2_key_s; + p3_controls <= cont3_key_s; + p4_controls <= cont4_key_s; + end + else begin + p1_pocket_btn <= snac_is_analog ? {{4'h3},{12'h0},p1_btn} : {{4'h2},{12'h0},p1_btn}; + p1_pocket_joy <= snac_is_analog ? p1_joy : neutral_joystick; + p2_pocket_btn <= snac_is_analog ? {{4'h3},{12'h0},p2_btn} : {{4'h2},{12'h0},p2_btn}; + p2_pocket_joy <= snac_is_analog ? p2_joy : neutral_joystick; + p3_pocket_btn <= snac_is_analog ? {{4'h3},{12'h0},p3_btn} : {{4'h2},{12'h0},p3_btn}; + p4_pocket_btn <= snac_is_analog ? {{4'h3},{12'h0},p4_btn} : {{4'h2},{12'h0},p4_btn}; + + case(snac_cont_assignment[2:0]) + 3'h0: begin //SNAC P1 -> Pocket P1 + //0x13 PSX SNAC Analog -> 0x3 See: https://www.analogue.co/developer/docs/bus-communication#PAD + //0xXX another SANC -> 0x2 + p1_controls <= p1_pocket_btn; + p1_joystick <= p1_pocket_joy; //check for PSX Analog SNAC or return neutral position data + p2_controls <= cont2_key_s; + p3_controls <= cont3_key_s; + p4_controls <= cont4_key_s; + + end + 3'h1: begin //SNAC P1 -> Pocket P2 + p1_controls <= cont1_key_s; + p1_joystick <= cont1_joy_s; + p2_controls <= p1_pocket_btn; + p3_controls <= cont3_key_s; + p4_controls <= cont4_key_s; + end + 3'h2: begin //SNAC P1 -> Pocket P1, SNAC P2 -> Pocket P2 + p1_controls <= p1_pocket_btn; + p1_joystick <= p1_pocket_joy; //check for PSX Analog SNAC or return neutral position data + p2_controls <= p2_pocket_btn; + p3_controls <= cont3_key_s; + p4_controls <= cont4_key_s; + end + 3'h3: begin //SNAC P1 -> Pocket P2, SNAC P2 -> Pocket P1 + p1_controls <= p2_pocket_btn; + p1_joystick <= p2_pocket_joy; //check for PSX Analog SNAC or return neutral position data + p2_controls <= p1_pocket_btn; + p3_controls <= cont3_key_s; + p4_controls <= cont4_key_s; + end + 3'h4: begin //SNAC P1-P2 -> Pocket P3-P4 + p1_controls <= cont1_key_s; + p1_joystick <= cont1_joy_s; + p2_controls <= cont2_key_s; + p3_controls <= p1_pocket_btn; + p4_controls <= p2_pocket_btn; + end + 3'h5: begin //SNAC P1-P4 -> Pocket P1-P4 + p1_controls <= p1_pocket_btn; + p1_joystick <= p1_pocket_joy; //check for PSX Analog SNAC or return neutral position data + p2_controls <= p2_pocket_btn; + p3_controls <= p3_pocket_btn; + p4_controls <= p4_pocket_btn; + end + default: begin + p1_controls <= cont1_key_s; + p1_joystick <= cont1_joy_s; + p2_controls <= cont2_key_s; + p3_controls <= cont3_key_s; + p4_controls <= cont4_key_s; + end + endcase + end + end + +wire SYNC = ~^{video_hs_nes, video_vs_nes}; + +//*** Analogizer Interface V1.0 *** +//reg analogizer_ena; +reg [3:0] analog_video_type; +reg [4:0] game_cont_type; + +// Video Y/C Encoder settings +// Follows the Mike Simone Y/C encoder settings: +// https://github.com/MikeS11/MiSTerFPGA_YC_Encoder +// SET PAL and NTSC TIMING and pass through status bits. ** YC must be enabled in the qsf file ** +// wire [39:0] CHROMA_PHASE_INC; +// wire PALFLAG; + +// parameter NTSC_REF = 3.579545; +// parameter PAL_REF = 4.43361875; + +// // Parameters to be modifed +// parameter CLK_VIDEO_NTSC = 42.954496; // Must be filled E.g XX.X Hz - CLK_VIDEO +// parameter CLK_VIDEO_PAL = 42.562736; // Must be filled E.g XX.X Hz - CLK_VIDEO + +//PAL CLOCK FREQUENCY SHOULD BE 42.56274 +localparam [39:0] NTSC_PHASE_INC = 40'd91626062837; //d91_625_958_315; //d91_625_968_981; // ((NTSC_REF**2^40) / CLK_VIDEO_NTSC) - SNES Example; +localparam [39:0] PAL_PHASE_INC = 40'd114532461227; //PAL +// assign CHROMA_PHASE_INC = PALFLAG ? PAL_PHASE_INC : NTSC_PHASE_INC; +// assign PALFLAG = (analogizer_video_type == 4'h4); + +//42_954_496 NTSC +//42_562_736 PAL + +generate + if (USE_PAL_PLL == 1'b0) begin + openFPGA_Pocket_Analogizer #(.MASTER_CLK_FREQ(42_954_496), .LINE_LENGTH(260), + .ADDRESS_ANALOGIZER_CONFIG(ADDRESS_ANALOGIZER_CONFIG), + .USE_OLD_STYLE_SVGA_SCANDOUBLER(`USE_OLD_STYLE_SCANDOUBLER)) + analogizer ( + .clk_74a(clk_74a), + .i_clk(clk_analogizer), + .i_rst(external_reset_s), //i_rst is active high + //Enable Analogizer (global setting) + .i_ena(analogizer_ena_s), + + //Video interface + .video_clk(clk_analogizer), + .R(video_rgb_nes[23:16]), + .G(video_rgb_nes[15:8]), + .B(video_rgb_nes[7:0]), + .Hblank(h_blank), + .Vblank(v_blank), + .BLANKn(de), + .Hsync(video_hs_nes), //composite SYNC on HSync. + .Vsync(video_vs_nes), + .Csync(SYNC), + + //openFPGA Bridge interface + .bridge_endian_little(bridge_endian_little), + .bridge_addr(bridge_addr), + .bridge_rd(bridge_rd), + .analogizer_bridge_rd_data(analogizer_bridge_rd_data), + .bridge_wr(bridge_wr), + .bridge_wr_data(bridge_wr_data), + + //Analogizer settings + .snac_game_cont_type_out(snac_game_cont_type), + .snac_cont_assignment_out(snac_cont_assignment), + .analogizer_video_type_out(), + .SC_fx_out(), + .pocket_blank_screen_out(pocket_blank_screen), + .analogizer_osd_out(), + + //Video Y/C Encoder interface + .CHROMA_PHASE_INC(NTSC_PHASE_INC), + .PALFLAG(1'b0), + //Video SVGA Scandoubler interface + .ce_pix(clk_video_5_37), + .scandoubler(1'b1), //logic for disable/enable the scandoubler + //SNAC interface + .p1_btn_state(p1_btn), + .p1_joy_state(p1_joy), + .p2_btn_state(p2_btn), + .p2_joy_state(p2_joy), + .p3_btn_state(p3_btn), + .p4_btn_state(p4_btn), + //Pocket Analogizer IO interface to the Pocket cartridge port + .cart_tran_bank2(cart_tran_bank2), + .cart_tran_bank2_dir(cart_tran_bank2_dir), + .cart_tran_bank3(cart_tran_bank3), + .cart_tran_bank3_dir(cart_tran_bank3_dir), + .cart_tran_bank1(cart_tran_bank1), + .cart_tran_bank1_dir(cart_tran_bank1_dir), + .cart_tran_bank0(cart_tran_bank0), + .cart_tran_bank0_dir(cart_tran_bank0_dir), + .cart_tran_pin30(cart_tran_pin30), + .cart_tran_pin30_dir(cart_tran_pin30_dir), + .cart_pin30_pwroff_reset(cart_pin30_pwroff_reset), + .cart_tran_pin31(cart_tran_pin31), + .cart_tran_pin31_dir(cart_tran_pin31_dir), + //debug + .o_stb() + ); + end + else begin + openFPGA_Pocket_Analogizer #(.MASTER_CLK_FREQ(42_562_736), .LINE_LENGTH(260), + .ADDRESS_ANALOGIZER_CONFIG(ADDRESS_ANALOGIZER_CONFIG), + .USE_OLD_STYLE_SVGA_SCANDOUBLER(`USE_OLD_STYLE_SCANDOUBLER)) + analogizer ( + .clk_74a(clk_74a), + .i_clk(clk_analogizer), + .i_rst(external_reset_s), //i_rst is active high + + //Enable Analogizer (global setting) + .i_ena(analogizer_ena_s), + + //Video interface + .video_clk(clk_analogizer), + .R(video_rgb_nes[23:16]), + .G(video_rgb_nes[15:8]), + .B(video_rgb_nes[7:0]), + .Hblank(h_blank), + .Vblank(v_blank), + .BLANKn(de), + .Hsync(video_hs_nes), //composite SYNC on HSync. + .Vsync(video_vs_nes), + .Csync(SYNC), + + //openFPGA Bridge interface + .bridge_endian_little(bridge_endian_little), + .bridge_addr(bridge_addr), + .bridge_rd(bridge_rd), + .analogizer_bridge_rd_data(analogizer_bridge_rd_data), + .bridge_wr(bridge_wr), + .bridge_wr_data(bridge_wr_data), + + //Analogizer settings + .snac_game_cont_type_out(snac_game_cont_type), + .snac_cont_assignment_out(snac_cont_assignment), + .analogizer_video_type_out(), + .SC_fx_out(), + .pocket_blank_screen_out(pocket_blank_screen), + .analogizer_osd_out(), + + //Video Y/C Encoder interface + .CHROMA_PHASE_INC(PAL_PHASE_INC), + .PALFLAG(1'b1), + //Video SVGA Scandoubler interface + .ce_pix(clk_video_5_37), + .scandoubler(1'b1), //logic for disable/enable the scandoubler + //SNAC interface + .p1_btn_state(p1_btn), + .p1_joy_state(p1_joy), + .p2_btn_state(p2_btn), + .p2_joy_state(p2_joy), + .p3_btn_state(p3_btn), + .p4_btn_state(p4_btn), + //Pocket Analogizer IO interface to the Pocket cartridge port + .cart_tran_bank2(cart_tran_bank2), + .cart_tran_bank2_dir(cart_tran_bank2_dir), + .cart_tran_bank3(cart_tran_bank3), + .cart_tran_bank3_dir(cart_tran_bank3_dir), + .cart_tran_bank1(cart_tran_bank1), + .cart_tran_bank1_dir(cart_tran_bank1_dir), + .cart_tran_bank0(cart_tran_bank0), + .cart_tran_bank0_dir(cart_tran_bank0_dir), + .cart_tran_pin30(cart_tran_pin30), + .cart_tran_pin30_dir(cart_tran_pin30_dir), + .cart_pin30_pwroff_reset(cart_pin30_pwroff_reset), + .cart_tran_pin31(cart_tran_pin31), + .cart_tran_pin31_dir(cart_tran_pin31_dir), + //debug + .o_stb() + ); + end +endgenerate +/*[ANALOGIZER_HOOK_END]*/ nes_top nes ( .clk_74a(clk_74a), @@ -749,72 +1066,77 @@ module core_top ( .clk_85_9(clk_85_9), .clock_locked(pll_core_locked), - .sys_type(region_s), + .sys_type(region), // Control // Region changed, reset - .external_reset(external_reset_s || prev_region != region_s || pll_reset), + .external_reset(external_reset_s || prev_region != region || pll_reset), // Input - .p1_button_a(cont1_key_s[4]), - .p1_button_b(cont1_key_s[5]), - .p1_button_a_turbo(cont1_key_s[6]), - .p1_button_b_turbo(cont1_key_s[7]), - .p1_button_start(cont1_key_s[15]), - .p1_button_select(cont1_key_s[14]), - .p1_dpad_up(cont1_key_s[0]), - .p1_dpad_down(cont1_key_s[1]), - .p1_dpad_left(cont1_key_s[2]), - .p1_dpad_right(cont1_key_s[3]), - - .p1_lstick_x(cont1_joy_s[7:0]), - .p1_lstick_y(cont1_joy_s[15:8]), - - .p2_button_a(cont2_key_s[4]), - .p2_button_b(cont2_key_s[5]), - .p2_button_a_turbo(cont2_key_s[6]), - .p2_button_b_turbo(cont2_key_s[7]), - .p2_button_start(cont2_key_s[15]), - .p2_button_select(cont2_key_s[14]), - .p2_dpad_up(cont2_key_s[0]), - .p2_dpad_down(cont2_key_s[1]), - .p2_dpad_left(cont2_key_s[2]), - .p2_dpad_right(cont2_key_s[3]), - - .p3_button_a(cont3_key_s[4]), - .p3_button_b(cont3_key_s[5]), - .p3_button_a_turbo(cont3_key_s[6]), - .p3_button_b_turbo(cont3_key_s[7]), - .p3_button_start(cont3_key_s[15]), - .p3_button_select(cont3_key_s[14]), - .p3_dpad_up(cont3_key_s[0]), - .p3_dpad_down(cont3_key_s[1]), - .p3_dpad_left(cont3_key_s[2]), - .p3_dpad_right(cont3_key_s[3]), - - .p4_button_a(cont4_key_s[4]), - .p4_button_b(cont4_key_s[5]), - .p4_button_a_turbo(cont4_key_s[6]), - .p4_button_b_turbo(cont4_key_s[7]), - .p4_button_start(cont4_key_s[15]), - .p4_button_select(cont4_key_s[14]), - .p4_dpad_up(cont4_key_s[0]), - .p4_dpad_down(cont4_key_s[1]), - .p4_dpad_left(cont4_key_s[2]), - .p4_dpad_right(cont4_key_s[3]), + .p1_button_a(p1_controls[4]), + .p1_button_b(p1_controls[5]), + .p1_button_a_turbo(p1_controls[6]), + .p1_button_b_turbo(p1_controls[7]), + .p1_button_start(p1_controls[15]), + .p1_button_select(p1_controls[14]), + .p1_dpad_up(p1_controls[0]), + .p1_dpad_down(p1_controls[1]), + .p1_dpad_left(p1_controls[2]), + .p1_dpad_right(p1_controls[3]), + + .p1_lstick_x(p1_joystick[7:0]), + .p1_lstick_y(p1_joystick[15:8]), + + .p2_button_a(p2_controls[4]), + .p2_button_b(p2_controls[5]), + .p2_button_a_turbo(p2_controls[6]), + .p2_button_b_turbo(p2_controls[7]), + .p2_button_start(p2_controls[15]), + .p2_button_select(p2_controls[14]), + .p2_dpad_up(p2_controls[0]), + .p2_dpad_down(p2_controls[1]), + .p2_dpad_left(p2_controls[2]), + .p2_dpad_right(p2_controls[3]), + + .p3_button_a(p3_controls[4]), + .p3_button_b(p3_controls[5]), + .p3_button_a_turbo(p3_controls[6]), + .p3_button_b_turbo(p3_controls[7]), + .p3_button_start(p3_controls[15]), + .p3_button_select(p3_controls[14]), + .p3_dpad_up(p3_controls[0]), + .p3_dpad_down(p3_controls[1]), + .p3_dpad_left(p3_controls[2]), + .p3_dpad_right(p3_controls[3]), + + .p4_button_a(p4_controls[4]), + .p4_button_b(p4_controls[5]), + .p4_button_a_turbo(p4_controls[6]), + .p4_button_b_turbo(p4_controls[7]), + .p4_button_start(p4_controls[15]), + .p4_button_select(p4_controls[14]), + .p4_dpad_up(p4_controls[0]), + .p4_dpad_down(p4_controls[1]), + .p4_dpad_left(p4_controls[2]), + .p4_dpad_right(p4_controls[3]), // Settings - .hide_overscan(hide_overscan_with_region), - .mask_vid_edges(mask_vid_edges_s), - .allow_extra_sprites(allow_extra_sprites_s), - .selected_palette(selected_palette_s), + .hide_overscan(hide_overscan), //Don't Hide overscan wire hide_overscan = status[4] && ~pal_video; + .mask_vid_edges(mask_vid_edges), + .allow_extra_sprites(allow_extra_sprites), + .selected_palette(selected_palette), + .dejitter_timing(video_dejitter), - .multitap_enabled(multitap_enabled_s), - .lightgun_enabled(lightgun_enabled_s), - .lightgun_dpad_aim_speed(lightgun_dpad_aim_speed_s), + .multitap_enabled(multitap_enabled), + .lightgun_enabled(lightgun_enabled), + .lightgun_dpad_aim_speed(lightgun_dpad_aim_speed), - .turbo_speed(turbo_speed_s), - .swap_controllers(swap_controllers_s), + //SNAC Zapper inputs from P2 port + .SNAC_Zapper_Trigger(p2_controls[7]), //added zapper trigger to Y + .SNAC_Zapper_Light(p2_controls[6]), //added zapper light to X + + .turbo_speed(turbo_speed), + .swap_controllers(swap_controllers), // APF .ioctl_wr(ioctl_wr), @@ -872,7 +1194,8 @@ module core_top ( ); // Video - + // wire ce_pix; + // wire ce_pix90; wire h_blank; wire v_blank; wire video_hs_nes; @@ -897,45 +1220,43 @@ module core_top ( reg de_prev; wire de = ~(h_blank || v_blank); - wire [23:0] video_slot_rgb = {9'b0, hide_overscan_with_region, square_pixels_s, 10'b0, 3'b0}; + wire [23:0] video_slot_rgb = {9'b0, hide_overscan_with_region, square_pixels, 10'b0, 3'b0}; always @(posedge clk_video_5_37) begin video_hs_reg <= 0; video_de_reg <= 0; video_rgb_reg <= 24'h0; - if (de) begin - video_de_reg <= 1; - - video_rgb_reg <= video_rgb_nes; - end else if (de_prev && ~de) begin - video_rgb_reg <= video_slot_rgb; - end + if (de) begin + video_de_reg <= 1; + //video_rgb_reg <= video_rgb_nes; + video_rgb_reg <= video_rgb_pocket; + end else if (de_prev && ~de) begin + video_rgb_reg <= video_slot_rgb; + end - if (hs_delay > 0) begin - hs_delay <= hs_delay - 1; - end + if (hs_delay > 0) begin + hs_delay <= hs_delay - 1; + end - if (hs_delay == 1) begin - video_hs_reg <= 1; - end + if (hs_delay == 1) begin + video_hs_reg <= 1; + end - if (~hs_prev && video_hs_nes) begin - // HSync went high. Delay by 3 cycles to prevent overlapping with VSync - hs_delay <= 7; - end + if (~hs_prev && video_hs_nes) begin + // HSync went high. Delay by 3 cycles to prevent overlapping with VSync + hs_delay <= 7; + end - // Set VSync to be high for a single cycle on the rising edge of the VSync coming out of the core - video_vs_reg <= ~vs_prev && video_vs_nes; - hs_prev <= video_hs_nes; - vs_prev <= video_vs_nes; - de_prev <= de; + // Set VSync to be high for a single cycle on the rising edge of the VSync coming out of the core + video_vs_reg <= ~vs_prev && video_vs_nes; + hs_prev <= video_hs_nes; + vs_prev <= video_vs_nes; + de_prev <= de; end // Sound - wire [15:0] audio; - reg [15:0] audio_buffer = 0; // Buffer audio to have better fitting on audio route @@ -967,18 +1288,23 @@ module core_top ( /////////////////////////////////////////////// wire clk_85_9; - wire clk_ppu_21_47; - wire clk_video_5_37; + wire clk_ppu_21_47; //26.60 for PAL + wire clk_video_5_37; //5.32 fof PAL wire clk_video_5_37_90deg; + wire clk_analogizer; //42_954_496 // - // wire [63:0] reconfig_to_pll; - // wire [63:0] reconfig_from_pll; +// wire [63:0] reconfig_to_pll; +// wire [63:0] reconfig_from_pll; wire pll_core_locked; reg pll_reset = 0; - mf_pllbase mp1 ( + // Select the correct PLL settings in nes_pll_01.v with parameter USE_PAL_PLL. + // Using two different pll is not used at the end because the fitter gives + // different results (the core don't fit using the second pll) based on the PLL + // used, PLL locations affects route resources avalaibility? + nes_pll mp1 ( .refclk(clk_74a), .rst (pll_reset), // .rst(0), @@ -987,128 +1313,7 @@ module core_top ( .outclk_1(clk_ppu_21_47), .outclk_2(clk_video_5_37), .outclk_3(clk_video_5_37_90deg), - - // .reconfig_to_pll (reconfig_to_pll), - // .reconfig_from_pll(reconfig_from_pll), - + .outclk_4(clk_analogizer), //42.954496MHz .locked(pll_core_locked) ); - - // See https://github.com/agg23/openfpga-NES/issues/26 - - // wire cfg_waitrequest; - // reg cfg_write; - // reg [ 5:0] cfg_address; - // reg [31:0] cfg_data; - - // pll_reconfig pll_reconfig ( - // .mgmt_clk(clk_74a), - // .mgmt_reset(0), - // .mgmt_waitrequest(cfg_waitrequest), - // .mgmt_read(0), - // .mgmt_readdata(), - // .mgmt_write(cfg_write), - // .mgmt_address(cfg_address), - // .mgmt_writedata(cfg_data), - // .reconfig_to_pll(reconfig_to_pll), - // .reconfig_from_pll(reconfig_from_pll) - // ); - - // wire pal = region != 0; - - // reg prev_pal = 0; - // reg write_pal = 0; - - // reg [3:0] state = 0; - - // reg prev_pll_core_locked = 0; - // reg [19:0] pll_reset_delay = 0; - - // always @(posedge clk_74a) begin - // prev_pal <= pal; - // prev_pll_core_locked <= pll_core_locked; - - // cfg_write <= 0; - // if (prev_pal != pal) begin - // state <= 1; - // write_pal <= pal; - // end - - // if (~pll_core_locked && prev_pll_core_locked) begin - // pll_reset_delay <= 20'hF_FFFF; - // end - - // if (pll_reset_delay == 20'hFFFF) begin - // pll_reset <= 1; - // end else if (pll_reset_delay == 20'h0) begin - // pll_reset <= 0; - // end - - // if (pll_reset_delay > 20'h0) begin - // pll_reset_delay <= pll_reset_delay - 20'h1; - // end - - // if (!cfg_waitrequest) begin - // if (state) state <= state + 1'd1; - // case (state) - // 1: begin - // cfg_address <= 0; - // cfg_data <= 0; - // cfg_write <= 1; - // end - // 3: begin - // // Set fractional division - // // Config addresses come from https://www.intel.com/content/www/us/en/docs/programmable/683640/current/fractional-pll-dynamic-reconfiguration.html - // cfg_address <= 7; - // // NTSC: 425907062 - // // Mem: 85.908992 MHz - // // Main: 21.477248 MHz - // // Vid: 5.369312 MHz - // // PAL: 737738000 - // // Mem: 85.125472 MHz - // // Main: 21.281368 MHz - // // Vid: 5.320342 MHz - // cfg_data <= write_pal ? 737738000 : 425907062; - // cfg_write <= 1; - // end - // 5: begin - // // Set counter C0 - // cfg_address <= 'h5; - // cfg_data <= write_pal ? 32'h000404 : 32'h020403; - // cfg_write <= 1; - // end - // 7: begin - // // Set counter C1 - // cfg_address <= 'h5; - // cfg_data <= write_pal ? 32'h041010 : 32'h040E0E; - // cfg_write <= 1; - // end - // 9: begin - // // Set counter C2 - // cfg_address <= 'h5; - // cfg_data <= write_pal ? 32'h084040 : 32'h083838; - // cfg_write <= 1; - // end - // 11: begin - // // Set counter C3 - // cfg_address <= 'h5; - // cfg_data <= write_pal ? 32'h0C4040 : 32'h0C3838; - // cfg_write <= 1; - // end - // 13: begin - // // Set counter M - // cfg_address <= 'h4; - // cfg_data <= write_pal ? 32'h20504 : 32'h00404; - // cfg_write <= 1; - // end - // 15: begin - // // Begin fractional PLL reconfig - // cfg_address <= 2; - // cfg_data <= 0; - // cfg_write <= 1; - // end - // endcase - // end - // end - endmodule diff --git a/target/pocket/mf_pllbase.qip b/target/pocket/mf_pllbase.qip deleted file mode 100644 index 7d6253c..0000000 --- a/target/pocket/mf_pllbase.qip +++ /dev/null @@ -1,337 +0,0 @@ -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_VERSION "21.1" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "mf_pllbase" -name MISC_FILE [file join $::quartus(qip_path) "mf_pllbase.cmp"] -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_QSYS_MODE "UNKNOWN" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZQ==" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MjEuMQ==" -set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZV8wMDAy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MjEuMQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NzQuMjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NzQuMjUgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::ODUuOTA4OTky::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjEuNDc3MjQ4::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Mjg=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NS4zNjkzMTI=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTEy::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::NS4zNjkzMTI=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MTEy::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::OTA=::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::OTAuMA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::ODUuOTA4OTkyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjEuNDc3MjQ4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NS4zNjkzMTIgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::NS4zNjkzMTIgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::NDY1NjEgcHM=::cGhhc2Vfc2hpZnQz" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw0LDMsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxNCwxNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1Niw1NiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1Niw1NiwyOSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMSwzMCwyMDAwLDYwMS4zNjI5NDMgTUh6LDQyNTkwNzA2MixnY2xrLGdsYixmYl8xLHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" - -set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase.v"] -set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.v"] -set_global_assignment -library "mf_pllbase" -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.qip"] - -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_VERSION "21.1" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" diff --git a/target/pocket/mf_pllbase/mf_pllbase_0002.qip b/target/pocket/mf_pllbase/mf_pllbase_0002.qip deleted file mode 100644 index fa37e63..0000000 --- a/target/pocket/mf_pllbase/mf_pllbase_0002.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET ON -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" diff --git a/target/pocket/mf_pllbase/mf_pllbase_0002.v b/target/pocket/mf_pllbase/mf_pllbase_0002.v deleted file mode 100644 index 13a1686..0000000 --- a/target/pocket/mf_pllbase/mf_pllbase_0002.v +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns/10ps -module mf_pllbase_0002( - - // interface 'refclk' - input wire refclk, - - // interface 'reset' - input wire rst, - - // interface 'outclk0' - output wire outclk_0, - - // interface 'outclk1' - output wire outclk_1, - - // interface 'outclk2' - output wire outclk_2, - - // interface 'outclk3' - output wire outclk_3, - - // interface 'locked' - output wire locked -); - - altera_pll #( - .fractional_vco_multiplier("true"), - .reference_clock_frequency("74.25 MHz"), - .operation_mode("normal"), - .number_of_clocks(4), - .output_clock_frequency0("85.908992 MHz"), - .phase_shift0("0 ps"), - .duty_cycle0(50), - .output_clock_frequency1("21.477248 MHz"), - .phase_shift1("0 ps"), - .duty_cycle1(50), - .output_clock_frequency2("5.369312 MHz"), - .phase_shift2("0 ps"), - .duty_cycle2(50), - .output_clock_frequency3("5.369312 MHz"), - .phase_shift3("46561 ps"), - .duty_cycle3(50), - .output_clock_frequency4("0 MHz"), - .phase_shift4("0 ps"), - .duty_cycle4(50), - .output_clock_frequency5("0 MHz"), - .phase_shift5("0 ps"), - .duty_cycle5(50), - .output_clock_frequency6("0 MHz"), - .phase_shift6("0 ps"), - .duty_cycle6(50), - .output_clock_frequency7("0 MHz"), - .phase_shift7("0 ps"), - .duty_cycle7(50), - .output_clock_frequency8("0 MHz"), - .phase_shift8("0 ps"), - .duty_cycle8(50), - .output_clock_frequency9("0 MHz"), - .phase_shift9("0 ps"), - .duty_cycle9(50), - .output_clock_frequency10("0 MHz"), - .phase_shift10("0 ps"), - .duty_cycle10(50), - .output_clock_frequency11("0 MHz"), - .phase_shift11("0 ps"), - .duty_cycle11(50), - .output_clock_frequency12("0 MHz"), - .phase_shift12("0 ps"), - .duty_cycle12(50), - .output_clock_frequency13("0 MHz"), - .phase_shift13("0 ps"), - .duty_cycle13(50), - .output_clock_frequency14("0 MHz"), - .phase_shift14("0 ps"), - .duty_cycle14(50), - .output_clock_frequency15("0 MHz"), - .phase_shift15("0 ps"), - .duty_cycle15(50), - .output_clock_frequency16("0 MHz"), - .phase_shift16("0 ps"), - .duty_cycle16(50), - .output_clock_frequency17("0 MHz"), - .phase_shift17("0 ps"), - .duty_cycle17(50), - .pll_type("General"), - .pll_subtype("General") - ) altera_pll_i ( - .rst (rst), - .outclk ({outclk_3, outclk_2, outclk_1, outclk_0}), - .locked (locked), - .fboutclk ( ), - .fbclk (1'b0), - .refclk (refclk) - ); -endmodule - diff --git a/target/pocket/mf_pllbase.ppf b/target/pocket/nes_pll.ppf similarity index 86% rename from target/pocket/mf_pllbase.ppf rename to target/pocket/nes_pll.ppf index c9218c2..0e013a9 100644 --- a/target/pocket/mf_pllbase.ppf +++ b/target/pocket/nes_pll.ppf @@ -1,6 +1,6 @@ @@ -11,6 +11,7 @@ + diff --git a/target/pocket/nes_pll.qip b/target/pocket/nes_pll.qip new file mode 100644 index 0000000..2a2b5be --- /dev/null +++ b/target/pocket/nes_pll.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "nes_pll" -name MISC_FILE [file join $::quartus(qip_path) "nes_pll.cmp"] +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZQ==" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "nes_pll" -library "nes_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZV8wMDAy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NzQuMjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NzQuMjUgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::ODUuOTA4OTky::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjEuNDc3MjQ4::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Mjg=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NS4zNjkzMTI=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTEy::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::NS4zNjkzMTI=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MTEy::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::OTA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::OTAuMA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::NDIuOTU0NDk2::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::NDI1OTA3MDYy::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MTQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::ODUuOTA4OTkyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjEuNDc3MjQ4IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NS4zNjkzMTIgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::NS4zNjkzMTIgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::NDY1NjEgcHM=::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::NDIuOTU0NDk2IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw0LDMsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxNCwxNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1Niw1NiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1Niw1NiwyOSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsNyw3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMzAsMjAwMCw2MDEuMzYyOTQzIE1Ieiw0MjU5MDcwNjIsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "nes_pll" -name VERILOG_FILE [file join $::quartus(qip_path) "nes_pll.v"] +set_global_assignment -library "nes_pll" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "nes_pll_01.sv"] +set_global_assignment -library "nes_pll" -name QIP_FILE [file join $::quartus(qip_path) "nes_pll_01.qip"] + +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "nes_pll_01" -library "nes_pll" -name IP_TOOL_ENV "mwpim" diff --git a/target/pocket/mf_pllbase.v b/target/pocket/nes_pll.v similarity index 98% rename from target/pocket/mf_pllbase.v rename to target/pocket/nes_pll.v index cc53fc7..50d11a7 100644 --- a/target/pocket/mf_pllbase.v +++ b/target/pocket/nes_pll.v @@ -1,27 +1,29 @@ // megafunction wizard: %PLL Intel FPGA IP v21.1% // GENERATION: XML -// mf_pllbase.v +// nes_pll.v -// Generated using ACDS version 21.1 850 +// Generated using ACDS version 21.1 842 `timescale 1 ps / 1 ps -module mf_pllbase ( +module nes_pll ( input wire refclk, // refclk.clk input wire rst, // reset.reset output wire outclk_0, // outclk0.clk output wire outclk_1, // outclk1.clk output wire outclk_2, // outclk2.clk output wire outclk_3, // outclk3.clk + output wire outclk_4, // outclk4.clk output wire locked // locked.export ); - mf_pllbase_0002 mf_pllbase_inst ( + nes_pll_01 mf_pllbase_inst ( .refclk (refclk), // refclk.clk .rst (rst), // reset.reset .outclk_0 (outclk_0), // outclk0.clk .outclk_1 (outclk_1), // outclk1.clk .outclk_2 (outclk_2), // outclk2.clk .outclk_3 (outclk_3), // outclk3.clk + .outclk_4 (outclk_4), // outclk4.clk .locked (locked) // locked.export ); @@ -32,7 +34,7 @@ endmodule // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // ************************************************************ -// Copyright (C) 1991-2023 Altera Corporation +// Copyright (C) 1991-2025 Altera Corporation // Any megafunction design, and related net list (encrypted or decrypted), // support information, device programming or simulation file, and any other // associated documentation or information provided by Altera or a partner @@ -67,7 +69,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -108,7 +110,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -255,5 +257,5 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// IPFS_FILES : mf_pllbase.vo -// RELATED_FILES: mf_pllbase.v, mf_pllbase_0002.v +// IPFS_FILES : nes_pll.vo +// RELATED_FILES: nes_pll.v, nes_pll_01.v diff --git a/target/pocket/nes_pll_01.qip b/target/pocket/nes_pll_01.qip new file mode 100644 index 0000000..b4413a2 --- /dev/null +++ b/target/pocket/nes_pll_01.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*nes_pll_01*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*nes_pll_01*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*nes_pll_01*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*nes_pll_01*|altera_pll:altera_pll_i*|*" diff --git a/target/pocket/nes_pll_01.sv b/target/pocket/nes_pll_01.sv new file mode 100644 index 0000000..719eb30 --- /dev/null +++ b/target/pocket/nes_pll_01.sv @@ -0,0 +1,183 @@ +`timescale 1ns/10ps +module nes_pll_01 +( + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'outclk3' + output wire outclk_3, + + // interface 'outclk4' + output wire outclk_4, + + // interface 'locked' + output wire locked +); + +parameter USE_PAL_PLL = 1'b0; +initial begin +$info("*** nes_pll_01 ***"); +$info("USE_PAL_PLL %d", USE_PAL_PLL); +end + +//NTSC + generate + if (USE_PAL_PLL == 1'b0) begin + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("74.25 MHz"), + .operation_mode("normal"), + .number_of_clocks(5), + .output_clock_frequency0("85.908992 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("21.477248 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("5.369312 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("5.369312 MHz"), + .phase_shift3("46561 ps"), + .duty_cycle3(50), + .output_clock_frequency4("42.954496 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); + + //PAL +end else begin + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("74.25 MHz"), + .operation_mode("direct"), + .number_of_clocks(5), + .output_clock_frequency0("85.125472 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("21.281368 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("5.320342 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("5.320342 MHz"), + .phase_shift3("46989 ps"), + .duty_cycle3(50), + .output_clock_frequency4("42.562736 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); + end +endgenerate +endmodule + + diff --git a/target/pocket/pll_reconfig.ppf b/target/pocket/pll_reconfig.ppf deleted file mode 100644 index e6cec87..0000000 --- a/target/pocket/pll_reconfig.ppf +++ /dev/null @@ -1,19 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/target/pocket/pll_reconfig.qip b/target/pocket/pll_reconfig.qip deleted file mode 100644 index fa59c81..0000000 --- a/target/pocket/pll_reconfig.qip +++ /dev/null @@ -1,45 +0,0 @@ -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_TOOL_VERSION "21.1" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll_reconfig" -name MISC_FILE [file join $::quartus(qip_path) "pll_reconfig.cmp"] -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_QSYS_MODE "UNKNOWN" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_NAME "cGxsX3JlY29uZmln" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_DISPLAY_NAME "UExMIFJlY29uZmlnIEludGVsIEZQR0EgSVA=" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_VERSION "MjEuMQ==" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3AgUmVjb25maWd1cmF0aW9uIEJsb2Nr" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" -set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_DISPLAY_NAME "UExMIFJlY29uZmlnIEludGVsIEZQR0EgSVA=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_VERSION "MjEuMQ==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3AgUmVjb25maWd1cmF0aW9uIEJsb2Nr" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" - -set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig.v"] -set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig/altera_pll_reconfig_top.v"] -set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig/altera_pll_reconfig_core.v"] -set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig/altera_std_synchronizer.v"] - -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_TOOL_VERSION "21.1" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_TOOL_ENV "mwpim" diff --git a/target/pocket/pll_reconfig.v b/target/pocket/pll_reconfig.v deleted file mode 100644 index e302b87..0000000 --- a/target/pocket/pll_reconfig.v +++ /dev/null @@ -1,86 +0,0 @@ -// megafunction wizard: %PLL Reconfig Intel FPGA IP v21.1% -// GENERATION: XML -// pll_reconfig.v - -// Generated using ACDS version 21.1 850 - -`timescale 1 ps / 1 ps -module pll_reconfig #( - parameter ENABLE_BYTEENABLE = 0, - parameter BYTEENABLE_WIDTH = 4, - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - parameter reconf_width = 64, - parameter WAIT_FOR_LOCK = 1 - ) ( - input wire mgmt_clk, // mgmt_clk.clk - input wire mgmt_reset, // mgmt_reset.reset - output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest - input wire mgmt_read, // .read - input wire mgmt_write, // .write - output wire [31:0] mgmt_readdata, // .readdata - input wire [5:0] mgmt_address, // .address - input wire [31:0] mgmt_writedata, // .writedata - output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll - input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll - ); - - altera_pll_reconfig_top #( - .device_family ("Cyclone V"), - .ENABLE_MIF (0), - .MIF_FILE_NAME (""), - .ENABLE_BYTEENABLE (ENABLE_BYTEENABLE), - .BYTEENABLE_WIDTH (BYTEENABLE_WIDTH), - .RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH), - .reconf_width (reconf_width), - .WAIT_FOR_LOCK (WAIT_FOR_LOCK) - ) pll_reconfig_inst ( - .mgmt_clk (mgmt_clk), // mgmt_clk.clk - .mgmt_reset (mgmt_reset), // mgmt_reset.reset - .mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest - .mgmt_read (mgmt_read), // .read - .mgmt_write (mgmt_write), // .write - .mgmt_readdata (mgmt_readdata), // .readdata - .mgmt_address (mgmt_address), // .address - .mgmt_writedata (mgmt_writedata), // .writedata - .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll - .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll - .mgmt_byteenable (4'b0000) // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// IPFS_FILES : pll_reconfig.vo -// RELATED_FILES: pll_reconfig.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v diff --git a/target/pocket/pll_reconfig/altera_pll_reconfig_core.v b/target/pocket/pll_reconfig/altera_pll_reconfig_core.v deleted file mode 100644 index 01f9dd2..0000000 --- a/target/pocket/pll_reconfig/altera_pll_reconfig_core.v +++ /dev/null @@ -1,2184 +0,0 @@ -// (C) 2001-2022 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -`timescale 1ps/1ps - -module altera_pll_reconfig_core -#( - parameter reconf_width = 64, - parameter device_family = "Stratix V", - // MIF Streaming parameters - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - parameter ROM_ADDR_WIDTH = 9, - parameter ROM_DATA_WIDTH = 32, - parameter ROM_NUM_WORDS = 512 -) ( - - //input - input wire mgmt_clk, - input wire mgmt_reset, - - - //conduits - output wire [reconf_width-1:0] reconfig_to_pll, - input wire [reconf_width-1:0] reconfig_from_pll, - - // user data (avalon-MM slave interface) - output wire [31:0] mgmt_readdata, - output wire mgmt_waitrequest, - input wire [5:0] mgmt_address, - input wire mgmt_read, - input wire mgmt_write, - input wire [31:0] mgmt_writedata, - - //other - output wire mif_start_out, - output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr -); - localparam mode_WR = 1'b0; - localparam mode_POLL = 1'b1; - localparam MODE_REG = 6'b000000; - localparam STATUS_REG = 6'b000001; - localparam START_REG = 6'b000010; - localparam N_REG = 6'b000011; - localparam M_REG = 6'b000100; - localparam C_COUNTERS_REG = 6'b000101; - localparam DPS_REG = 6'b000110; - localparam DSM_REG = 6'b000111; - localparam BWCTRL_REG = 6'b001000; - localparam CP_CURRENT_REG = 6'b001001; - localparam ANY_DPRIO = 6'b100000; - localparam CNT_BASE = 5'b001010; - localparam VCO_REG = 6'b011100; - localparam MIF_REG = 6'b011111; - - //C Counters - localparam number_of_counters = 5'd18; - localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2, - CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5, - CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8, - CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11, - CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14, - CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17; - //C counter addresses - localparam C_CNT_0_DIV_ADDR = 5'h00; - localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11; - localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15; - localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17; - localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14; - localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16; - //N counter addresses - localparam N_CNT_DIV_ADDR = 5'h13; - localparam N_CNT_BYPASS_EN_ADDR = 5'h15; - localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17; - //M counter addresses - localparam M_CNT_DIV_ADDR = 5'h12; - localparam M_CNT_BYPASS_EN_ADDR = 5'h15; - localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17; - - //DSM address - localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18; - localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19; - localparam DSM_K_READY_ADDR = 5'h17; - localparam DSM_K_DITHER_ADDR = 5'h17; - localparam DSM_OUT_SEL_ADDR = 6'h30; - - //Other DSM params - localparam DSM_K_READY_BIT_INDEX = 4'd11; - //BWCTRL address - //Bit 0-3 of addr - localparam BWCTRL_ADDR = 6'h30; - //CP_CURRENT address - //Bit 0-2 of addr - localparam CP_CURRENT_ADDR = 6'h31; - - // VCODIV address - localparam VCO_ADDR = 5'h17; - - localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4, - FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10, - ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15; - localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10; - - wire clk; - wire reset; - wire gnd; - - wire [5: 0] slave_address; - wire slave_read; - wire slave_write; - wire [31: 0] slave_writedata; - - reg [31: 0] slave_readdata_d; - reg [31: 0] slave_readdata_q; - wire slave_waitrequest; - reg slave_mode; - - assign clk = mgmt_clk; - - assign slave_address = mgmt_address; - assign slave_read = mgmt_read; - assign slave_write = mgmt_write; - assign slave_writedata = mgmt_writedata; - - reg read_waitrequest; - // Outputs - assign mgmt_readdata = slave_readdata_q; - assign mgmt_waitrequest = slave_waitrequest | read_waitrequest; //Read waitrequest asserted in polling mode - - //internal signals - wire locked_orig; - wire locked; - - wire pll_start; - wire pll_start_valid; - reg status_read; - wire read_slave_mode_asserted; - - wire pll_start_asserted; - - reg [1:0] current_state; - reg [1:0] next_state; - - reg status;//0=busy, 1=ready - //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load); - //declaring the init wires. These will have 0 on them for 64 clk cycles - wire [ 5:0] init_dprio_address; - wire init_dprio_read; - wire [ 1:0] init_dprio_byteen; - wire init_dprio_write; - wire [15:0] init_dprio_writedata; - - wire init_atpgmode; - wire init_mdio_dis; - wire init_scanen; - wire init_ser_shift_load; - wire dprio_init_done; - - //DPRIO output signals after initialization is done - wire dprio_clk; - reg avmm_dprio_write; - reg avmm_dprio_read; - reg [5:0] avmm_dprio_address; - reg [15:0] avmm_dprio_writedata; - reg [1:0] avmm_dprio_byteen; - wire avmm_atpgmode; - wire avmm_mdio_dis; - wire avmm_scanen; - - //Final output wires that are muxed between the init and avmm wires. - wire dprio_init_reset; - wire [5:0] dprio_address /*synthesis keep*/; - wire dprio_read/*synthesis keep*/; - wire [1:0] dprio_byteen/*synthesis keep*/; - wire dprio_write/*synthesis keep*/; - wire [15:0] dprio_writedata/*synthesis keep*/; - wire dprio_mdio_dis/*synthesis keep*/; - wire dprio_ser_shift_load/*synthesis keep*/; - wire dprio_atpgmode/*synthesis keep*/; - wire dprio_scanen/*synthesis keep*/; - - - //other PLL signals for dyn ph shift - wire phase_done/*synthesis keep*/; - wire phase_en/*synthesis keep*/; - wire up_dn/*synthesis keep*/; - wire [4:0] cnt_sel; - - //DPRIO input signals - wire [15:0] dprio_readdata; - - //internal logic signals - //storage registers for user sent data - reg dprio_temp_read_1; - reg dprio_temp_read_2; - reg dprio_start; - reg mif_start_assert; - reg dps_start_assert; - wire usr_valid_changes; - reg [3:0] dprio_cur_state; - reg [3:0] dprio_next_state; - reg [15:0] dprio_temp_m_n_c_readdata_1_d; - reg [15:0] dprio_temp_m_n_c_readdata_2_d; - reg [15:0] dprio_temp_m_n_c_readdata_1_q; - reg [15:0] dprio_temp_m_n_c_readdata_2_q; - reg dprio_write_done; - //C counters signals - reg [7:0] usr_c_cnt_lo; - reg [7:0] usr_c_cnt_hi; - reg usr_c_cnt_bypass_en; - reg usr_c_cnt_odd_duty_div_en; - reg [7:0] temp_c_cnt_lo [0:17]; - reg [7:0] temp_c_cnt_hi [0:17]; - reg temp_c_cnt_bypass_en [0:17]; - reg temp_c_cnt_odd_duty_div_en [0:17]; - reg any_c_cnt_changed; - reg all_c_cnt_done_q; - reg all_c_cnt_done_d; - reg [17:0] c_cnt_changed; - reg [17:0] c_cnt_done_d; - reg [17:0] c_cnt_done_q; - //N counter signals - reg [7:0] usr_n_cnt_lo; - reg [7:0] usr_n_cnt_hi; - reg usr_n_cnt_bypass_en; - reg usr_n_cnt_odd_duty_div_en; - reg n_cnt_changed; - reg n_cnt_done_d; - reg n_cnt_done_q; - //M counter signals - reg [7:0] usr_m_cnt_lo; - reg [7:0] usr_m_cnt_hi; - reg usr_m_cnt_bypass_en; - reg usr_m_cnt_odd_duty_div_en; - reg m_cnt_changed; - reg m_cnt_done_d; - reg m_cnt_done_q; - //dyn phase regs - reg [15:0] usr_num_shifts; - reg [4:0] usr_cnt_sel /*synthesis preserve*/; - reg usr_up_dn; - reg dps_changed; - wire dps_changed_valid; - wire dps_done; - - //DSM Signals - reg [31:0] usr_k_value; - reg dsm_k_changed; - reg dsm_k_done_d; - reg dsm_k_done_q; - reg dsm_k_ready_false_done_d; - //BW signals - reg [3:0] usr_bwctrl_value; - reg bwctrl_changed; - reg bwctrl_done_d; - reg bwctrl_done_q; - //CP signals - reg [2:0] usr_cp_current_value; - reg cp_current_changed; - reg cp_current_done_d; - reg cp_current_done_q; - //VCO signals - reg usr_vco_value; - reg vco_changed; - reg vco_done_d; - reg vco_done_q; - //Manual DPRIO signals - reg manual_dprio_done_q; - reg manual_dprio_done_d; - reg manual_dprio_changed; - reg [5:0] usr_dprio_address; - reg [15:0] usr_dprio_writedata_0; - reg usr_r_w; - //keeping track of which operation happened last - reg [5:0] operation_address; - // Address wires for all C_counter DPRIO registers - // These are outputs of LUTS, changing depending - // on whether PLL_0 or PLL_1 being used - - - //Fitter will tell if FPLL1 is being used - wire fpll_1; - - // other - reg mif_reg_asserted; - // MAIN FSM - - // Synchronize locked signal - altera_std_synchronizer #( - .depth(3) - ) altera_std_synchronizer_inst ( - .clk(mgmt_clk), - .reset_n(~mgmt_reset), - .din(locked_orig), - .dout(locked) - ); - - always @(posedge clk) - begin - if (reset) - begin - dprio_cur_state <= DPRIO_IDLE; - current_state <= IDLE; - end - else - begin - current_state <= next_state; - dprio_cur_state <= dprio_next_state; - end - end - - always @(*) - begin - case(current_state) - IDLE: - begin - if (pll_start & !slave_waitrequest & usr_valid_changes) - next_state = WAIT_ON_LOCK; - else - next_state = IDLE; - end - WAIT_ON_LOCK: - begin - if (locked & dps_done & dprio_write_done) // received locked high from PLL - begin - if (slave_mode==mode_WR) //if the mode is waitrequest, then - // goto IDLE state directly - next_state = IDLE; - else - next_state = LOCKED; //otherwise go the locked state - end - else - next_state = WAIT_ON_LOCK; - end - - LOCKED: - begin - if (status_read) // stay in LOCKED until user reads status - next_state = IDLE; - else - next_state = LOCKED; - end - - default: next_state = 2'bxx; - - endcase - end - - - // ask the pll to start reconfig - assign pll_start = (pll_start_asserted & (current_state==IDLE)) ; - assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ; - - - - // WRITE OPERATIONS - assign pll_start_asserted = slave_write & (slave_address == START_REG); - assign mif_start_out = pll_start & mif_reg_asserted; - - //reading the mode register to determine what mode the slave will operate - //in. - always @(posedge clk) - begin - if (reset) - slave_mode <= mode_WR; - else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest) - slave_mode <= slave_writedata[0]; - end - - //record which values user wants to change. - - //reading in the actual values that need to be reconfigged and sending - //them to the PLL - always @(posedge clk) - begin - if (reset) - begin - //reset all regs here - //BW signals reset - usr_bwctrl_value <= 0; - bwctrl_changed <= 0; - bwctrl_done_q <= 0; - //CP signals reset - usr_cp_current_value <= 0; - cp_current_changed <= 0; - cp_current_done_q <= 0; - //VCO signals reset - usr_vco_value <= 0; - vco_changed <= 0; - vco_done_q <= 0; - //DSM signals reset - usr_k_value <= 0; - dsm_k_changed <= 0; - dsm_k_done_q <= 0; - //N counter signals reset - usr_n_cnt_lo <= 0; - usr_n_cnt_hi <= 0; - usr_n_cnt_bypass_en <= 0; - usr_n_cnt_odd_duty_div_en <= 0; - n_cnt_changed <= 0; - n_cnt_done_q <= 0; - //M counter signals reset - usr_m_cnt_lo <= 0; - usr_m_cnt_hi <= 0; - usr_m_cnt_bypass_en <= 0; - usr_m_cnt_odd_duty_div_en <= 0; - m_cnt_changed <= 0; - m_cnt_done_q <= 0; - //C counter signals reset - usr_c_cnt_lo <= 0; - usr_c_cnt_hi <= 0; - usr_c_cnt_bypass_en <= 0; - usr_c_cnt_odd_duty_div_en <= 0; - any_c_cnt_changed <= 0; - all_c_cnt_done_q <= 0; - c_cnt_done_q <= 0; - //generic signals - dprio_start <= 0; - mif_start_assert <= 0; - dps_start_assert <= 0; - dprio_temp_m_n_c_readdata_1_q <= 0; - dprio_temp_m_n_c_readdata_2_q <= 0; - c_cnt_done_q <= 0; - //DPS signals - usr_up_dn <= 0; - usr_cnt_sel <= 0; - usr_num_shifts <= 0; - dps_changed <= 0; - //manual DPRIO signals - manual_dprio_changed <= 0; - usr_dprio_address <= 0; - usr_dprio_writedata_0 <= 0; - usr_r_w <= 0; - operation_address <= 0; - mif_reg_asserted <= 0; - mif_base_addr <= 0; - end - else - begin - if (dprio_temp_read_1) - begin - dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; - end - if (dprio_temp_read_2) - begin - dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; - end - if ((dps_done)) dps_changed <= 0; - if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d; - if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d; - if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d; - if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d; - if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d; - if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d; - if (cp_current_done_d) cp_current_done_q <= cp_current_done_d; - if (vco_done_d) vco_done_q <= vco_done_d; - if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d; - - if (mif_start_out == 1'b1) - mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle - - if (dps_done != 1'b1) - dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle - - if (dprio_next_state == ONE) - dprio_start <= 0; - if (dprio_write_done) - begin - bwctrl_done_q <= 0; - cp_current_done_q <= 0; - vco_done_q <= 0; - dsm_k_done_q <= 0; - dsm_k_done_q <= 0; - n_cnt_done_q <= 0; - m_cnt_done_q <= 0; - all_c_cnt_done_q <= 0; - c_cnt_done_q <= 0; - dsm_k_changed <= 0; - n_cnt_changed <= 0; - m_cnt_changed <= 0; - any_c_cnt_changed <= 0; - bwctrl_changed <= 0; - cp_current_changed <= 0; - vco_changed <= 0; - manual_dprio_changed <= 0; - manual_dprio_done_q <= 0; - if (dps_changed | dps_changed_valid | !dps_done ) - begin - usr_cnt_sel <= usr_cnt_sel; - end - else - begin - usr_cnt_sel <= 0; - end - mif_reg_asserted <= 0; - end - else - begin - dsm_k_changed <= dsm_k_changed; - n_cnt_changed <= n_cnt_changed; - m_cnt_changed <= m_cnt_changed; - any_c_cnt_changed <= any_c_cnt_changed; - manual_dprio_changed <= manual_dprio_changed; - mif_reg_asserted <= mif_reg_asserted; - usr_cnt_sel <= usr_cnt_sel; - end - - - if(slave_write & !slave_waitrequest) - begin - case(slave_address) - //read in the values here from the user and act on them - DSM_REG: - begin - operation_address <= DSM_REG; - usr_k_value <= slave_writedata[31:0]; - dsm_k_changed <= 1'b1; - dsm_k_done_q <= 0; - dprio_start <= 1'b1; - end - N_REG: - begin - operation_address <= N_REG; - usr_n_cnt_lo <= slave_writedata[7:0]; - usr_n_cnt_hi <= slave_writedata[15:8]; - usr_n_cnt_bypass_en <= slave_writedata[16]; - usr_n_cnt_odd_duty_div_en <= slave_writedata[17]; - n_cnt_changed <= 1'b1; - n_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - M_REG: - begin - operation_address <= M_REG; - usr_m_cnt_lo <= slave_writedata[7:0]; - usr_m_cnt_hi <= slave_writedata[15:8]; - usr_m_cnt_bypass_en <= slave_writedata[16]; - usr_m_cnt_odd_duty_div_en <= slave_writedata[17]; - m_cnt_changed <= 1'b1; - m_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - DPS_REG: - begin - operation_address <= DPS_REG; - usr_num_shifts <= slave_writedata[15:0]; - usr_cnt_sel <= slave_writedata[20:16]; - usr_up_dn <= slave_writedata[21]; - dps_changed <= 1; - dps_start_assert <= 1; - end - C_COUNTERS_REG: - begin - operation_address <= C_COUNTERS_REG; - usr_c_cnt_lo <= slave_writedata[7:0]; - usr_c_cnt_hi <= slave_writedata[15:8]; - usr_c_cnt_bypass_en <= slave_writedata[16]; - usr_c_cnt_odd_duty_div_en <= slave_writedata[17]; - usr_cnt_sel <= slave_writedata[22:18]; - any_c_cnt_changed <= 1'b1; - all_c_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - BWCTRL_REG: - begin - usr_bwctrl_value <= slave_writedata[3:0]; - bwctrl_changed <= 1'b1; - bwctrl_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= BWCTRL_REG; - end - CP_CURRENT_REG: - begin - usr_cp_current_value <= slave_writedata[2:0]; - cp_current_changed <= 1'b1; - cp_current_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= CP_CURRENT_REG; - end - VCO_REG: - begin - usr_vco_value <= slave_writedata[0]; - vco_changed <= 1'b1; - vco_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= VCO_REG; - end - ANY_DPRIO: - begin - operation_address <= ANY_DPRIO; - manual_dprio_changed <= 1'b1; - usr_dprio_address <= slave_writedata[5:0]; - usr_dprio_writedata_0 <= slave_writedata[21:6]; - usr_r_w <= slave_writedata[22]; - manual_dprio_done_q <= 0; - dprio_start <= 1'b1; - end - MIF_REG: - begin - mif_reg_asserted <= 1'b1; - mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0]; - mif_start_assert <= 1'b1; - end - endcase - end - end - end - //C Counter assigning values to the 2-d array of values for each C counter - - reg [4:0] j; - always @(posedge clk) - begin - - if (reset) - begin - c_cnt_changed[17:0] <= 0; - for (j = 0; j < number_of_counters; j = j + 1'b1) - begin : c_cnt_reset - temp_c_cnt_bypass_en[j] <= 0; - temp_c_cnt_odd_duty_div_en[j] <= 0; - temp_c_cnt_lo[j][7:0] <= 0; - temp_c_cnt_hi[j][7:0] <= 0; - end - end - else - begin - if (dprio_write_done) - begin - c_cnt_changed <= 0; - end - if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG)) - begin - case (cnt_sel) - CNT_0: - begin - temp_c_cnt_lo [0] <= usr_c_cnt_lo; - temp_c_cnt_hi [0] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [0] <= 1'b1; - end - CNT_1: - begin - temp_c_cnt_lo [1] <= usr_c_cnt_lo; - temp_c_cnt_hi [1] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [1] <= 1'b1; - end - CNT_2: - begin - temp_c_cnt_lo [2] <= usr_c_cnt_lo; - temp_c_cnt_hi [2] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [2] <= 1'b1; - end - CNT_3: - begin - temp_c_cnt_lo [3] <= usr_c_cnt_lo; - temp_c_cnt_hi [3] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [3] <= 1'b1; - end - CNT_4: - begin - temp_c_cnt_lo [4] <= usr_c_cnt_lo; - temp_c_cnt_hi [4] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [4] <= 1'b1; - end - CNT_5: - begin - temp_c_cnt_lo [5] <= usr_c_cnt_lo; - temp_c_cnt_hi [5] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [5] <= 1'b1; - end - CNT_6: - begin - temp_c_cnt_lo [6] <= usr_c_cnt_lo; - temp_c_cnt_hi [6] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [6] <= 1'b1; - end - CNT_7: - begin - temp_c_cnt_lo [7] <= usr_c_cnt_lo; - temp_c_cnt_hi [7] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [7] <= 1'b1; - end - CNT_8: - begin - temp_c_cnt_lo [8] <= usr_c_cnt_lo; - temp_c_cnt_hi [8] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [8] <= 1'b1; - end - CNT_9: - begin - temp_c_cnt_lo [9] <= usr_c_cnt_lo; - temp_c_cnt_hi [9] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [9] <= 1'b1; - end - CNT_10: - begin - temp_c_cnt_lo [10] <= usr_c_cnt_lo; - temp_c_cnt_hi [10] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [10] <= 1'b1; - end - CNT_11: - begin - temp_c_cnt_lo [11] <= usr_c_cnt_lo; - temp_c_cnt_hi [11] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [11] <= 1'b1; - end - CNT_12: - begin - temp_c_cnt_lo [12] <= usr_c_cnt_lo; - temp_c_cnt_hi [12] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [12] <= 1'b1; - end - CNT_13: - begin - temp_c_cnt_lo [13] <= usr_c_cnt_lo; - temp_c_cnt_hi [13] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [13] <= 1'b1; - end - CNT_14: - begin - temp_c_cnt_lo [14] <= usr_c_cnt_lo; - temp_c_cnt_hi [14] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [14] <= 1'b1; - end - CNT_15: - begin - temp_c_cnt_lo [15] <= usr_c_cnt_lo; - temp_c_cnt_hi [15] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [15] <= 1'b1; - end - CNT_16: - begin - temp_c_cnt_lo [16] <= usr_c_cnt_lo; - temp_c_cnt_hi [16] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [16] <= 1'b1; - end - CNT_17: - begin - temp_c_cnt_lo [17] <= usr_c_cnt_lo; - temp_c_cnt_hi [17] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [17] <= 1'b1; - end - endcase - - end - end - end - - - //logic to handle which writes the user indicated and wants to start. - assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed; - - - //start the reconfig operations by writing to the DPRIO - reg break_loop; - reg [4:0] i; - always @(*) - begin - dprio_temp_read_1 = 0; - dprio_temp_read_2 = 0; - dprio_temp_m_n_c_readdata_1_d = 0; - dprio_temp_m_n_c_readdata_2_d = 0; - break_loop = 0; - dprio_next_state = DPRIO_IDLE; - avmm_dprio_write = 0; - avmm_dprio_read = 0; - avmm_dprio_address = 0; - avmm_dprio_writedata = 0; - avmm_dprio_byteen = 0; - dprio_write_done = 1; - manual_dprio_done_d = 0; - n_cnt_done_d = 0; - dsm_k_done_d = 0; - dsm_k_ready_false_done_d = 0; - m_cnt_done_d = 0; - c_cnt_done_d[17:0] = 0; - all_c_cnt_done_d = 0; - bwctrl_done_d = 0; - cp_current_done_d = 0; - vco_done_d = 0; - i = 0; - - // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) - if (dprio_start | mif_start_assert) - dprio_write_done = 0; - - if (current_state == WAIT_ON_LOCK) - begin - case (dprio_cur_state) - ONE: - begin - if (n_cnt_changed & !n_cnt_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_address = N_CNT_DIV_ADDR; - avmm_dprio_writedata[7:0] = usr_n_cnt_lo; - avmm_dprio_writedata[15:8] = usr_n_cnt_hi; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_address = M_CNT_DIV_ADDR; - avmm_dprio_writedata[7:0] = usr_m_cnt_lo; - avmm_dprio_writedata[15:8] = usr_m_cnt_hi; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_hilo - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i; - else avmm_dprio_address = C_CNT_0_DIV_ADDR + i; - avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i]; - avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i]; - //To break from the loop, since only one counter - //is addressed at a time - break_loop = 1'b1; - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (cp_current_changed & !cp_current_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (vco_changed & !vco_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (manual_dprio_changed & !manual_dprio_done_q) - begin - dprio_write_done = 0; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_write = usr_r_w; - avmm_dprio_address = usr_dprio_address; - avmm_dprio_writedata[15:0] = usr_dprio_writedata_0; - end - else dprio_next_state = DPRIO_IDLE; - end - - TWO: - begin - //handle reading the two setting bits on n_cnt, then - //writing them back while preserving other bits. - //Issue two consecutive reads then wait; readLatency=3 - dprio_write_done = 0; - dprio_next_state = THREE; - avmm_dprio_byteen = 2'b11; - avmm_dprio_read = 1'b1; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; - end - - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_read_bypass - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - end - end - end - //reading the K ready 16 bit word. Need to write 0 to it - //afterwards to indicate that K has not been done writing - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - dprio_next_state = FOUR; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_address = BWCTRL_ADDR; - dprio_next_state = FOUR; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_address = CP_CURRENT_ADDR; - dprio_next_state = FOUR; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_address = VCO_ADDR; - dprio_next_state = FOUR; - end - else if (manual_dprio_changed & !manual_dprio_done_q) - begin - avmm_dprio_read = ~usr_r_w; - avmm_dprio_address = usr_dprio_address; - dprio_next_state = DPRIO_DONE; - end - else dprio_next_state = DPRIO_IDLE; - end - THREE: - begin - dprio_write_done = 0; - avmm_dprio_byteen = 2'b11; - avmm_dprio_read = 1'b1; - dprio_next_state = FOUR; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_read_odd_div - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - end - end - end - else dprio_next_state = DPRIO_IDLE; - end - FOUR: - begin - dprio_temp_read_1 = 1'b1; - dprio_write_done = 0; - if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) - begin - dprio_temp_m_n_c_readdata_1_d = dprio_readdata; - dprio_next_state = FIVE; - end - else dprio_next_state = DPRIO_IDLE; - end - FIVE: - begin - dprio_write_done = 0; - dprio_temp_read_2 = 1'b1; - if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) - begin - //this is where DSM ready value comes. - //Need to store in a register to be used later - dprio_temp_m_n_c_readdata_2_d = dprio_readdata; - dprio_next_state = SIX; - end - else dprio_next_state = DPRIO_IDLE; - end - SIX: - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = SEVEN; - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; - avmm_dprio_writedata[5] = usr_n_cnt_bypass_en; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; - avmm_dprio_writedata[4] = usr_m_cnt_bypass_en; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_bypass - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_write = 0; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_write = 0; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_write = 0; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_write = 0; - end - else dprio_next_state = DPRIO_IDLE; - end - SEVEN: - begin - dprio_write_done = 0; - dprio_next_state = EIGHT; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en; - n_cnt_done_d = 1'b1; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en; - m_cnt_done_d = 1'b1; - end - - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_odd_div - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - //have to OR the signals to prevent - //overwriting of previous dones - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - //have to OR the signals to prevent - //overwriting of previous dones - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0; - dsm_k_ready_false_done_d = 1'b1; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_address = BWCTRL_ADDR; - avmm_dprio_writedata[3:0] = usr_bwctrl_value; - bwctrl_done_d = 1'b1; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_address = CP_CURRENT_ADDR; - avmm_dprio_writedata[2:0] = usr_cp_current_value; - cp_current_done_d = 1'b1; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_address = VCO_ADDR; - avmm_dprio_writedata[8] = usr_vco_value; - vco_done_d = 1'b1; - end - - - //if all C_cnt that were changed are done, then assert all_c_cnt_done - if (c_cnt_done_d == c_cnt_changed) - all_c_cnt_done_d = 1'b1; - if (n_cnt_changed & n_cnt_done_d) - dprio_next_state = DPRIO_DONE; - if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q) - dprio_next_state = ONE; - else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q) - dprio_next_state = ONE; - else if (dsm_k_changed & !dsm_k_ready_false_done_d) - dprio_next_state = TWO; - else if (dsm_k_changed & !dsm_k_done_q) - dprio_next_state = EIGHT; - else if (bwctrl_changed & !bwctrl_done_d) - dprio_next_state = TWO; - else if (cp_current_changed & !cp_current_done_d) - dprio_next_state = TWO; - else if (vco_changed & !vco_done_d) - dprio_next_state = TWO; - else - begin - dprio_next_state = DPRIO_DONE; - dprio_write_done = 1'b1; - end - end - //finish the rest of the DSM reads/writes - //writing k value, writing k_ready to 1. - EIGHT: - begin - dprio_write_done = 0; - dprio_next_state = NINE; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0; - avmm_dprio_writedata[15:0] = usr_k_value[15:0]; - end - end - NINE: - begin - dprio_write_done = 0; - dprio_next_state = TEN; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1; - avmm_dprio_writedata[15:0] = usr_k_value[31:16]; - end - end - TEN: - begin - dprio_write_done = 0; - dprio_next_state = ONE; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - //already have the readdata for DSM_K_READY_ADDR since we read it - //earlier. Just reuse here - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; - avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1; - dsm_k_done_d = 1'b1; - end - end - DPRIO_DONE: - begin - dprio_write_done = 1'b1; - if (dprio_start) dprio_next_state = DPRIO_IDLE; - else dprio_next_state = DPRIO_DONE; - end - DPRIO_IDLE: - begin - if (dprio_start) dprio_next_state = ONE; - else dprio_next_state = DPRIO_IDLE; - end - default: dprio_next_state = 4'bxxxx; - endcase - end - - end - - - //assert the waitreq signal according to the state of the slave - assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0; - - // Read operations - always @(*) - begin - status = 0; - if (slave_mode == mode_POLL) - //asserting status to 1 if the slave is done. - status = (current_state == LOCKED); - end - //************************************************************// - //************************************************************// - //******************** READ STATE MACHINE ********************// - //************************************************************// - //************************************************************// - reg [1:0] current_read_state; - reg [1:0] next_read_state; - reg [5:0] slave_address_int_d; - reg [5:0] slave_address_int_q; - reg dprio_read_1; - reg [5:0] dprio_address_1; - reg [1:0] dprio_byteen_1; - reg [4:0] usr_cnt_sel_1; - localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10, READ_POST_WAIT = 2'b11; - - always @(*) - begin - if(next_read_state == READ_IDLE) - begin - read_waitrequest <= 1'b0; - end - else - begin - read_waitrequest <= 1'b1; - end - end - - always @(posedge clk) - begin - if (reset) - begin - current_read_state <= READ_IDLE; - slave_address_int_q <= 0; - slave_readdata_q <= 0; - end - else - begin - current_read_state <= next_read_state; - slave_address_int_q <= slave_address_int_d; - slave_readdata_q <= slave_readdata_d; - end - end - always @(*) - begin - dprio_read_1 = 0; - dprio_address_1 = 0; - dprio_byteen_1 = 0; - slave_address_int_d = 0; - slave_readdata_d = 0; - status_read = 0; - usr_cnt_sel_1 = 0; - case(current_read_state) - READ_IDLE: - begin - slave_address_int_d = 0; - next_read_state = READ_IDLE; - if ((current_state != WAIT_ON_LOCK) && slave_read) - begin - slave_address_int_d = slave_address; - if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18)) - begin - next_read_state = READ_WAIT; - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE); - if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel; - else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel; - end - else - begin - case (slave_address) - MODE_REG: - begin - next_read_state = READ_WAIT; - slave_readdata_d = slave_mode; - end - STATUS_REG: - begin - next_read_state = READ_WAIT; - status_read = 1'b1; - slave_readdata_d = status; - end - N_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = N_CNT_DIV_ADDR; - next_read_state = READ_WAIT; - end - M_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = M_CNT_DIV_ADDR; - next_read_state = READ_WAIT; - end - BWCTRL_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = BWCTRL_ADDR; - next_read_state = READ_WAIT; - end - CP_CURRENT_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = CP_CURRENT_ADDR; - next_read_state = READ_WAIT; - end - VCO_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = VCO_ADDR; - next_read_state = READ_WAIT; - end - ANY_DPRIO: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = ~slave_writedata[22]; - dprio_address_1 = slave_writedata[5:0]; - next_read_state = READ_WAIT; - end - default : next_read_state = READ_IDLE; - endcase - end - end - else - next_read_state = READ_IDLE; - end - READ_WAIT: - begin - next_read_state = READ; - slave_address_int_d = slave_address_int_q; - case (slave_address_int_q) - MODE_REG: - begin - slave_readdata_d = slave_readdata_q; - end - STATUS_REG: - begin - slave_readdata_d = slave_readdata_q; - end - endcase - end - READ: - begin - next_read_state = READ_POST_WAIT; - slave_address_int_d = slave_address_int_q; - slave_readdata_d = dprio_readdata; - case (slave_address_int_q) - MODE_REG: - begin - slave_readdata_d = slave_readdata_q; - end - STATUS_REG: - begin - slave_readdata_d = slave_readdata_q; - end - BWCTRL_REG: - begin - slave_readdata_d = dprio_readdata[3:0]; - end - CP_CURRENT_REG: - begin - slave_readdata_d = dprio_readdata[2:0]; - end - VCO_REG: - begin - slave_readdata_d = dprio_readdata[8]; - end - ANY_DPRIO: - begin - slave_readdata_d = dprio_readdata; - end - endcase - end - READ_POST_WAIT: - begin - next_read_state = READ_IDLE; - end - default: next_read_state = 2'bxx; - endcase - end - - - dyn_phase_shift dyn_phase_shift_inst ( - .clk(clk), - .reset(reset), - .phase_done(phase_done), - .pll_start_valid(pll_start_valid), - .dps_changed(dps_changed), - .dps_changed_valid(dps_changed_valid), - .dprio_write_done(dprio_write_done), - .usr_num_shifts(usr_num_shifts), - .usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1), - .usr_up_dn(usr_up_dn), - .locked(locked), - .dps_done(dps_done), - .phase_en(phase_en), - .up_dn(up_dn), - .cnt_sel(cnt_sel)); - defparam dyn_phase_shift_inst.device_family = device_family; - - assign dprio_clk = clk; - self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset); - - dprio_mux dprio_mux_inst ( - .init_dprio_address(init_dprio_address), - .init_dprio_read(init_dprio_read), - .init_dprio_byteen(init_dprio_byteen), - .init_dprio_write(init_dprio_write), - .init_dprio_writedata(init_dprio_writedata), - - - .init_atpgmode(init_atpgmode), - .init_mdio_dis(init_mdio_dis), - .init_scanen(init_scanen), - .init_ser_shift_load(init_ser_shift_load), - .dprio_init_done(dprio_init_done), - - // Inputs from avmm master - .avmm_dprio_address(avmm_dprio_address | dprio_address_1), - .avmm_dprio_read(avmm_dprio_read | dprio_read_1), - .avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1), - .avmm_dprio_write(avmm_dprio_write), - .avmm_dprio_writedata(avmm_dprio_writedata), - - .avmm_atpgmode(avmm_atpgmode), - .avmm_mdio_dis(avmm_mdio_dis), - .avmm_scanen(avmm_scanen), - - // Outputs to fpll - .dprio_address(dprio_address), - .dprio_read(dprio_read), - .dprio_byteen(dprio_byteen), - .dprio_write(dprio_write), - .dprio_writedata(dprio_writedata), - - .atpgmode(dprio_atpgmode), - .mdio_dis(dprio_mdio_dis), - .scanen(dprio_scanen), - .ser_shift_load(dprio_ser_shift_load) - ); - - - fpll_dprio_init fpll_dprio_init_inst ( - .clk(clk), - .reset_n(~reset), - .locked(locked), - - //outputs - .dprio_address(init_dprio_address), - .dprio_read(init_dprio_read), - .dprio_byteen(init_dprio_byteen), - .dprio_write(init_dprio_write), - .dprio_writedata(init_dprio_writedata), - - .atpgmode(init_atpgmode), - .mdio_dis(init_mdio_dis), - .scanen(init_scanen), - .ser_shift_load(init_ser_shift_load), - .dprio_init_done(dprio_init_done)); - - //address luts, to be reconfigged by the Fitter - //FPLL_1 or 0 address lut - generic_lcell_comb lcell_fpll_0_1 ( - .dataa(1'b0), - .combout (fpll_1)); - defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA; - defparam lcell_fpll_0_1.dont_touch = "on"; - defparam lcell_fpll_0_1.family = device_family; - - - wire dprio_read_combout; - generic_lcell_comb lcell_dprio_read ( - .dataa(fpll_1), - .datab(dprio_read), - .datac(1'b0), - .datad(1'b0), - .datae(1'b0), - .dataf(1'b0), - .combout (dprio_read_combout)); - defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC; - defparam lcell_dprio_read.dont_touch = "on"; - defparam lcell_dprio_read.family = device_family; - - - - - - //assign reconfig_to_pll signals - assign reconfig_to_pll[0] = dprio_clk; - assign reconfig_to_pll[1] = ~dprio_init_reset; - assign reconfig_to_pll[2] = dprio_write; - assign reconfig_to_pll[3] = dprio_read_combout; - assign reconfig_to_pll[9:4] = dprio_address; - assign reconfig_to_pll[25:10] = dprio_writedata; - assign reconfig_to_pll[27:26] = dprio_byteen; - assign reconfig_to_pll[28] = dprio_ser_shift_load; - assign reconfig_to_pll[29] = dprio_mdio_dis; - assign reconfig_to_pll[30] = phase_en; - assign reconfig_to_pll[31] = up_dn; - assign reconfig_to_pll[36:32] = cnt_sel; - assign reconfig_to_pll[37] = dprio_scanen; - assign reconfig_to_pll[38] = dprio_atpgmode; - //assign reconfig_to_pll[40:37] = clken; - assign reconfig_to_pll[63:39] = 0; - - //assign reconfig_from_pll signals - assign dprio_readdata = reconfig_from_pll [15:0]; - assign locked_orig = reconfig_from_pll [16]; - assign phase_done = reconfig_from_pll [17]; - -endmodule -module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset); - - localparam RESET_COUNTER_VALUE = 3'd2; - localparam INITIAL_WAIT_VALUE = 9'd340; - reg [9:0]counter; - reg local_reset; - reg usr_mode_init_wait; - initial - begin - local_reset = 1'b1; - counter = 0; - usr_mode_init_wait = 0; - end - - always @(posedge clk) - begin - if (mgmt_reset) - begin - counter <= 0; - end - else - begin - if (!usr_mode_init_wait) - begin - if (counter == INITIAL_WAIT_VALUE) - begin - local_reset <= 0; - usr_mode_init_wait <= 1'b1; - counter <= 0; - end - else - begin - counter <= counter + 1'b1; - end - end - else - begin - if (counter == RESET_COUNTER_VALUE) - local_reset <= 0; - else - counter <= counter + 1'b1; - end - end - end - assign reset = mgmt_reset | local_reset; - assign init_reset = local_reset; -endmodule - -module dprio_mux ( - // Inputs from init block - input [ 5:0] init_dprio_address, - input init_dprio_read, - input [ 1:0] init_dprio_byteen, - input init_dprio_write, - input [15:0] init_dprio_writedata, - - input init_atpgmode, - input init_mdio_dis, - input init_scanen, - input init_ser_shift_load, - input dprio_init_done, - - // Inputs from avmm master - input [ 5:0] avmm_dprio_address, - input avmm_dprio_read, - input [ 1:0] avmm_dprio_byteen, - input avmm_dprio_write, - input [15:0] avmm_dprio_writedata, - - input avmm_atpgmode, - input avmm_mdio_dis, - input avmm_scanen, - input avmm_ser_shift_load, - - // Outputs to fpll - output [ 5:0] dprio_address, - output dprio_read, - output [ 1:0] dprio_byteen, - output dprio_write, - output [15:0] dprio_writedata, - - output atpgmode, - output mdio_dis, - output scanen, - output ser_shift_load -); - - assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address; - assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read; - assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen; - assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write; - assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata; - - assign atpgmode = init_atpgmode; - assign scanen = init_scanen; - assign mdio_dis = init_mdio_dis; - assign ser_shift_load = init_ser_shift_load ; -endmodule -module fpll_dprio_init ( - input clk, - input reset_n, - input locked, - - output [ 5:0] dprio_address, - output dprio_read, - output [ 1:0] dprio_byteen, - output dprio_write, - output [15:0] dprio_writedata, - - output reg atpgmode, - output reg mdio_dis, - output reg scanen, - output reg ser_shift_load, - output reg dprio_init_done -); - - reg [1:0] rst_n = 2'b00; - reg [6:0] count = 7'd0; - reg init_done_forever; - - // Internal versions of control signals - wire int_mdio_dis; - wire int_ser_shift_load; - wire int_dprio_init_done; - wire int_atpgmode/*synthesis keep*/; - wire int_scanen/*synthesis keep*/; - - - assign dprio_address = count[6] ? 5'b0 : count[5:0] ; - assign dprio_byteen = 2'b11; // always enabled - assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles - assign dprio_read = 1'b0; - assign dprio_writedata = 16'd0; - - assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1; - assign int_mdio_dis = count[6] ? ~count[2] : 1'b1; - assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0) - : 1'b1; - assign int_atpgmode = 0; - assign int_scanen = 0; - - initial begin - count = 7'd0; - init_done_forever = 0; - mdio_dis = 1'b1; - ser_shift_load = 1'b1; - dprio_init_done = 1'b0; - scanen = 1'b0; - atpgmode = 1'b0; - end - - // reset synch. - always @(posedge clk or negedge reset_n) - if(!reset_n) rst_n <= 2'b00; - else rst_n <= {rst_n[0],1'b1}; - - // counter - always @(posedge clk) - begin - if (!rst_n[1]) - init_done_forever <= 1'b0; - else - begin - if (count[6] && &count[1:0]) - init_done_forever <= 1'b1; - end - end - always @(posedge clk or negedge rst_n[1]) - begin - if(!rst_n[1]) - begin - count <= 7'd0; - end - else if(~int_dprio_init_done) - begin - count <= count + 7'd1; - end - else - begin - count <= count; - end - end - - // outputs - always @(posedge clk) begin - mdio_dis <= int_mdio_dis; - ser_shift_load <= int_ser_shift_load; - dprio_init_done <= int_dprio_init_done; - atpgmode <= int_atpgmode; - scanen <= int_scanen; - end - -endmodule -module dyn_phase_shift -#( - parameter device_family = "Stratix V" -) ( - - input wire clk, - input wire reset, - input wire phase_done, - input wire pll_start_valid, - input wire dps_changed, - input wire dprio_write_done, - input wire [15:0] usr_num_shifts, - input wire [4:0] usr_cnt_sel, - input wire usr_up_dn, - input wire locked, - - //output - output wire dps_done, - output reg phase_en, - output wire up_dn, - output wire dps_changed_valid, - output wire [4:0] cnt_sel); - - - - reg first_phase_shift_d; - reg first_phase_shift_q; - reg [15:0] phase_en_counter; - reg [3:0] dps_current_state; - reg [3:0] dps_next_state; - localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; - localparam PHASE_EN_WAIT_COUNTER = 5'd1; - - reg [15:0] shifts_done_counter; - reg phase_done_final; - wire gnd /*synthesis keep*/; - - //fsm - //always block controlling the state regs - always @(posedge clk) - begin - if (reset) - begin - dps_current_state <= DPS_DONE; - end - else - begin - dps_current_state <= dps_next_state; - end - end - //the combinational part. assigning the next state - //this turns on the phase_done_final signal when phase_done does this: - //_____ ______ - // |______| - always @(*) - begin - phase_done_final = 0; - first_phase_shift_d = 0; - phase_en = 0; - dps_next_state = DPS_DONE; - case (dps_current_state) - DPS_START: - begin - phase_en = 1'b1; - dps_next_state = DPS_WAIT_PHASE_EN; - end - DPS_WAIT_PHASE_EN: - begin - phase_en = 1'b1; - if (first_phase_shift_q) - begin - first_phase_shift_d = 1'b1; - dps_next_state = DPS_WAIT_PHASE_EN; - end - else - begin - if (phase_en_counter == PHASE_EN_WAIT_COUNTER) - dps_next_state = DPS_WAIT_PHASE_DONE; - else dps_next_state = DPS_WAIT_PHASE_EN; - end - end - DPS_WAIT_PHASE_DONE: - begin - if (!phase_done | !locked) - begin - dps_next_state = DPS_WAIT_PHASE_DONE; - end - else - begin - if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0)) - begin - dps_next_state = DPS_START; - phase_done_final = 1'b1; - end - else - begin - dps_next_state = DPS_DONE; - end - - end - end - DPS_DONE: - begin - phase_done_final = 0; - if (dps_changed) - dps_next_state = DPS_CHANGED; - else dps_next_state = DPS_DONE; - - end - DPS_CHANGED: - begin - if (pll_start_valid) - dps_next_state = DPS_WAIT_DPRIO_WRITING; - else - dps_next_state = DPS_CHANGED; - end - DPS_WAIT_DPRIO_WRITING: - begin - if (dprio_write_done) - dps_next_state = DPS_START; - else - dps_next_state = DPS_WAIT_DPRIO_WRITING; - end - - default: dps_next_state = 4'bxxxx; - endcase - - - end - - always @(posedge clk) - begin - - - if (dps_current_state == DPS_WAIT_PHASE_DONE) - phase_en_counter <= 0; - else if (dps_current_state == DPS_WAIT_PHASE_EN) - phase_en_counter <= phase_en_counter + 1'b1; - - if (reset) - begin - phase_en_counter <= 0; - shifts_done_counter <= 1'b1; - first_phase_shift_q <= 1; - end - else - begin - if (first_phase_shift_d) - first_phase_shift_q <= 0; - if (dps_done) - begin - shifts_done_counter <= 1'b1; - end - else - begin - if (phase_done_final & (dps_next_state!= DPS_DONE)) - shifts_done_counter <= shifts_done_counter + 1'b1; - else - shifts_done_counter <= shifts_done_counter; - end - end - end - - assign dps_changed_valid = (dps_current_state == DPS_CHANGED); - assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED); - assign up_dn = usr_up_dn; - assign gnd = 1'b0; - - //cnt select luts (5) - generic_lcell_comb lcell_cnt_sel_0 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[0])); - defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA; - defparam lcell_cnt_sel_0.dont_touch = "on"; - defparam lcell_cnt_sel_0.family = device_family; - generic_lcell_comb lcell_cnt_sel_1 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[1])); - defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC; - defparam lcell_cnt_sel_1.dont_touch = "on"; - defparam lcell_cnt_sel_1.family = device_family; - generic_lcell_comb lcell_cnt_sel_2 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[2])); - defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0; - defparam lcell_cnt_sel_2.dont_touch = "on"; - defparam lcell_cnt_sel_2.family = device_family; - generic_lcell_comb lcell_cnt_sel_3 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[3])); - defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00; - defparam lcell_cnt_sel_3.dont_touch = "on"; - defparam lcell_cnt_sel_3.family = device_family; - generic_lcell_comb lcell_cnt_sel_4 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[4])); - defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000; - defparam lcell_cnt_sel_4.dont_touch = "on"; - defparam lcell_cnt_sel_4.family = device_family; - - -endmodule - -module generic_lcell_comb -#( - //parameter - parameter family = "Stratix V", - parameter lut_mask = 64'hAAAAAAAAAAAAAAAA, - parameter dont_touch = "on" -) ( - - input dataa, - input datab, - input datac, - input datad, - input datae, - input dataf, - - output combout -); - - generate - if (family == "Stratix V") - begin - stratixv_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Arria V") - begin - arriav_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Arria V GZ") - begin - arriavgz_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Cyclone V") - begin - cyclonev_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - endgenerate -endmodule diff --git a/target/pocket/pll_reconfig/altera_pll_reconfig_top.v b/target/pocket/pll_reconfig/altera_pll_reconfig_top.v deleted file mode 100644 index 2cf9ce5..0000000 --- a/target/pocket/pll_reconfig/altera_pll_reconfig_top.v +++ /dev/null @@ -1,428 +0,0 @@ -// (C) 2001-2022 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -`timescale 1ps/1ps - -module altera_pll_reconfig_top -#( - parameter reconf_width = 64, - parameter device_family = "Stratix V", - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - - parameter ROM_ADDR_WIDTH = 9, - parameter ROM_DATA_WIDTH = 32, - parameter ROM_NUM_WORDS = 512, - - parameter ENABLE_MIF = 0, - parameter MIF_FILE_NAME = "", - - parameter ENABLE_BYTEENABLE = 0, - parameter BYTEENABLE_WIDTH = 4, - parameter WAIT_FOR_LOCK = 1 -) ( - - //input - input wire mgmt_clk, - input wire mgmt_reset, - - - //conduits - output wire [reconf_width-1:0] reconfig_to_pll, - input wire [reconf_width-1:0] reconfig_from_pll, - - // user data (avalon-MM slave interface) - output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata, - output wire mgmt_waitrequest, - input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address, - input wire mgmt_read, - input wire mgmt_write, - input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata, - - //conditional input - input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable -); - -localparam NM28_START_REG = 6'b000010; -localparam NM20_START_REG = 9'b000000000; -localparam NM20_MIFSTART_ADDR = 9'b000010000; - -localparam MIF_STATE_DONE = 2'b00; -localparam MIF_STATE_START = 2'b01; -localparam MIF_STATE_BUSY = 2'b10; - -wire mgmt_byteenable_write; -assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? - ((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : - mgmt_write; - -generate -if (device_family == "Arria 10") -begin:nm20_reconfig - if(ENABLE_MIF == 1) - begin:mif_reconfig_20nm // Generate Reconfig with MIF - - // MIF-related regs/wires - reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; - reg reconfig_mgmt_read; - reg reconfig_mgmt_write; - reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; - wire reconfig_mgmt_waitrequest; - wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; - - wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; - wire mif_busy; - wire mif2reconfig_read; - wire mif2reconfig_write; - wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - reg mif_select; - //wire mif_user_start; // start signal provided by user to start mif - //reg user_start; - - reg [1:0] mif_curstate; - reg [1:0] mif_nextstate; - - wire mif_start; //start signal to mif reader - - assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start; - // Don't output readdata if MIF streaming is taking place - assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; - - //user must lower this by the time mif streaming is done - suggest to lower after 1 cycle - assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR); - - //mif base addr is initially specified by the user - assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0]; - - //MIF statemachine - always @(posedge mgmt_clk) - begin - if(mgmt_reset) - mif_curstate <= MIF_STATE_DONE; - else - mif_curstate <= mif_nextstate; - end - - always @(*) - begin - case (mif_curstate) - MIF_STATE_DONE: - begin - if(mif_start) - mif_nextstate <= MIF_STATE_START; - else - mif_nextstate <= MIF_STATE_DONE; - end - MIF_STATE_START: - begin - mif_nextstate <= MIF_STATE_BUSY; - end - MIF_STATE_BUSY: - begin - if(mif_busy) - mif_nextstate <= MIF_STATE_BUSY; - else - mif_nextstate <= MIF_STATE_DONE; - end - endcase - end - - //Mif muxes - always @(*) - begin - if (mgmt_reset) - begin - reconfig_mgmt_addr <= 0; - reconfig_mgmt_read <= 0; - reconfig_mgmt_write <= 0; - reconfig_mgmt_writedata <= 0; - //user_start <= 0; - end - else - begin - reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; - reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; - reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; - reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; - //user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0; - end - end - - always @(*) - begin - if (mgmt_reset) - begin - mif_select <= 0; - end - else - begin - mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0; - end - end - - twentynm_pll_reconfig_mif_reader - #( - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS), - .DEVICE_FAMILY(device_family), - .ENABLE_MIF(ENABLE_MIF), - .MIF_FILE_NAME(MIF_FILE_NAME) - ) twentynm_pll_reconfig_mif_reader_inst0 ( - .mif_clk(mgmt_clk), - .mif_rst(mgmt_reset), - - //Altera_PLL Reconfig interface - //inputs - .reconfig_waitrequest(reconfig_mgmt_waitrequest), - //.reconfig_read_data(reconfig_mgmt_readdata), - //outputs - .reconfig_write_data(mif2reconfig_writedata), - .reconfig_addr(mif2reconfig_addr), - .reconfig_write(mif2reconfig_write), - .reconfig_read(mif2reconfig_read), - - //MIF Ctrl Interface - //inputs - .mif_base_addr(mif_base_addr), - .mif_start(mif_start), - //outputs - .mif_busy(mif_busy) - ); - - // ------ END MIF-RELATED MANAGEMENT ------ - - twentynm_iopll_reconfig_core - #( - .WAIT_FOR_LOCK(WAIT_FOR_LOCK) - ) twentynm_iopll_reconfig_core_inst ( - // Inputs - .mgmt_clk(mgmt_clk), - .mgmt_rst_n(~mgmt_reset), - .mgmt_read(reconfig_mgmt_read), - .mgmt_write(reconfig_mgmt_write), - .mgmt_address(reconfig_mgmt_addr), - .mgmt_writedata(reconfig_mgmt_writedata), - - // Outputs - .mgmt_readdata(reconfig_mgmt_readdata), - .mgmt_waitrequest(reconfig_mgmt_waitrequest), - - // PLL Conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) - ); - - end // End generate reconfig with MIF - else - begin:reconfig_core_20nm - twentynm_iopll_reconfig_core - #( - .WAIT_FOR_LOCK(WAIT_FOR_LOCK) - ) twentynm_iopll_reconfig_core_inst ( - // Inputs - .mgmt_clk(mgmt_clk), - .mgmt_rst_n(~mgmt_reset), - .mgmt_read(mgmt_read), - .mgmt_write(mgmt_byteenable_write), - .mgmt_address(mgmt_address), - .mgmt_writedata(mgmt_writedata), - - // Outputs - .mgmt_readdata(mgmt_readdata), - .mgmt_waitrequest(mgmt_waitrequest), - - // PLL Conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) - ); - end -end // 20nm reconfig -else -begin:NM28_reconfig - if (ENABLE_MIF == 1) - begin:mif_reconfig // Generate Reconfig with MIF - - // MIF-related regs/wires - reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; - reg reconfig_mgmt_read; - reg reconfig_mgmt_write; - reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; - wire reconfig_mgmt_waitrequest; - wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; - - wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; - wire mif2reconfig_busy; - wire mif2reconfig_read; - wire mif2reconfig_write; - wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - reg mif_select; - reg user_start; - - wire reconfig2mif_start_out; - - assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start; - // Don't output readdata if MIF streaming is taking place - assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; - - always @(posedge mgmt_clk) - begin - if (mgmt_reset) - begin - reconfig_mgmt_addr <= 0; - reconfig_mgmt_read <= 0; - reconfig_mgmt_write <= 0; - reconfig_mgmt_writedata <= 0; - user_start <= 0; - end - else - begin - reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; - reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; - reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; - reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; - user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0; - end - end - - always @(*) - begin - if (mgmt_reset) - begin - mif_select <= 0; - end - else - begin - mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0; - end - end - - altera_pll_reconfig_mif_reader - #( - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS), - .DEVICE_FAMILY(device_family), - .ENABLE_MIF(ENABLE_MIF), - .MIF_FILE_NAME(MIF_FILE_NAME) - ) altera_pll_reconfig_mif_reader_inst0 ( - .mif_clk(mgmt_clk), - .mif_rst(mgmt_reset), - - //Altera_PLL Reconfig interface - //inputs - .reconfig_busy(reconfig_mgmt_waitrequest), - .reconfig_read_data(reconfig_mgmt_readdata), - //outputs - .reconfig_write_data(mif2reconfig_writedata), - .reconfig_addr(mif2reconfig_addr), - .reconfig_write(mif2reconfig_write), - .reconfig_read(mif2reconfig_read), - - //MIF Ctrl Interface - //inputs - .mif_base_addr(mif_base_addr), - .mif_start(reconfig2mif_start_out), - //outputs - .mif_busy(mif2reconfig_busy) - ); - - // ------ END MIF-RELATED MANAGEMENT ------ - - - altera_pll_reconfig_core - #( - .reconf_width(reconf_width), - .device_family(device_family), - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS) - ) altera_pll_reconfig_core_inst0 ( - //inputs - .mgmt_clk(mgmt_clk), - .mgmt_reset(mgmt_reset), - - //PLL interface conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - - //User data outputs - .mgmt_readdata(reconfig_mgmt_readdata), - .mgmt_waitrequest(reconfig_mgmt_waitrequest), - - //User data inputs - .mgmt_address(reconfig_mgmt_addr), - .mgmt_read(reconfig_mgmt_read), - .mgmt_write(reconfig_mgmt_write), - .mgmt_writedata(reconfig_mgmt_writedata), - - // other - .mif_start_out(reconfig2mif_start_out), - .mif_base_addr(mif_base_addr) - ); - - end // End generate reconfig with MIF - else - begin:reconfig_core // Generate Reconfig core only - - wire reconfig2mif_start_out; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - - altera_pll_reconfig_core - #( - .reconf_width(reconf_width), - .device_family(device_family), - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS) - ) altera_pll_reconfig_core_inst0 ( - //inputs - .mgmt_clk(mgmt_clk), - .mgmt_reset(mgmt_reset), - - //PLL interface conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - - //User data outputs - .mgmt_readdata(mgmt_readdata), - .mgmt_waitrequest(mgmt_waitrequest), - - //User data inputs - .mgmt_address(mgmt_address), - .mgmt_read(mgmt_read), - .mgmt_write(mgmt_byteenable_write), - .mgmt_writedata(mgmt_writedata), - - // other - .mif_start_out(reconfig2mif_start_out), - .mif_base_addr(mif_base_addr) - ); - - - end // End generate reconfig core only -end // End 28nm Reconfig -endgenerate - -endmodule - diff --git a/target/pocket/pll_reconfig/altera_std_synchronizer.v b/target/pocket/pll_reconfig/altera_std_synchronizer.v deleted file mode 100644 index 47135c2..0000000 --- a/target/pocket/pll_reconfig/altera_std_synchronizer.v +++ /dev/null @@ -1,159 +0,0 @@ -// (C) 2001-2022 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/21.1std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $ -// $Revision: #1 $ -// $Date: 2020/06/22 $ -// $Author: psgswbuild $ -//----------------------------------------------------------------------------- -// -// File: altera_std_synchronizer.v -// -// Abstract: Single bit clock domain crossing synchronizer. -// Composed of two or more flip flops connected in series. -// Random metastable condition is simulated when the -// __ALTERA_STD__METASTABLE_SIM macro is defined. -// Use +define+__ALTERA_STD__METASTABLE_SIM argument -// on the Verilog simulator compiler command line to -// enable this mode. In addition, dfine the macro -// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output -// with every metastable event generated in the synchronizer. -// -// Copyright (C) Altera Corporation 2009, All Rights Reserved -//----------------------------------------------------------------------------- - -`timescale 1ns / 1ns - -module altera_std_synchronizer ( - clk, - reset_n, - din, - dout - ); - - parameter depth = 3; // This value must be >= 2 ! - - input clk; - input reset_n; - input din; - output dout; - - // QuartusII synthesis directives: - // 1. Preserve all registers ie. do not touch them. - // 2. Do not merge other flip-flops with synchronizer flip-flops. - // QuartusII TimeQuest directives: - // 1. Identify all flip-flops in this module as members of the synchronizer - // to enable automatic metastability MTBF analysis. - // 2. Cut all timing paths terminating on data input pin of the first flop din_s1. - - (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]\" "} *) reg din_s1; - - (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg; - - //synthesis translate_off - initial begin - if (depth <2) begin - $display("%m: Error: synchronizer length: %0d less than 2.", depth); - end - end - - // the first synchronizer register is either a simple D flop for synthesis - // and non-metastable simulation or a D flop with a method to inject random - // metastable events resulting in random delay of [0,1] cycles - -`ifdef __ALTERA_STD__METASTABLE_SIM - - reg[31:0] RANDOM_SEED = 123456; - wire next_din_s1; - wire dout; - reg din_last; - reg random; - event metastable_event; // hook for debug monitoring - - initial begin - $display("%m: Info: Metastable event injection simulation mode enabled"); - end - - always @(posedge clk) begin - if (reset_n == 0) - random <= $random(RANDOM_SEED); - else - random <= $random; - end - - assign next_din_s1 = (din_last ^ din) ? random : din; - - always @(posedge clk or negedge reset_n) begin - if (reset_n == 0) - din_last <= 1'b0; - else - din_last <= din; - end - - always @(posedge clk or negedge reset_n) begin - if (reset_n == 0) - din_s1 <= 1'b0; - else - din_s1 <= next_din_s1; - end - -`else - - //synthesis translate_on - always @(posedge clk or negedge reset_n) begin - if (reset_n == 0) - din_s1 <= 1'b0; - else - din_s1 <= din; - end - //synthesis translate_off - -`endif - -`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE - always @(*) begin - if (reset_n && (din_last != din) && (random != din)) begin - $display("%m: Verbose Info: metastable event @ time %t", $time); - ->metastable_event; - end - end -`endif - - //synthesis translate_on - - // the remaining synchronizer registers form a simple shift register - // of length depth-1 - generate - if (depth < 3) begin - always @(posedge clk or negedge reset_n) begin - if (reset_n == 0) - dreg <= {depth-1{1'b0}}; - else - dreg <= din_s1; - end - end else begin - always @(posedge clk or negedge reset_n) begin - if (reset_n == 0) - dreg <= {depth-1{1'b0}}; - else - dreg <= {dreg[depth-3:0], din_s1}; - end - end - endgenerate - - assign dout = dreg[depth-2]; - -endmodule - - - diff --git a/target/pocket/save_state_controller.sv b/target/pocket/save_state_controller.sv index b4d9ecf..52bfa65 100644 --- a/target/pocket/save_state_controller.sv +++ b/target/pocket/save_state_controller.sv @@ -129,7 +129,7 @@ module save_state_controller ( ); defparam fifo_load.intended_device_family = "Cyclone V", fifo_load.lpm_numwords = 4096, fifo_load.lpm_showahead = "OFF", fifo_load.lpm_type = "dcfifo_mixed_widths", - fifo_load.lpm_width = 32, fifo_load.lpm_widthu = 12, + fifo_load.lpm_width = 32, fifo_load.lpm_widthu = 12, fifo_load.ram_block_type = "M10K", fifo_load.lpm_widthu_r = 11, fifo_load.lpm_width_r = 64, fifo_load.overflow_checking = "OFF", fifo_load.rdsync_delaypipe = 5, fifo_load.underflow_checking = "ON", fifo_load.use_eab = "ON", fifo_load.wrsync_delaypipe = 5, fifo_load.write_aclr_synch = "ON"; @@ -163,7 +163,7 @@ module save_state_controller ( ); defparam fifo_save.intended_device_family = "Cyclone V", fifo_save.lpm_numwords = 4, fifo_save.lpm_showahead = "OFF", fifo_save.lpm_type = "dcfifo_mixed_widths", - fifo_save.lpm_width = 64, fifo_save.lpm_widthu = 2, fifo_save.lpm_widthu_r = 3, + fifo_save.lpm_width = 64, fifo_save.lpm_widthu = 2, fifo_save.ram_block_type = "M10K", fifo_save.lpm_widthu_r = 3, fifo_save.lpm_width_r = 32, fifo_save.overflow_checking = "ON", fifo_save.rdsync_delaypipe = 5, fifo_save.underflow_checking = "ON", fifo_save.use_eab = "ON", fifo_save.wrsync_delaypipe = 5; diff --git a/target/pocket/stp1.stp b/target/pocket/stp1.stp index 445325a..030e751 100644 --- a/target/pocket/stp1.stp +++ b/target/pocket/stp1.stp @@ -148,7 +148,7 @@ - + @@ -1286,7 +1286,7 @@ - + @@ -3801,7 +3801,7 @@ - + @@ -4501,7 +4501,7 @@ - + @@ -5254,7 +5254,7 @@ - + @@ -7342,7 +7342,7 @@ - + @@ -9558,7 +9558,7 @@ - + @@ -12366,7 +12366,7 @@ - + @@ -14279,7 +14279,7 @@ - + @@ -16173,7 +16173,7 @@ - + diff --git a/target/pocket/sync_fifo.sv b/target/pocket/sync_fifo.sv index 895e72e..ce73e54 100644 --- a/target/pocket/sync_fifo.sv +++ b/target/pocket/sync_fifo.sv @@ -58,6 +58,7 @@ module sync_fifo #( .wrusedw() ); defparam dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 4, + dcfifo_component. ram_block_type = "M10K", dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = WIDTH, dcfifo_component.lpm_widthu = 2, dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 5, diff --git a/tools/reverse_bits.exe b/tools/reverse_bits.exe new file mode 100644 index 0000000..ffe650b Binary files /dev/null and b/tools/reverse_bits.exe differ