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‎latest/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/index.html‎

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window.location.replace("../../../../../../../rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/" + window.location.hash);
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Redirecting to <a href="../../../../../../../rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/">../../../../../../../rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/</a>...
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‎rel-25.1/common/templates/linux_driver_template/index.html‎

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<h1 id="host-attach-dfl-fpga-management-engine-ip-driver"><strong>Host Attach DFL FPGA Management Engine IP Driver</strong><a class="headerlink" href="#host-attach-dfl-fpga-management-engine-ip-driver" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>June 25, 2025</strong> </p>
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<p>Last updated: <strong>July 07, 2025</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
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<p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
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<h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">June 25, 2025</span>
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">July 7, 2025</span>
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‎rel-25.1/ed-demo-list/ed-list/index.html‎

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<td align="center">Embedded</td>
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<td align="left">Agilex 5 E-Series Premium Development Kit</td>
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<td align="left">Demonstrate a simple Hello World and On-Chip Memory Test application based on Nios V/c processor.</td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/niosv/niosv_c/niosv_c_helloworld_ocm_mem_test/" target="_blank">Agilex 5 FPGA - Helloworld and OCM memory test design on Nios® V/c Processor</a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/niosv/niosv_c/niosv_c_helloworld_ocm_mem_test/ug-helloworld-ocm-mem-test-agx5e-premium/" target="_blank">Agilex 5 FPGA - Helloworld and OCM memory test design on Nios® V/c Processor</a></td>
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</tr>
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<td align="center">Agilex 5 FPGA - Nios® V/g Processor OCM to OCM</td>
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<td align="center">Embedded</td>
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<td align="left">Agilex 5 E-Series Premium Development Kit</td>
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<td align="left">Provides a simple Baseline Nios V GHRD that comprises of On-Chip Memory, Parallel Input/Output, JTAG UART and System IP core.</td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/niosv/niosv_m/niosv_m_baseline_ghrd/" target="_blank">Agilex 5 FPGA- Nios® V/m Processor Baseline GHRD Design</a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/niosv/niosv_m/niosv_m_baseline_ghrd/ug-baseline-ghrd-agx5e-premium/" target="_blank">Agilex 5 FPGA- Nios® V/m Processor Baseline GHRD Design</a></td>
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</tr>
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<td align="center">Agilex 5 FPGA- Nios® V/g TinyML LiteRT for Microcontroller Design</td>
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<td align="center">Agilex 5</td>
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<td align="center">Embedded</td>
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<td align="left">Agilex 5 E-Series Premium Development Kit</td>
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<td align="left">Demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor.</td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/niosv/niosv_g/tinyml_liteRT/" target="_blank">Agilex 5 FPGA- Nios® V/g TinyML LiteRT for Microcontroller Design</a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/niosv/niosv_g/tinyml_liteRT/ug-tinyml-liteRT-agx5e-premium/" target="_blank">Agilex 5 FPGA- Nios® V/g TinyML LiteRT for Microcontroller Design</a></td>
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<td align="center">Agilex 7 FPGA- Nios® V/g TinyML LiteRT for Microcontroller Design</td>
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<td align="center">Agilex 7</td>
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<td align="center">Embedded</td>
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<td align="left">Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile (DK-DEV-AGF014EA)</td>
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<td align="left">Demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor.</td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/f-series/fpga/niosv/niosv_g/tinyml_liteRT/" target="_blank"> Agilex 7 FPGA- Nios® V/g TinyML LiteRT for Microcontroller Design </a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/f-series/fpga/niosv/niosv_g/tinyml_liteRT/ug-tinyml-litert-agx7f-fpga/" target="_blank"> Agilex 7 FPGA- Nios® V/g TinyML LiteRT for Microcontroller Design </a></td>
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<td align="center">Agilex 7 FPGA- Nios® V/g Processor Floating Point Unit (FPU) Design</td>
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<td align="center">Agilex 7</td>
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<td align="center">Embedded</td>
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<td align="left">Agilex 7 Transceiver-SoC Development kit P-Tile E-Tile production (DK-SI-AGF014EB)</td>
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<td align="left">Demonstrate a floating point application using Nios V/g processor FPU.</td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/f-series/soc/niosv/niosv_g/fpu_test/" target="_blank"> Agilex 7 FPGA- Nios® V/g Processor Floating Point Unit (FPU) Design </a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/f-series/soc/niosv/niosv_g/fpu_test/ug-fpu-agx7f-fpga/" target="_blank"> Agilex 7 FPGA- Nios® V/g Processor Floating Point Unit (FPU) Design </a></td>
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<td align="center">Agilex 3 FPGA- Nios® V/m Processor Baseline GHRD Design</td>
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">June 16, 2025</span>
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">July 7, 2025</span>
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‎rel-25.1/embedded-designs/agilex-5/e-series/modular/drive-on-chip/doc-crc/index.html‎

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<div class="highlight"><pre><span></span><code><a id="__codelineno-4-1" name="__codelineno-4-1" href="#__codelineno-4-1"></a>git clone https://github.com/altera-fpga/altera-ros2.git
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<a id="__codelineno-4-2" name="__codelineno-4-2" href="#__codelineno-4-2"></a>cd altera-ros2
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<a id="__codelineno-4-3" name="__codelineno-4-3" href="#__codelineno-4-3"></a>docker buildx build -f .docker/Dockerfile -t altera-ros2 .
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<a id="__codelineno-4-3" name="__codelineno-4-3" href="#__codelineno-4-3"></a>docker build -f .docker/Dockerfile -t altera-ros2 .
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</code></pre></div>
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<div class="highlight"><pre><span></span><code><a id="__codelineno-5-1" name="__codelineno-5-1" href="#__codelineno-5-1"></a>docker image ls
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">June 25, 2025</span>
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‎rel-25.1/embedded-designs/agilex-5/e-series/modular/drive-on-chip/doc-funct-safety/index.html‎

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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">June 25, 2025</span>
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‎rel-25.1/embedded-designs/agilex-5/e-series/modular/drive-on-chip/doc-plc/index.html‎

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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">June 25, 2025</span>
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">July 7, 2025</span>
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‎rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/images/cv-ds-boot-config.png‎

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‎rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/images/cv-ds-boot-spl-debugger.png‎

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