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Author: Jdavidbr-alt

rel-24.3.1/common/templates/linux_driver_template/index.html

@@ -3370,7 +3370,7 @@
 
 
 <h1 id="host-attach-dfl-fpga-management-engine-ip-driver"><strong>Host Attach DFL FPGA Management Engine IP Driver</strong><a class="headerlink" href="#host-attach-dfl-fpga-management-engine-ip-driver" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
 <p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
 <h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
@@ -3442,7 +3442,7 @@ <h2 id="example-designs"><strong>Example Designs</strong><a class="headerlink" h
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/embedded-designs/agilex-7/m-series/pcie_rp/ug-pcie_rp-agx7m-hbm2e/index.html

@@ -2913,6 +2913,13 @@
     Helpful Reference Documentation
   </a>
 
+</li>
+      
+        <li class="md-nav__item">
+  <a href="#build-agilex-pcie-root-port" class="md-nav__link">
+    Build Agilex PCIe Root Port
+  </a>
+  
 </li>
 
         <li class="md-nav__item">
@@ -3456,6 +3463,13 @@
     Helpful Reference Documentation
   </a>
 
+</li>
+      
+        <li class="md-nav__item">
+  <a href="#build-agilex-pcie-root-port" class="md-nav__link">
+    Build Agilex PCIe Root Port
+  </a>
+  
 </li>
 
         <li class="md-nav__item">
@@ -3568,7 +3582,7 @@ <h2 id="required-components">Required Components<a class="headerlink" href="#req
 </li>
 <li><a href="https://github.com/altera-fpga/agilex7-ed-pcie-rp/releases/tag/24.3-1">Pre-compiled Software/Firmware</a>.</li>
 <li>Tools and software.<ul>
-<li>System with supported Linux distribution with Ubuntu 20.04 (LTS)</li>
+<li>System with supported Linux distribution with Ubuntu 22.04 (LTS)</li>
 <li>Intel ® Quartus ®Prime Design Suite software 24.3 version </li>
 <li>Serial terminal application such as Putty</li>
 </ul>
@@ -3588,6 +3602,13 @@ <h2 id="helpful-reference-documentation">Helpful Reference Documentation<a class
 <ul>
 <li><a href="https://www.intel.com/content/www/us/en/docs/programmable/683501/24-3/about-the-r-tile-streaming-fpga-ip-for.html">R-Tile Avalon ® Intel ® FPGA IP for PCI Express</a></li>
 </ul>
+<h2 id="build-agilex-pcie-root-port">Build Agilex PCIe Root Port<a class="headerlink" href="#build-agilex-pcie-root-port" title="Permanent link">&para;</a></h2>
+<p>Here are the steps to build either SW and HW files:</p>
+<ul>
+<li><a href="https://github.com/altera-fpga/agilex7-ed-pcie-rp/blob/main/src/sw/README.md">SW_Readme</a></li>
+<li><a href="https://github.com/altera-fpga/agilex7-ed-pcie-rp/tree/main/src/hw">HW_Readme</a></li>
+</ul>
+<p>Both links show how to build the files needed for the project, acording with the <a href="https://github.com/altera-opensource/gsrd-socfpga">Intel® SoC FPGA Golden Software Reference Design (GSRD)</a></p>
 <h2 id="hardware-description">Hardware Description<a class="headerlink" href="#hardware-description" title="Permanent link">&para;</a></h2>
 <p><a class="glightbox" href="../images/RPDiagram.png" data-type="image" data-width="100%" data-height="auto" data-desc-position="bottom"><img alt="image-20241214093228785" src="../images/RPDiagram.png" /></a></p>
 <h3 id="memory-map">Memory Map<a class="headerlink" href="#memory-map" title="Permanent link">&para;</a></h3>
@@ -4721,20 +4742,52 @@ <h3 id="fio-transactions">fio transactions<a class="headerlink" href="#fio-trans
 </code></pre></div>
 <div class="admonition note">
 <p class="admonition-title">Note</p>
-<p>You could change the parameter <mark>--numjobs=</mark> with values 4, 8, 16 or 20, i.e.:</p>
+<p>You could change the parameters <mark>--size=<strong>xG</strong></mark> with 2G and 8G, <mark>--rw=<strong>x</strong></mark> write and read, <mark>--numjobs=<strong>x</strong></mark> with values 4, 8, 16 or 20, i.e.:</p>
 <ul>
-<li>fio --filename=/dev/nvme0n1 --rw=write --gtod_reduce=1 --blocksize=64k --size=2G --iodepth=2 --group_reporting --name=myjob --ioengine=libaio <mark>--numjobs=4</mark></li>
+<li>fio --filename=/dev/nvme0n1 --rw= <mark><strong>write</strong></mark> --gtod_reduce=1 --blocksize=64k --size= <mark><strong>2G</strong></mark> --iodepth=2 --group_reporting --name=myjob --ioengine=libaio --numjobs= <mark><strong>4</strong></mark></li>
 </ul>
 <ul>
-<li>fio --filename=/dev/nvme0n1 --rw=read --gtod_reduce=1 --blocksize=64k --size=2G --iodepth=2 --group_reporting --name=myjob --ioengine=libaio <mark>--numjobs=8</mark></li>
+<li>fio --filename=/dev/nvme0n1 --rw= <mark><strong>read</strong></mark> --gtod_reduce=1 --blocksize=64k --size= <mark><strong>2G</strong></mark> --iodepth=2 --group_reporting --name=myjob --ioengine=libaio --numjobs= <mark><strong>8</strong></mark></li>
 </ul>
 <ul>
-<li>fio --filename=/dev/nvme0n1 --rw=write --gtod_reduce=1 --blocksize=64k --size=2G --iodepth=2 --group_reporting --name=myjob --ioengine=libaio <mark>--numjobs=16</mark></li>
+<li>fio --filename=/dev/nvme0n1 --rw= <mark><strong>write</strong></mark> --gtod_reduce=1 --blocksize=64k --size= <mark><strong>8G</strong></mark> --iodepth=2 --group_reporting --name=myjob --ioengine=libaio --numjobs= <mark><strong>16</strong></mark></li>
 </ul>
 <ul>
-<li>fio --filename=/dev/nvme0n1 --rw=read --gtod_reduce=1 --blocksize=64k --size=2G --iodepth=2 --group_reporting --name=myjob --ioengine=libaio <mark>--numjobs=20</mark></li>
+<li>fio --filename=/dev/nvme0n1 --rw= <mark><strong>read</strong></mark> --gtod_reduce=1 --blocksize=64k --size= <mark><strong>8G</strong></mark> --iodepth=2 --group_reporting --name=myjob --ioengine=libaio --numjobs= <mark><strong>20</strong></mark></li>
 </ul>
 </div>
+<p>Example of the values that we got for the Wr &amp; Rd fio transactions using the recommended commands:</p>
+<table>
+<thead>
+<tr>
+<th>numjobs</th>
+<th>Wr</th>
+<th>Rd</th>
+</tr>
+</thead>
+<tbody>
+<tr>
+<td>4</td>
+<td>1109 MB/S</td>
+<td>1360 MB/S</td>
+</tr>
+<tr>
+<td>8</td>
+<td>1407 MB/S</td>
+<td>1967 MB/S</td>
+</tr>
+<tr>
+<td>16</td>
+<td>1544 MB/S</td>
+<td>2225 MB/S</td>
+</tr>
+<tr>
+<td>20</td>
+<td>1697 MB/S</td>
+<td>2284 MB/S</td>
+</tr>
+</tbody>
+</table>
 <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href="#notices-disclaimers" title="Permanent link">&para;</a></h2>
 <p>Altera® Corporation technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Performance varies by use, configuration and other factors. Your costs and results may vary. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Altera or Intel products described herein. You agree to grant Altera Corporation a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document, with the sole exception that you may publish an unmodified copy. You may create software implementations based on this document and in compliance with the foregoing that are intended to execute on the Altera or Intel product(s) referenced in this document. No rights are granted to create modifications or derivatives of this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Altera disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. You are responsible for safety of the overall system, including compliance with applicable safety-related requirements or standards. © Altera Corporation. Altera, the Altera logo, and other Altera marks are trademarks of Altera Corporation. Other names and brands may be claimed as the property of others.</p>
 
@@ -4743,7 +4796,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">January 8, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/linux-dfl/dfl/dfl/index.html

@@ -3463,7 +3463,7 @@
 
 
 <h1 id="device-feature-list-driver"><strong>Device Feature List Driver</strong><a class="headerlink" href="#device-feature-list-driver" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/fpga/dfl.c?h=master">Upstreamed</a></p>
 <p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
 <h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
@@ -3523,7 +3523,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/linux-dfl/dfl_afu/dfl_afu/index.html

@@ -3477,7 +3477,7 @@
 
 
 <h1 id="accelerator-functional-unit-aka-workload-driver-for-host-attach"><strong>Accelerator Functional Unit (aka workload) Driver For Host Attach</strong><a class="headerlink" href="#accelerator-functional-unit-aka-workload-driver-for-host-attach" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
 <p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
 <h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
@@ -3541,7 +3541,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/linux-dfl/dfl_emif/dfl_emif/index.html

@@ -3491,7 +3491,7 @@
 
 
 <h1 id="host-attach-memory-subsystem-ip-driver"><strong>Host Attach Memory Subsystem IP Driver</strong><a class="headerlink" href="#host-attach-memory-subsystem-ip-driver" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/memory/dfl-emif.c?h=master">Upstreamed</a></p>
 <p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
 <h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
@@ -3560,7 +3560,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/linux-dfl/dfl_fme/dfl_fme/index.html

@@ -3477,7 +3477,7 @@
 
 
 <h1 id="host-attach-dfl-fpga-management-engine-ip-driver"><strong>Host Attach DFL FPGA Management Engine IP Driver</strong><a class="headerlink" href="#host-attach-dfl-fpga-management-engine-ip-driver" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
 <p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
 <h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
@@ -3562,7 +3562,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/linux-dfl/dfl_pci/dfl_pci/index.html

@@ -3477,7 +3477,7 @@
 
 
 <h1 id="dfl-pci-express-subsystem-ip-driver"><strong>DFL PCI Express Subsystem IP Driver</strong><a class="headerlink" href="#dfl-pci-express-subsystem-ip-driver" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/fpga/dfl-pci.c?h=master">Upstreamed</a></p>
 <p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
 <h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
@@ -3538,7 +3538,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/linux-dfl/intel_m10_bmc_core/intel_m10_bmc_core/index.html

@@ -3463,7 +3463,7 @@
 
 
 <h1 id="max-10-board-management-controller-driver"><strong>Max® 10 Board Management Controller Driver</strong><a class="headerlink" href="#max-10-board-management-controller-driver" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mfd?h=master">Upstreamed</a></p>
 <ul>
 <li><code>intel-m10-bmc-log</code> is not upstreamed.</li>
@@ -3563,7 +3563,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/linux-dfl/ptp_dfl_tod/ptp_dfl_tod/index.html

@@ -3463,7 +3463,7 @@
 
 
 <h1 id="ethernet-ieee-1588-time-of-day-clock-fpga-ip-driver-for-host-attach"><strong>Ethernet IEEE 1588 Time of Day Clock FPGA IP Driver for Host Attach</strong><a class="headerlink" href="#ethernet-ieee-1588-time-of-day-clock-fpga-ip-driver-for-host-attach" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ptp/ptp_dfl_tod.c?h=master">Upstreamed</a></p>
 <h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
 <p>This page provides an overview of the Time-of-day driver for the Time of Day Clock FPGA IP that is used in the 1588PTP Design examples.  The Time of Day Clock FPGA IP is exposed as PTP Hardware Clock (PHC) device to the Linux PTP stack to synchronize the system clock to its ToD information using phc2sys utility of the Linux PTP stack.</p>
@@ -3503,7 +3503,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created:

rel-24.3.1/linux-dfl/uart_16550/uart_16550/index.html

@@ -3477,7 +3477,7 @@
 
 
 <h1 id="altera-16550-compatible-uart-core-driver-for-host-attach"><strong>Altera 16550 Compatible UART Core Driver for Host Attach</strong><a class="headerlink" href="#altera-16550-compatible-uart-core-driver-for-host-attach" title="Permanent link">&para;</a></h1>
-<p>Last updated: <strong>February 13, 2025</strong> </p>
+<p>Last updated: <strong>February 20, 2025</strong> </p>
 <p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/serial/8250/8250_dfl.c?h=master">Upstreamed</a></p>
 <h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
 <p>This driver for the 16550 Compatible UART Core to establish TTY communications to FPGA through PCIe.</p>
@@ -3516,7 +3516,7 @@ <h2 id="notices-disclaimers">Notices &amp; Disclaimers<a class="headerlink" href
   <small>
 
       Last update:
-      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 13, 2025</span>
+      <span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">February 20, 2025</span>
 
         <br>
         Created: