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‎rel-24.2/common/templates/linux_driver_template/index.html‎

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<h1 id="host-attach-dfl-fpga-management-engine-ip-driver"><strong>Host Attach DFL FPGA Management Engine IP Driver</strong><a class="headerlink" href="#host-attach-dfl-fpga-management-engine-ip-driver" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 15, 2024</strong> </p>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
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<p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
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<h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
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<td align="center">Golden System Reference Design (GSRD)</td>
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<td align="center">Agilex™ 5</td>
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<td align="center">Agilex 5</td>
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<td align="center">Embedded</td>
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<td align="left">* Agilex™ 5 E-Series Premium Development Kit</br> * Agilex™ 5 E-Series Modular Development Kit</td>
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<td align="left">* Agilex 5 E-Series Premium Development Kit</br> * Agilex 5 E-Series Modular Development Kit</td>
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<td align="left">Provides instructions on how to test a basic HPS example with software on the development kit</td>
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<td align="left">* <a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/">Agilex 5 E-Series Premium Development Kit GSRD User Guide</a></br>* <a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/">Agilex 5 E-Series Modular Development Kit GSRD User Guide</a></td>
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<td align="center">Golden System Reference Design (GSRD)</td>
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<td align="center">Agilex™ 5</td>
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<td align="center">Agilex 5</td>
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<td align="center">Embedded</td>
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<td align="left">Agilex™ 5 E-Series Universal Virtual Platforms</td>
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<td align="left">Agilex 5 E-Series Universal Virtual Platforms</td>
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<td align="left">Provides instructions on how to exercise several use cases in which HPS software is running on the Intel Simics simulator using virtual platforms</td>
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<td align="left">* <a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/common/virtual-platforms/linux-gsrd/ug-linux-gsrd-agilex5-virtual-platforms/">Agilex™ 5 Intel Simics Virtual Platform Example User Guide - Linux GSRD</a> </br>*<a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/common/virtual-platforms/zephyr-gsrd/ug-zephyr-gsrd-agilex5-virtual-platforms/">Agilex™ 5 Intel Simics Virtual Platform Example User Guide - Zephyr GSRD</a></td>
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<td align="left">* <a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/common/virtual-platforms/linux-gsrd/ug-linux-gsrd-agilex5-virtual-platforms/">Agilex 5 Intel Simics Virtual Platform Example User Guide - Linux GSRD</a> </br>*<a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/common/virtual-platforms/zephyr-gsrd/ug-zephyr-gsrd-agilex5-virtual-platforms/">Agilex 5 Intel Simics Virtual Platform Example User Guide - Zephyr GSRD</a></td>
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<td align="center">Golden Hardware Reference Design (GHRD) Boot Examples</td>
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<td align="center">Agilex™ 5</td>
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<td align="center">Agilex 5</td>
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<td align="center">Embedded</td>
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<td align="left">* Agilex™ 5 E-Series Premium Development Kit</br> * Agilex™ 5 E-Series Modular Development Kit</td>
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<td align="left">* Agilex 5 E-Series Premium Development Kit</br> * Agilex 5 E-Series Modular Development Kit</td>
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<td align="left">Provides instructions on how to build Linux systems from separate components</td>
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<td align="left">* <a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/">Agilex 5 E-Series Premium Development Kit GHRD Linux Boot Examples</a></br> * <a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/e-series/modulare/boot-examples/ug-linux-boot-agx5e-modular/">Agilex 5 E-Series Modular Development Kit GHRD Linux Boot Examples</a></td>
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<td align="center">HPS Remote System Update Example</td>
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<td align="left">Agilex™ 7 Transceiver-SoC Development kit P-Tile E-Tile production Linear power solution (DK-SI-AGF014EB)</td>
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<td align="left">Agilex 7 Transceiver-SoC Development kit P-Tile E-Tile production Linear power solution (DK-SI-AGF014EB)</td>
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<td align="left">Provides a complete Remote System Update example including build and execution</td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-7/f-series/soc/rsu/ug-rsu-agx7f-soc/">Agilex 7 HPS Remote System Update Example</a></td>
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<td align="center">HPS Multi-QSPI Remote System Update Example</td>
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<td align="left">Agilex 7 Transceiver-SoC Development kit P-Tile E-Tile production Linear power solution (DK-SI-AGF014EB)</td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-7/f-series/soc/rsu/ug-rsu-multiqspi-agx7f-soc/">Agilex 7 HPS Multi-QSPI Remote System Update Example</a></td>
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<td align="center">HPS Remote System Update Example</td>
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<td align="center">Stratix 10</td>
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<td align="left">Stratix® 10 SX SoC Development Kit H-Tile (DK-SOC-1SSX-H-D)</td>
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<td align="left">Stratix 10 SX SoC Development Kit H-Tile (DK-SOC-1SSX-H-D)</td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/stratix-10/sx/soc/rsu/ug-rsu-s10sx-soc/">Stratix 10 HPS Remote System Update Example</a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/e-series/premium/remote-debug/ug-remote-debug-agx5e-premium/">Agilex 5 FPGA Remote Debug Example</a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-7/f-series/soc/remote-debug/ug-remote-debug-agx7f-soc/">Agilex 7 FPGA Remote Debug Example</a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/stratix-10/sx/soc/remote-debug/ug-remote-debug-s10sx-soc/">Stratix 10 FPGA Remote Debug Example</a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-7/f-series/soc/emmc/ug-emmc-agx7f-soc/">Agilex 7 HPS eMMC Boot Example</a></td>
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<td align="left"><a href="https://altera-fpga.github.io/rel-24.2/embedded-designs/stratix-10/sx/soc/emmc/ug-emmc-s10sx-soc/">Stratix 10 HPS eMMC Boot Example</a></td>
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">October 8, 2024</span>
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‎rel-24.2/linux-dfl/dfl/dfl/index.html‎

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<h1 id="device-feature-list-driver"><strong>Device Feature List Driver</strong><a class="headerlink" href="#device-feature-list-driver" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/fpga/dfl.c?h=master">Upstreamed</a></p>
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<p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
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<h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
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<h1 id="accelerator-functional-unit-aka-workload-driver-for-host-attach"><strong>Accelerator Functional Unit (aka workload) Driver For Host Attach</strong><a class="headerlink" href="#accelerator-functional-unit-aka-workload-driver-for-host-attach" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 15, 2024</strong> </p>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
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‎rel-24.2/linux-dfl/dfl_emif/dfl_emif/index.html‎

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<h1 id="host-attach-memory-subsystem-ip-driver"><strong>Host Attach Memory Subsystem IP Driver</strong><a class="headerlink" href="#host-attach-memory-subsystem-ip-driver" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/memory/dfl-emif.c?h=master">Upstreamed</a></p>
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‎rel-24.2/linux-dfl/dfl_fme/dfl_fme/index.html‎

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<h1 id="host-attach-dfl-fpga-management-engine-ip-driver"><strong>Host Attach DFL FPGA Management Engine IP Driver</strong><a class="headerlink" href="#host-attach-dfl-fpga-management-engine-ip-driver" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">October 15, 2024</span>
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<h1 id="dfl-pci-express-subsystem-ip-driver"><strong>DFL PCI Express Subsystem IP Driver</strong><a class="headerlink" href="#dfl-pci-express-subsystem-ip-driver" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/fpga/dfl-pci.c?h=master">Upstreamed</a></p>
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<h1 id="max-10-board-management-controller-driver"><strong>Max® 10 Board Management Controller Driver</strong><a class="headerlink" href="#max-10-board-management-controller-driver" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 15, 2024</strong> </p>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mfd?h=master">Upstreamed</a></p>
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<span class="git-revision-date-localized-plugin git-revision-date-localized-plugin-date">October 23, 2024</span>
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<h1 id="ethernet-ieee-1588-time-of-day-clock-fpga-ip-driver-for-host-attach"><strong>Ethernet IEEE 1588 Time of Day Clock FPGA IP Driver for Host Attach</strong><a class="headerlink" href="#ethernet-ieee-1588-time-of-day-clock-fpga-ip-driver-for-host-attach" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 15, 2024</strong> </p>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ptp/ptp_dfl_tod.c?h=master">Upstreamed</a></p>
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<h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
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<p>This page provides an overview of the Time-of-day driver for the Time of Day Clock FPGA IP that is used in the 1588PTP Design examples. The Time of Day Clock FPGA IP is exposed as PTP Hardware Clock (PHC) device to the Linux PTP stack to synchronize the system clock to its ToD information using phc2sys utility of the Linux PTP stack.</p>
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<h1 id="altera-16550-compatible-uart-core-driver-for-host-attach"><strong>Altera 16550 Compatible UART Core Driver for Host Attach</strong><a class="headerlink" href="#altera-16550-compatible-uart-core-driver-for-host-attach" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>October 15, 2024</strong> </p>
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<p>Last updated: <strong>October 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/serial/8250/8250_dfl.c?h=master">Upstreamed</a></p>
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<h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
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<p>This driver for the 16550 Compatible UART Core to establish TTY communications to FPGA through PCIe.</p>
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