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1 | 1 | %-------------------------------------------------------------------------- |
2 | 2 | % HDL Workflow Script |
3 | | -% Generated with MATLAB 9.3 (R2017b) at 17:40:49 on 17/04/2018 |
| 3 | +% Generated with MATLAB 9.3 (R2017b) at 14:05:38 on 07/05/2018 |
4 | 4 | % This script was generated using the following parameter values: |
5 | | -% Filename : '/tmp/modem-phy/FixedPoint/demos/ADI_AXIMM/hdlworkflow.m' |
| 5 | +% Filename : '/tmp/MathWorks_tools/targeting_models/modem-qpsk/FixedPoint/demos/ADI_DMA_TT/hdlworkflow.m' |
6 | 6 | % Overwrite : true |
7 | 7 | % Comments : true |
8 | 8 | % Headers : true |
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28 | 28 | hdlset_param('combinedTxRx_ADIDMA', 'SynthesisToolSpeedValue', '-2L'); |
29 | 29 | hdlset_param('combinedTxRx_ADIDMA', 'TargetDirectory', 'hdl_prj/hdlsrc'); |
30 | 30 | hdlset_param('combinedTxRx_ADIDMA', 'TargetLanguage', 'Verilog'); |
31 | | -hdlset_param('combinedTxRx_ADIDMA', 'TargetPlatform', 'AnalogDevices adrv9361z7035 box lvds (Rx & Tx)'); |
| 31 | +hdlset_param('combinedTxRx_ADIDMA', 'TargetPlatform', 'AnalogDevices adrv9361z7035 box lvds (modem)'); |
32 | 32 | hdlset_param('combinedTxRx_ADIDMA', 'Workflow', 'IP Core Generation'); |
33 | 33 |
|
34 | 34 | % Set SubSystem HDL parameters |
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277 | 277 | hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/syncRx', 'IOInterfaceMapping', '[0]'); |
278 | 278 |
|
279 | 279 | % Set Outport HDL parameters |
280 | | -hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/reRx', 'IOInterface', 'IP Debug 2 OUT [0:15]'); |
| 280 | +hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/reRx', 'IOInterface', 'IP Debug 1 OUT [0:15]'); |
281 | 281 | hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/reRx', 'IOInterfaceMapping', '[0:15]'); |
282 | 282 |
|
283 | 283 | % Set Outport HDL parameters |
284 | | -hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/imRx', 'IOInterface', 'IP Debug 3 OUT [0:15]'); |
| 284 | +hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/imRx', 'IOInterface', 'IP Debug 2 OUT [0:15]'); |
285 | 285 | hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/imRx', 'IOInterfaceMapping', '[0:15]'); |
286 | 286 |
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287 | 287 | % Set Outport HDL parameters |
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