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Commit 09a4d55

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Merge branch 'master' into 2017b
2 parents 13be0a2 + 750189f commit 09a4d55

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8 files changed

+5
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targeting_models/modem-qpsk/FixedPoint/demos/ADI_DMA_TT/hdlworkflow.m

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
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%--------------------------------------------------------------------------
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% HDL Workflow Script
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% Generated with MATLAB 9.3 (R2017b) at 17:40:49 on 17/04/2018
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% Generated with MATLAB 9.3 (R2017b) at 14:05:38 on 07/05/2018
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% This script was generated using the following parameter values:
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% Filename : '/tmp/modem-phy/FixedPoint/demos/ADI_AXIMM/hdlworkflow.m'
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% Filename : '/tmp/MathWorks_tools/targeting_models/modem-qpsk/FixedPoint/demos/ADI_DMA_TT/hdlworkflow.m'
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% Overwrite : true
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% Comments : true
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% Headers : true
@@ -28,7 +28,7 @@
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hdlset_param('combinedTxRx_ADIDMA', 'SynthesisToolSpeedValue', '-2L');
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hdlset_param('combinedTxRx_ADIDMA', 'TargetDirectory', 'hdl_prj/hdlsrc');
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hdlset_param('combinedTxRx_ADIDMA', 'TargetLanguage', 'Verilog');
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hdlset_param('combinedTxRx_ADIDMA', 'TargetPlatform', 'AnalogDevices adrv9361z7035 box lvds (Rx & Tx)');
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hdlset_param('combinedTxRx_ADIDMA', 'TargetPlatform', 'AnalogDevices adrv9361z7035 box lvds (modem)');
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hdlset_param('combinedTxRx_ADIDMA', 'Workflow', 'IP Core Generation');
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% Set SubSystem HDL parameters
@@ -277,11 +277,11 @@
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hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/syncRx', 'IOInterfaceMapping', '[0]');
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% Set Outport HDL parameters
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hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/reRx', 'IOInterface', 'IP Debug 2 OUT [0:15]');
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hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/reRx', 'IOInterface', 'IP Debug 1 OUT [0:15]');
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hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/reRx', 'IOInterfaceMapping', '[0:15]');
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% Set Outport HDL parameters
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hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/imRx', 'IOInterface', 'IP Debug 3 OUT [0:15]');
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hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/imRx', 'IOInterface', 'IP Debug 2 OUT [0:15]');
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hdlset_param('combinedTxRx_ADIDMA/Combined TX and RX/imRx', 'IOInterfaceMapping', '[0:15]');
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% Set Outport HDL parameters
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targeting_models/modem-qpsk/FixedPoint/demos/AXI_MM/aximm_runtime.m

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