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tfcollinstfcollins
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Add HDL targeting support for Pluto with fixes for AD9363 targeted devices. (#55)
Signed-off-by: Travis Collins <travis.collins@analog.com>
1 parent eceaf3c commit 0aacd07

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‎CI/projects/pluto/Makefile‎

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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := pluto
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M_DEPS += ../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += util_fir_dec
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LIB_DEPS += util_fir_int
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include ../scripts/project-xilinx.mk

‎CI/projects/pluto/config_prj.tcl‎

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global ref_design
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global fpga_board
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global dma
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# Add System Reset IP
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startgroup
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create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0
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endgroup
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connect_bd_net [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins sys_rstgen/peripheral_aresetn]
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connect_bd_net [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins axi_ad9361/l_clk]
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# Add 1 extra AXI master ports to the interconnect
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set_property -dict [list CONFIG.NUM_MI {5}] [get_bd_cells axi_cpu_interconnect]
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connect_bd_net [get_bd_pins axi_cpu_interconnect/M04_ACLK] [get_bd_pins axi_ad9361/l_clk]
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connect_bd_net [get_bd_pins axi_cpu_interconnect/M04_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
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# Remove filters
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delete_bd_objs [get_bd_cells fir_decimator]
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delete_bd_objs [get_bd_cells fir_interpolator]
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# Configure DMA
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if {$dma eq "Packetized"} {
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma]
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connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins axi_ad9361/l_clk]
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}
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# Insert pack cores
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startgroup
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create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_0
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endgroup
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16} CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_cpack_0]
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# Clocks and resets
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connect_bd_net [get_bd_pins util_cpack_0/adc_clk] [get_bd_pins axi_ad9361/l_clk]
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connect_bd_net [get_bd_pins util_cpack_0/adc_rst] [get_bd_pins proc_sys_reset_0/peripheral_reset]
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# Connect enables
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connect_bd_net [get_bd_pins axi_ad9361/adc_enable_i0] [get_bd_pins util_cpack_0/adc_enable_0]
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connect_bd_net [get_bd_pins axi_ad9361/adc_enable_q0] [get_bd_pins util_cpack_0/adc_enable_1]
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# Connect valids together
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connect_bd_net [get_bd_pins util_cpack_0/adc_valid_1] [get_bd_pins util_cpack_0/adc_valid_0]
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############ DMA MODE
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if {$dma eq "Packetized"} {
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# Packetized DMA
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connect_bd_net [get_bd_pins util_cpack_0/adc_data] [get_bd_pins axi_ad9361_adc_dma/s_axis_data]
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connect_bd_net [get_bd_pins util_cpack_0/adc_valid] [get_bd_pins axi_ad9361_adc_dma/s_axis_valid]
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} else {
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# FIFO DMA
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connect_bd_net [get_bd_pins util_cpack_0/adc_data] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din]
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connect_bd_net [get_bd_pins util_cpack_0/adc_valid] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en]
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}
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###### UnPack
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startgroup
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create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_0
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endgroup
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16} CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_upack_0]
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# Connect data
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connect_bd_net [get_bd_pins util_upack_0/dac_data_0] [get_bd_pins axi_ad9361/dac_data_i0]
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connect_bd_net [get_bd_pins util_upack_0/dac_data_1] [get_bd_pins axi_ad9361/dac_data_q0]
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connect_bd_net [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] [get_bd_pins util_upack_0/dac_data]
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# Connect Clock
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connect_bd_net [get_bd_pins util_upack_0/dac_clk] [get_bd_pins axi_ad9361/l_clk]
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# Valid from pack to DMA
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connect_bd_net [get_bd_pins util_upack_0/dac_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en]
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#
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#connect_bd_net [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] [get_bd_pins util_upack_0/dac_valid_0]
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#connect_bd_net [get_bd_pins util_upack_0/dac_valid_1] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
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# Input valids
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connect_bd_net [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] [get_bd_pins util_upack_0/dac_enable_0]
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connect_bd_net [get_bd_pins util_upack_0/dac_valid_0] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
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connect_bd_net [get_bd_pins util_upack_0/dac_valid_1] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
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connect_bd_net [get_bd_pins util_upack_0/dac_enable_1] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
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‎CI/projects/pluto/config_rxtx.tcl‎

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set ad_hdl_dir [pwd]
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set proj_dir $ad_hdl_dir/projects/pluto
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source $proj_dir/config_prj.tcl
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source $ad_hdl_dir/projects/pluto/config_rxtx_board.tcl
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regenerate_bd_layout

‎CI/projects/pluto/config_rxtx_board.tcl‎

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global ref_design
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global fpga_board
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# Configure DMA
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#set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma]
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#connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins axi_ad9361/l_clk]
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#connect_bd_net [get_bd_pins fir_decimator/m_axis_data_tdata] [get_bd_pins axi_ad9361_adc_dma/s_axis_data]
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#connect_bd_net [get_bd_pins fir_decimator/m_axis_data_tvalid] [get_bd_pins axi_ad9361_adc_dma/s_axis_valid]
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if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} {
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# Disconnect the ADC PACK pins
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delete_bd_objs [get_bd_nets axi_ad9361_adc_data_i0]
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delete_bd_objs [get_bd_nets axi_ad9361_adc_data_q0]
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# Disconnect valid
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delete_bd_objs [get_bd_nets axi_ad9361_adc_valid_i0]
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}
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if {$ref_design eq "Tx" || $ref_design eq "Rx & Tx"} {
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# Disconnect the DAC UNPACK pins
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delete_bd_objs [get_bd_nets fir_interpolator_channel_0]
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delete_bd_objs [get_bd_nets fir_interpolator_channel_1]
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# Disconnect valid
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#delete_bd_objs [get_bd_nets axi_ad9361_dac_dma_fifo_rd_valid]
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}

‎CI/projects/pluto/pluto_fpga.tcl‎

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# Build the project
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update_compile_order -fileset sources_1
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reset_run impl_1
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reset_run synth_1
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launch_runs synth_1
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wait_on_run synth_1
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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# Define local variables
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set cdir [pwd]
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set sdk_loc vivado_prj.sdk
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# Export the hdf
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file delete -force $sdk_loc
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file mkdir $sdk_loc
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file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hdf
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# Close the Vivado project
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close_project
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puts "------------------------------------"
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puts "Embedded system build completed."
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puts "You may close this shell."
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puts "------------------------------------"
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exit

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