Merge pull request #39 from analogdevicesinc/fix-bootbin-gen

tfcollins · web-flow · commit 37182b3a0e63 · 2019-02-08T16:07:33.000-08:00
Fix boot.bin generation
diff --git a/+adi/Version.m b/+adi/Version.m
@@ -0,0 +1,20 @@
+classdef Version
+    %Version
+    %   BSP Version information
+    properties(Constant)
+        HDL = 'hdl_2018_r1';
+        Vivado = '2017.4.1';
+        MATLAB = 'R2018b';
+        Release = '18.2';
+    end
+    properties(Dependent)
+        VivadoShort
+    end
+    
+    methods
+        function value = get.VivadoShort(obj)
+            value = obj.Vivado(1:6); 
+        end
+    end
+end
+
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -78,6 +78,24 @@ test_installer:2018_R1_Installer:
         reports:
             junit: test/BSPTestResults.xml
 
+# Test weekly fully sythesized design
+test:Synthesize:
+    when: manual
+    tags:
+     - matlab
+     - vivado
+    stage: test
+    dependencies:
+     - build:2018_R1
+    script:
+     - ./CI/scripts/dockermake test_synth
+    artifacts:
+        when: always
+        name: "$CI_COMMIT_REF_NAME"
+        paths:
+            - test/
+            - Report.pdf
+
 # Test streaming interfaces with hardware
 test_hardware:Streaming_Hardware:
     tags:
diff --git a/CI/projects/adrv9371x/common/config_rxtx.tcl b/CI/projects/adrv9371x/common/config_rxtx.tcl
@@ -20,8 +20,22 @@ connect_bd_net [get_bd_pins util_ad9371_rx_cpack/adc_valid_0] [get_bd_pins util_
 
 }
 
+# Tie clocks to only use RX clocks
+if {$ref_design eq "Rx & Tx"} {
+  delete_bd_objs [get_bd_nets axi_ad9371_tx_clkgen_clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_0] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_2] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_3] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins axi_ad9371_tx_jesd/device_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_tx_upack/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins axi_ad9371_tx_jesd_rstgen/slowest_sync_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins axi_ad9371_dacfifo/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins axi_ad9371_core/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+}
+
 # Connect clock
-if {$fpga_board eq "ZC706"} { 
+if {$fpga_board eq "ZC706"} {
 if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} {
 connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M18_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
 }
@@ -30,7 +44,7 @@ connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_inte
 }
 }
 
-if {$fpga_board eq "ZCU102"} { 
+if {$fpga_board eq "ZCU102"} {
 if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} {
 connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
 }
diff --git a/CI/projects/adrv9371x/zc706/boot/u-boot.elf b/CI/projects/adrv9371x/zc706/boot/u-boot.elf
diff --git a/CI/projects/adrv9371x/zc706/system_project_rxtx.tcl b/CI/projects/adrv9371x/zc706/system_project_rxtx.tcl
@@ -10,6 +10,7 @@ adi_project_files adrv9371x_zc706 [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
+  "$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 adi_project_run adrv9371x_zc706
diff --git a/CI/projects/common/boot/bl31.elf b/CI/projects/common/boot/bl31.elf
diff --git a/CI/projects/common/boot/zynq.bif b/CI/projects/common/boot/zynq.bif
@@ -0,0 +1,6 @@
+the_ROM_image:
+{
+[bootloader]./fsbl.elf
+./system_top.bit
+./u-boot.elf
+}
diff --git a/CI/projects/common/boot/zynqmp.bif b/CI/projects/common/boot/zynqmp.bif
@@ -0,0 +1,9 @@
+the_ROM_image:
+{
+[fsbl_config] a53_x64
+[bootloader] ./fsbl.elf
+[pmufw_image] ./pmufw.elf
+[destination_device=pl] ./system_top.bit
+[destination_cpu=a53-0,exception_level=el-3,trustzone] ./bl31.elf
+[destination_cpu=a53-0,exception_level=el-2] ./u-boot-zcu.elf
+}
diff --git a/CI/projects/scripts/fixmake.sh b/CI/projects/scripts/fixmake.sh
@@ -0,0 +1,3 @@
+grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile
+cd pmufw
+make
diff --git a/CI/projects/scripts/fsbl_build.tcl b/CI/projects/scripts/fsbl_build.tcl
@@ -1,3 +1,13 @@
+
+if { $argc != 3 } {
+    set fpga_board "ZC706"
+} else {
+    set fpga_board [lindex $argv 1]
+}
+puts "==========="
+puts $fpga_board
+puts "==========="
+
 set cdir [pwd]
 set sdk_loc $cdir/vivado_prj.sdk
 
@@ -6,9 +16,26 @@ hsi open_hw_design $sdk_loc/system_top.hdf
 set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0] 
 sdk set_workspace $sdk_loc
 sdk create_hw_project -name hw_0 -hwspec $sdk_loc/system_top.hdf
-sdk create_app_project -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}
+
+# Create project
+if {$fpga_board eq "ZCU102"} {
+    sdk create_app_project -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL}
+} else {
+    sdk create_app_project -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}
+}
+
 sdk configapp -app fsbl build-config release
 sdk build_project -type all
 
+# Collect necessary files
+file copy -force $cdir/projects/common/boot/zynq.bif $cdir/boot/zynq.bif
+file copy -force $sdk_loc/fsbl/Release/fsbl.elf $cdir/boot/fsbl.elf
+file copy -force $sdk_loc/hw_0/system_top.bit $cdir/boot/system_top.bit
+cd $cdir/boot
+
 # Create the BOOT.bin
+if {$fpga_board eq "ZCU102"} {
+exec bootgen -image $cdir/boot/zynqmp.bif -w -o i $cdir/boot/BOOT.BIN
+} else {
 exec bootgen -image $cdir/boot/zynq.bif -w -o i $cdir/boot/BOOT.BIN
+}
diff --git a/CI/projects/scripts/fsbl_build_zynq.tcl b/CI/projects/scripts/fsbl_build_zynq.tcl
@@ -0,0 +1,29 @@
+
+
+### Calling script must have system_top.hdf u-boot.elf
+
+
+set cdir [pwd]
+set sdk_loc $cdir/vivado_prj.sdk
+
+### Create fsbl
+hsi open_hw_design $sdk_loc/system_top.hdf
+set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]
+sdk setws $sdk_loc
+sdk createhw -name hw_0 -hwspec $sdk_loc/system_top.hdf
+sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}
+configapp -app fsbl build-config release
+sdk projects -build -type all
+
+### Copy common zynq.bif file
+file copy -force $cdir/projects/common/boot/zynq.bif $cdir/boot/zynq.bif
+
+### Copy fsbl and system_top.bit into the output folder
+file copy -force $sdk_loc/fsbl/Release/fsbl.elf $cdir/boot/fsbl.elf
+file copy -force $sdk_loc/hw_0/system_top.bit $cdir/boot/system_top.bit
+
+### Build BOOT.BIN
+cd $cdir/boot
+exec bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w
+exit
+
diff --git a/CI/projects/scripts/fsbl_build_zynqmp.tcl b/CI/projects/scripts/fsbl_build_zynqmp.tcl
@@ -0,0 +1,34 @@
+
+
+### Calling script must have system_top.hdf u-boot.elf
+
+
+set cdir [pwd]
+set sdk_loc $cdir/vivado_prj.sdk
+
+### Create fsbl
+hsi open_hw_design $sdk_loc/system_top.hdf
+set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]
+sdk setws $sdk_loc
+sdk createhw -name hw_0 -hwspec $sdk_loc/system_top.hdf
+sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL}
+configapp -app fsbl build-config release
+sdk projects -build -type all
+
+### Create create_pmufw_project.tcl
+#set hwdsgn [open_hw_design $sdk_loc/system_top.hdf]
+#generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw
+
+### Copy common zynqmp.bif and bl31.elf file
+file copy -force $cdir/projects/common/boot/zynqmp.bif $cdir/boot/zynqmp.bif
+file copy -force $cdir/projects/common/boot/bl31.elf $cdir/boot/bl31.elf
+
+### Copy fsbl and system_top.bit into the output folder
+file copy -force $sdk_loc/fsbl/Release/fsbl.elf $cdir/boot/fsbl.elf
+file copy -force $sdk_loc/hw_0/system_top.bit $cdir/boot/system_top.bit
+file copy -force $cdir/pmufw/executable.elf $cdir/boot/pmufw.elf
+
+### Build BOOT.BIN
+cd $cdir/boot
+exec bootgen -arch zynqmp -image zynqmp.bif -o BOOT.BIN -w
+exit
diff --git a/CI/projects/scripts/pmufw_zynqmp.tcl b/CI/projects/scripts/pmufw_zynqmp.tcl
@@ -0,0 +1,8 @@
+
+set cdir [pwd]
+set sdk_loc $cdir/vivado_prj.sdk
+
+### Create create_pmufw_project.tcl
+set hwdsgn [open_hw_design $sdk_loc/system_top.hdf]
+generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw
+quit
diff --git a/CI/scripts/Docker b/CI/scripts/Docker
@@ -1,6 +1,8 @@
-FROM ubuntu:18.04
+FROM ubuntu:16.04
 
 MAINTAINER Travis Collins <travis.collins@analog.com>
 RUN apt update
 RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libpng-dev libfreetype6-dev libblas-dev liblapack-dev gfortran build-essential xorg
-RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git
+RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git xvfb
+RUN DEBIAN_FRONTEND=noninteractive dpkg --add-architecture i386
+RUN DEBIAN_FRONTEND=noninteractive apt-get install -y lib32stdc++6
diff --git a/CI/scripts/Makefile b/CI/scripts/Makefile
@@ -3,6 +3,8 @@
 # Example
 #	make build MLRELEASE=R2018b HDLBRANCH=hdl_2018_r1
 
+SHELL := /bin/bash
+
 MLFLAGS := -nodisplay -nodesktop -nosplash
 
 ifeq ($(MLRELEASE),)
@@ -92,6 +94,9 @@ test_modem:
 	cd ../.. ; \
 	${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "addpath(genpath('hdl_wa_bsp'));cd('targeting_models');addpath(genpath('modem-qpsk'))"
 
+test_synth:
+	bash synth_designs.sh
+
 gen_tlbx:
 	${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "genTlbx;exit();"
 
diff --git a/CI/scripts/adi_build.tcl b/CI/scripts/adi_build.tcl
@@ -1,3 +1,14 @@
+global fpga_board
+
+if {[info exists fpga_board]} {
+    puts "==========="
+    puts $fpga_board
+    puts "==========="
+} else {
+    # Set to something not ZCU102
+    set fpga_board "ZYNQ"
+}
+
 # Build the project
 update_compile_order -fileset sources_1
 reset_run impl_1
@@ -20,7 +31,45 @@ file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hd
 close_project
 
 # Create the BOOT.bin
-exec xsdk -batch -source $cdir/projects/scripts/fsbl_build.tcl -wait
+#exec xsdk -batch -source $cdir/projects/scripts/fsbl_build.tcl -tclargs $fpga_board -wait
+
+if {$fpga_board eq "ZCU102"} {
+    exec hsi -source $cdir/projects/scripts/pmufw_zynqmp.tcl
+    file copy -force $cdir/projects/scripts/fixmake.sh $cdir/fixmake.sh
+    exec chmod +x fixmake.sh
+
+    #exec ./fixmake.sh
+    #cd pmufw
+    #exec make
+    #cd ..
+    if [catch "exec -ignorestderr ./fixmake.sh" ret opt] {
+        set makeRet [lindex [dict get $opt -errorcode] end]
+        puts "make returned with $makeRet"
+    }
+    if {[file exist pmufw/executable.elf] eq 0} {
+        puts "ERROR: pmufw not built"
+        return -code error 10
+    } else {
+        puts "pmufw built correctly!"
+    }
+    
+    exec xsdk -batch -source $cdir/projects/scripts/fsbl_build_zynqmp.tcl
+    if {[file exist boot/BOOT.BIN] eq 0} {
+        puts "ERROR: BOOT.BIN not built"
+        return -code error 11
+    } else {
+        puts "BOOT.BIN built correctly!"
+    }
+
+} else {
+    exec xsdk -batch -source $cdir/projects/scripts/fsbl_build_zynq.tcl
+    if {[file exist boot/BOOT.BIN] eq 0} {
+        puts "ERROR: BOOT.BIN not built"
+        return -code error 11
+    } else {
+        puts "BOOT.BIN built correctly!"
+    }
+}
 
 puts "------------------------------------"
 puts "Embedded system build completed."
diff --git a/CI/scripts/dockermake b/CI/scripts/dockermake
@@ -1,3 +1,3 @@
 #!/bin/bash
 docker build . -t matlabci -f CI/scripts/Docker
-docker run --rm -e "MLRELEASE=$MLRELEASE"  -e "HDLBRANCH=$HDLBRANCH" -v "$(pwd):/work"  -v /mlhsp:/mlhspro:ro -v /usr/local/MATLAB:/usr/local/MATLAB  -v /root/.matlab:/root/.matlabro:ro -v /opt/Xilinx:/opt/Xilinx --mac-address="$ADDR" matlabci /bin/bash -c "cd /work && chmod +x CI/scripts/setupDocker.sh && ./CI/scripts/setupDocker.sh && make -C CI/scripts '$@'"
+docker run --rm -e "LM_LICENSE_FILE=$LM_LICENSE_FILE" -e "XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE" -e "MLRELEASE=$MLRELEASE"  -e "HDLBRANCH=$HDLBRANCH" -v "$(pwd):/work"  -v /mlhsp:/mlhspro:ro -v /usr/local/MATLAB:/usr/local/MATLAB  -v /root/.matlab:/root/.matlabro:ro -v /root/.Xilinx:/root/.Xilinxro:ro -v /opt/Xilinx:/opt/Xilinx --mac-address="$ADDR" matlabci /bin/bash -c "cd /work && chmod +x CI/scripts/setupDocker.sh && ./CI/scripts/setupDocker.sh && make -C CI/scripts '$@'"
diff --git a/CI/scripts/setupDocker.sh b/CI/scripts/setupDocker.sh
@@ -4,4 +4,6 @@ echo "Copying HSP files"
 cp -r /mlhspro /mlhsp
 echo "Copying .matlab"
 cp -r /root/.matlabro /root/.matlab
-
+echo "Copying .Xilinx"
+cp -r /root/.Xilinxro /root/.Xilinx
+source /opt/Xilinx/Vivado/2017.4/settings64.sh
diff --git a/CI/scripts/synth_designs.sh b/CI/scripts/synth_designs.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+MLFLAGS="-nodisplay -nodesktop -nosplash"
+
+if [ -z "$MLRELEASE" ]
+then
+	MLRELEASE=R2018b
+fi
+
+MLPATH=/usr/local/MATLAB
+
+cd ../.. 
+cp hdl_wa_bsp/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m
+sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m
+source /opt/Xilinx/Vivado/2017.4/settings64.sh
+Xvfb :77 &
+export DISPLAY=:77
+export SWT_GTK3=0
+source /opt/Xilinx/Vivado/2017.4/settings64.sh
+$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "cd('test');runSynthTests;"
+kill -9 `pidof Xvfb`
diff --git a/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+common/plugin_rd.m b/hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9009/+common/plugin_rd.m
@@ -53,7 +53,12 @@
 hRD.CustomFiles = {...
     fullfile('projects')...,
 	fullfile('library')...,
-    };	
+    };
+
+hRD.addParameter( ...
+    'ParameterID',   'fpga_board', ...
+    'DisplayName',   'FPGA Boad', ...
+    'DefaultValue',  upper(board));
 	
 %% Add interfaces
 % add clock interface
diff --git a/targeting_models/modem-qpsk/test/hdl/checkTimingReport.m b/targeting_models/modem-qpsk/test/hdl/checkTimingReport.m
@@ -11,7 +11,14 @@
 full = [path,'/',filename];
 
 if ~isfile(full)
-   error(['No timing report found under: ',full]); 
+    full1 = full;
+    % Try ZYNQMP naming
+    path = [hdl_prj,'/vivado_ip_prj/vivado_prj.runs/impl_1'];
+    filename = 'system_top_timing_summary_routed.rpt';
+    full = [path,'/',filename];
+    if ~isfile(full)
+        error(['No timing report found under: ',full,' or ',full1]);
+    end
 end
 
 fid = fopen(full);
diff --git a/test/BSPTestsBase.m b/test/BSPTestsBase.m
diff --git a/test/build_design.m b/test/build_design.m
diff --git a/test/runSynthTests.m b/test/runSynthTests.m

Original file line number	Diff line number	Diff line change
`@@ -20,8 +20,22 @@ connect_bd_net [get_bd_pins util_ad9371_rx_cpack/adc_valid_0] [get_bd_pins util_`
`20`	`20`
`21`	`21`	`}`
`22`	`22`
	`23`	`+# Tie clocks to only use RX clocks`
	`24`	`+if {$ref_design eq "Rx & Tx"} {`
	`25`	`+ delete_bd_objs [get_bd_nets axi_ad9371_tx_clkgen_clk_0]`
	`26`	`+ connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_0] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`27`	`+ connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`28`	`+ connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_2] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`29`	`+ connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_3] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`30`	`+ connect_bd_net [get_bd_pins axi_ad9371_tx_jesd/device_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`31`	`+ connect_bd_net [get_bd_pins util_ad9371_tx_upack/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`32`	`+ connect_bd_net [get_bd_pins axi_ad9371_tx_jesd_rstgen/slowest_sync_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`33`	`+ connect_bd_net [get_bd_pins axi_ad9371_dacfifo/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`34`	`+ connect_bd_net [get_bd_pins axi_ad9371_core/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
	`35`	`+}`
	`36`	`+`
`23`	`37`	`# Connect clock`
`24`		`-if {$fpga_board eq "ZC706"} {`
	`38`	`+if {$fpga_board eq "ZC706"} {`
`25`	`39`	`if {$ref_design eq "Rx" \|\| $ref_design eq "Rx & Tx"} {`
`26`	`40`	`connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M18_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
`27`	`41`	`}`
`@@ -30,7 +44,7 @@ connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_inte`
`30`	`44`	`}`
`31`	`45`	`}`
`32`	`46`
`33`		`-if {$fpga_board eq "ZCU102"} {`
	`47`	`+if {$fpga_board eq "ZCU102"} {`
`34`	`48`	`if {$ref_design eq "Rx" \|\| $ref_design eq "Rx & Tx"} {`
`35`	`49`	`connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]`
`36`	`50`	`}`
Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,3 @@`
	`1`	`+grep "CC_FLAGS :=" pmufw/Makefile \| grep -e "-Os" \|\| sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile`
	`2`	`+cd pmufw`
	`3`	`+make`