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This repository was archived by the owner on Feb 2, 2021. It is now read-only.

Commit 7a49693

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tfcollinstfcollins
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Migrate to 2017.4
Signed-off-by: Travis Collins <travis.collins@analog.com>
1 parent 50692a5 commit 7a49693

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14 files changed

+19
-19
lines changed

14 files changed

+19
-19
lines changed

‎CI/projects/adrv9361z7035/ccbox_lvds_modem/system_bd.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2016.4
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set scripts_vivado_version 2017.4
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {

‎CI/projects/scripts/adi_project.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ variable p_prcfg_list
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variable p_prcfg_status
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if {![info exists REQUIRED_VIVADO_VERSION]} {
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set REQUIRED_VIVADO_VERSION "2016.4"
10+
set REQUIRED_VIVADO_VERSION "2017.4"
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}
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if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {

‎CI/scripts/adi_project.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ variable p_prcfg_list
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variable p_prcfg_status
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if {![info exists REQUIRED_VIVADO_VERSION]} {
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set REQUIRED_VIVADO_VERSION "2016.4"
10+
set REQUIRED_VIVADO_VERSION "2017.4"
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}
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if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {

‎hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9361z7035/+common/plugin_rd.m‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,13 @@
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% Create the reference design for the SOM-only
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% This is the base reference design that other RDs can build upon
11-
hRD.ReferenceDesignName = sprintf('adrv9361z7035 %s Base System (Vivado 2016.4)', board);
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hRD.ReferenceDesignName = sprintf('adrv9361z7035 %s Base System (Vivado 2017.4)', board);
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% Determine the board name based on the design
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hRD.BoardName = sprintf('AnalogDevices adrv9361z7035 %s (%s)', board, design);
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% Tool information
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hRD.SupportedToolVersion = {'2016.4'};
17+
hRD.SupportedToolVersion = {'2017.4'};
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% Get the root directory
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rootDir = fileparts(strtok(mfilename('fullpath'), '+'));

‎hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+adrv9364z7020/+common/plugin_rd.m‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,13 @@
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% Create the reference design for the SOM-only
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% This is the base reference design that other RDs can build upon
11-
hRD.ReferenceDesignName = sprintf('adrv9364z7020 %s Base System (Vivado 2016.4)', board);
11+
hRD.ReferenceDesignName = sprintf('adrv9364z7020 %s Base System (Vivado 2017.4)', board);
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% Determine the board name based on the design
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hRD.BoardName = sprintf('AnalogDevices adrv9364z7020 %s (%s)', board, design);
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% Tool information
17-
hRD.SupportedToolVersion = {'2016.4'};
17+
hRD.SupportedToolVersion = {'2017.4'};
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% Get the root directory
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rootDir = fileparts(strtok(mfilename('fullpath'), '+'));

‎hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms2/+common/plugin_rd.m‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,13 @@
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% Create the reference design for the SOM-only
1010
% This is the base reference design that other RDs can build upon
11-
hRD.ReferenceDesignName = sprintf('FMCOMMS2/3 %s Base System (Vivado 2016.4)', upper(board));
11+
hRD.ReferenceDesignName = sprintf('FMCOMMS2/3 %s Base System (Vivado 2017.4)', upper(board));
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% Determine the board name based on the design
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hRD.BoardName = sprintf('AnalogDevices FMCOMMS2/3 %s (%s)', upper(board), design);
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% Tool information
17-
hRD.SupportedToolVersion = {'2016.4'};
17+
hRD.SupportedToolVersion = {'2017.4'};
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% Get the root directory
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rootDir = fileparts(strtok(mfilename('fullpath'), '+'));

‎hdl_wa_bsp/vendor/AnalogDevices/+AnalogDevices/+fmcomms5/+common/plugin_rd.m‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,13 @@
88

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% Create the reference design for the SOM-only
1010
% This is the base reference design that other RDs can build upon
11-
hRD.ReferenceDesignName = sprintf('FMCOMMS5 %s Base System (Vivado 2016.4)', upper(board));
11+
hRD.ReferenceDesignName = sprintf('FMCOMMS5 %s Base System (Vivado 2017.4)', upper(board));
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% Determine the board name based on the design
1414
hRD.BoardName = sprintf('AnalogDevices FMCOMMS5 %s (%s)', upper(board), design);
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% Tool information
17-
hRD.SupportedToolVersion = {'2016.4'};
17+
hRD.SupportedToolVersion = {'2017.4'};
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% Get the root directory
2020
rootDir = fileparts(strtok(mfilename('fullpath'), '+'));

‎targeting_models/modem-qpsk/FixedPoint/demos/ADI_DMA_TT/hdlworkflow.m‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
%% Model HDL Parameters
2121
%% Set Model 'combinedTxRx_ADIDMA' HDL parameters
2222
hdlset_param('combinedTxRx_ADIDMA', 'HDLSubsystem', 'combinedTxRx_ADIDMA/Combined TX and RX');
23-
hdlset_param('combinedTxRx_ADIDMA', 'ReferenceDesign', 'adrv9361z7035 box lvds Base System (Vivado 2016.4)');
23+
hdlset_param('combinedTxRx_ADIDMA', 'ReferenceDesign', 'adrv9361z7035 box lvds Base System (Vivado 2017.4)');
2424
hdlset_param('combinedTxRx_ADIDMA', 'SynthesisTool', 'Xilinx Vivado');
2525
hdlset_param('combinedTxRx_ADIDMA', 'SynthesisToolChipFamily', 'Zynq');
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hdlset_param('combinedTxRx_ADIDMA', 'SynthesisToolDeviceName', 'xc7z035i');
@@ -311,7 +311,7 @@
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312312
% Specify the top level project directory
313313
hWC.ProjectFolder = 'hdl_prj';
314-
hWC.ReferenceDesignToolVersion = '2016.4';
314+
hWC.ReferenceDesignToolVersion = '2017.4';
315315
hWC.IgnoreToolVersionMismatch = false;
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% Set Workflow tasks to run

‎targeting_models/modem-qpsk/FixedPoint/demos/External_Mode/hdlworkflow.m‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@
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% Specify the top level project directory
275275
hWC.ProjectFolder = 'hdl_prj';
276-
hWC.ReferenceDesignToolVersion = '2016.4';
276+
hWC.ReferenceDesignToolVersion = '2017.4';
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hWC.IgnoreToolVersionMismatch = false;
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% Set Workflow tasks to run

‎targeting_models/modem-qpsk/FixedPoint/demos/FPGA_Capture/hdlworkflow.m‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@
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% Specify the top level project directory
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hWC.ProjectFolder = 'hdl_prj';
252-
hWC.ReferenceDesignToolVersion = '2016.4';
252+
hWC.ReferenceDesignToolVersion = '2017.4';
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hWC.IgnoreToolVersionMismatch = false;
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% Set Workflow tasks to run

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