Fix RX&TX reference design clock bug for ADRV9371

Signed-off-by: Travis Collins <travis.collins@analog.com>

Author: tfcollins

CI/projects/adrv9371x/common/config_rxtx.tcl

@@ -20,8 +20,22 @@ connect_bd_net [get_bd_pins util_ad9371_rx_cpack/adc_valid_0] [get_bd_pins util_
 
 }
 
+# Tie clocks to only use RX clocks
+if {$ref_design eq "Rx & Tx"} {
+  delete_bd_objs [get_bd_nets axi_ad9371_tx_clkgen_clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_0] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_1] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_2] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_xcvr/tx_clk_3] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins axi_ad9371_tx_jesd/device_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins util_ad9371_tx_upack/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins axi_ad9371_tx_jesd_rstgen/slowest_sync_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins axi_ad9371_dacfifo/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+  connect_bd_net [get_bd_pins axi_ad9371_core/dac_clk] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
+}
+
 # Connect clock
-if {$fpga_board eq "ZC706"} { 
+if {$fpga_board eq "ZC706"} {
 if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} {
 connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M18_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
 }
@@ -30,7 +44,7 @@ connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_inte
 }
 }
 
-if {$fpga_board eq "ZCU102"} { 
+if {$fpga_board eq "ZCU102"} {
 if {$ref_design eq "Rx" || $ref_design eq "Rx & Tx"} {
 connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
 }