@@ -185,18 +185,63 @@ function AD9361_Filter_Wizard_OpeningFcn(hObject, eventdata, handles, varargin)
185185% sanity check the DAC divider value and alter it if necessary, note that if
186186% it's altered then the PLL and calibration dividers must be updated as well
187187if isfield(handles , ' input_tx' ) && isfield(handles , ' input_rx' )
188- ADC_rate = handles .input_rx .Rdata * handles .input_rx .FIR * ...
189- handles .input_rx .HB1 * handles .input_rx .HB2 * handles .input_rx .HB3 ;
190- DAC_rate = handles .input_tx .Rdata * handles .input_tx .FIR * ...
191- handles .input_tx .HB1 * handles .input_tx .HB2 * handles .input_tx .HB3 ;
192- DAC_div = ADC_rate / DAC_rate ;
193- if ~(handles .input_tx .DAC_div == DAC_div )
194- handles.input_tx.DAC_div = DAC_div ;
188+ if (handles .input_rx .PLL_rate ~= handles .input_tx .PLL_rate )
189+ rhb1 = handles .input_tx .HB1 ;
190+ rhb2 = handles .input_tx .HB2 ;
191+ if handles .input_tx .HB3 == 3
192+ rhb3 = 3 ;
193+ elseif handles .input_tx .HB3 == 2
194+ rhb3 = 2 ;
195+ else
196+ rhb3 = 1 ;
197+ end
198+ handles.input_rx.HB1 = rhb1 ;
199+ handles.input_rx.HB2 = rhb2 ;
200+ handles.input_rx.HB3 = rhb3 ;
201+
202+ ADC_rate = handles .input_rx .Rdata * handles .input_rx .FIR * ...
203+ handles .input_rx .HB1 * handles .input_rx .HB2 * handles .input_rx .HB3 ;
204+ DAC_rate = handles .input_tx .Rdata * handles .input_tx .FIR * ...
205+ handles .input_tx .HB1 * handles .input_tx .HB2 * handles .input_tx .HB3 ;
206+ DAC_div = ADC_rate / DAC_rate ;
207+ if ~(handles .input_tx .DAC_div == DAC_div )
208+ if (DAC_div == 1 || DAC_div == 2 )
209+ handles.input_tx.DAC_div = DAC_div ;
210+ handles.input_tx.PLL_mult = handles .input_rx .PLL_mult ;
211+ filter_type = get(handles .filter_type , ' Value' );
212+ set(handles .filter_type , ' Value' , 0 );
213+ handles.input_tx.caldiv = default_caldiv(handles );
214+ set(handles .filter_type , ' Value' , filter_type );
215+ end
216+ end
217+
218+ handles.input_rx.PLL_mult = fastest_FIR([64 32 16 8 4 2 1 ], handles .MAX_BBPLL_FREQ , handles .MIN_BBPLL_FREQ , ...
219+ handles .input_rx .Rdata * handles .input_rx .FIR * handles .input_rx .HB1 * handles .input_rx .HB2 * handles .input_rx .HB3 * handles .input_rx .DAC_div );
195220 handles.input_tx.PLL_mult = handles .input_rx .PLL_mult ;
196- filter_type = get(handles .filter_type , ' Value' );
197- set(handles .filter_type , ' Value' , 0 );
198- handles.input_tx.caldiv = default_caldiv(handles );
199- set(handles .filter_type , ' Value' , filter_type );
221+
222+ if handles .input_rx .PLL_mult > 64
223+ X = [' Date rate = ' , num2str(tohwTx .TXSAMP ), ' Hz. Tx BBPLL is too high for Rx to match.' ];
224+ disp(X );
225+ end
226+
227+ handles.input_rx.PLL_rate = handles .input_rx .Rdata * handles .input_rx .FIR * handles .input_rx .HB1 * ...
228+ handles .input_rx .HB2 * handles .input_rx .HB3 * handles .input_rx .PLL_mult ;
229+ else
230+ ADC_rate = handles .input_rx .Rdata * handles .input_rx .FIR * ...
231+ handles .input_rx .HB1 * handles .input_rx .HB2 * handles .input_rx .HB3 ;
232+ DAC_rate = handles .input_tx .Rdata * handles .input_tx .FIR * ...
233+ handles .input_tx .HB1 * handles .input_tx .HB2 * handles .input_tx .HB3 ;
234+ DAC_div = ADC_rate / DAC_rate ;
235+ if ~(handles .input_tx .DAC_div == DAC_div )
236+ if (DAC_div == 1 || DAC_div == 2 )
237+ handles.input_tx.DAC_div = DAC_div ;
238+ handles.input_tx.PLL_mult = handles .input_rx .PLL_mult ;
239+ filter_type = get(handles .filter_type , ' Value' );
240+ set(handles .filter_type , ' Value' , 0 );
241+ handles.input_tx.caldiv = default_caldiv(handles );
242+ set(handles .filter_type , ' Value' , filter_type );
243+ end
244+ end
200245 end
201246end
202247
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