From 5533991fc7a41696185fc0ee11362074936154f9 Mon Sep 17 00:00:00 2001 From: Ionut Podgoreanu Date: Mon, 4 Aug 2025 13:45:31 +0300 Subject: [PATCH] axi_dmac: Default to 64 bit addressing This commit increases the maximum address width of the DMA AXI interfaces to 64 to enable accessing the upper DDR memory regions of the 64 bit address spaces. Signed-off-by: Ionut Podgoreanu --- docs/regmap/adi_regmap_dmac.txt | 4 ++-- library/axi_dmac/address_generator.v | 4 ++-- library/axi_dmac/axi_dmac.v | 4 ++-- library/axi_dmac/axi_dmac_framelock.v | 4 ++-- library/axi_dmac/axi_dmac_regmap.v | 6 +++--- library/axi_dmac/axi_dmac_regmap_request.v | 4 ++-- library/axi_dmac/axi_dmac_transfer.v | 4 ++-- library/axi_dmac/dest_axi_mm.v | 4 ++-- library/axi_dmac/dmac_2d_transfer.v | 4 ++-- library/axi_dmac/dmac_sg.v | 4 ++-- library/axi_dmac/request_arb.v | 4 ++-- library/axi_dmac/src_axi_mm.v | 4 ++-- 12 files changed, 25 insertions(+), 25 deletions(-) diff --git a/docs/regmap/adi_regmap_dmac.txt b/docs/regmap/adi_regmap_dmac.txt index d8da24cf4e3..d07e2c08db6 100644 --- a/docs/regmap/adi_regmap_dmac.txt +++ b/docs/regmap/adi_regmap_dmac.txt @@ -9,7 +9,7 @@ ENDTITLE REG 0x000 VERSION -Version of the peripheral. Follows semantic versioning. Current version 4.05.64. +Version of the peripheral. Follows semantic versioning. Current version 4.05.65. ENDREG FIELD @@ -25,7 +25,7 @@ RO ENDFIELD FIELD -[7:0] 0x00000064 +[7:0] 0x00000065 VERSION_PATCH RO ENDFIELD diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v index 01d2801b38f..be17e1c5237 100644 --- a/library/axi_dmac/address_generator.v +++ b/library/axi_dmac/address_generator.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,7 +39,7 @@ module address_generator #( parameter ID_WIDTH = 3, parameter DMA_DATA_WIDTH = 64, - parameter DMA_ADDR_WIDTH = 32, + parameter DMA_ADDR_WIDTH = 64, parameter BEATS_PER_BURST_WIDTH = 4, parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8), parameter LENGTH_WIDTH = 8, diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index 4f053a739fc..57b0baeee48 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -60,7 +60,7 @@ module axi_dmac #( parameter DMA_AXI_PROTOCOL_SG = 0, parameter DMA_TYPE_DEST = 0, parameter DMA_TYPE_SRC = 2, - parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_AXI_ADDR_WIDTH = 64, parameter MAX_BYTES_PER_BURST = 128, parameter FIFO_SIZE = 8, // In bursts parameter AXI_ID_WIDTH_SRC = 1, diff --git a/library/axi_dmac/axi_dmac_framelock.v b/library/axi_dmac/axi_dmac_framelock.v index 45f24f74ea4..a52a952e3a1 100644 --- a/library/axi_dmac/axi_dmac_framelock.v +++ b/library/axi_dmac/axi_dmac_framelock.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -34,7 +34,7 @@ // *************************************************************************** module axi_dmac_framelock #( - parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_AXI_ADDR_WIDTH = 64, parameter BYTES_PER_BEAT_WIDTH_DEST = 3, parameter BYTES_PER_BEAT_WIDTH_SRC = 3, parameter FRAMELOCK_MODE = 0, // 0 - MM writer ; 1 - MM reader diff --git a/library/axi_dmac/axi_dmac_regmap.v b/library/axi_dmac/axi_dmac_regmap.v index 0e812d64b94..9c31c1ee4ee 100644 --- a/library/axi_dmac/axi_dmac_regmap.v +++ b/library/axi_dmac/axi_dmac_regmap.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -44,7 +44,7 @@ module axi_dmac_regmap #( parameter BYTES_PER_BURST_WIDTH = 7, parameter DMA_TYPE_DEST = 0, parameter DMA_TYPE_SRC = 2, - parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_AXI_ADDR_WIDTH = 64, parameter DMA_LENGTH_WIDTH = 24, parameter DMA_LENGTH_ALIGN = 3, parameter DMA_CYCLIC = 0, @@ -147,7 +147,7 @@ module axi_dmac_regmap #( input [31:0] dbg_ids1 ); - localparam PCORE_VERSION = 'h00040564; + localparam PCORE_VERSION = 'h00040565; localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32; localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1; diff --git a/library/axi_dmac/axi_dmac_regmap_request.v b/library/axi_dmac/axi_dmac_regmap_request.v index 3b7090f8c1a..41272f905b8 100644 --- a/library/axi_dmac/axi_dmac_regmap_request.v +++ b/library/axi_dmac/axi_dmac_regmap_request.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -41,7 +41,7 @@ module axi_dmac_regmap_request #( parameter BYTES_PER_BEAT_WIDTH_SRC = 1, parameter BYTES_PER_BEAT_WIDTH_SG = 1, parameter BYTES_PER_BURST_WIDTH = 7, - parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_AXI_ADDR_WIDTH = 64, parameter DMA_LENGTH_WIDTH = 24, parameter DMA_LENGTH_ALIGN = 3, parameter DMA_CYCLIC = 0, diff --git a/library/axi_dmac/axi_dmac_transfer.v b/library/axi_dmac/axi_dmac_transfer.v index ae3307824b8..1873092580f 100644 --- a/library/axi_dmac/axi_dmac_transfer.v +++ b/library/axi_dmac/axi_dmac_transfer.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -46,7 +46,7 @@ module axi_dmac_transfer #( parameter BYTES_PER_BEAT_WIDTH_SG = $clog2(DMA_DATA_WIDTH_SG/8), parameter DMA_TYPE_DEST = 0, parameter DMA_TYPE_SRC = 2, - parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_AXI_ADDR_WIDTH = 64, parameter DMA_2D_TRANSFER = 0, parameter DMA_2D_TLAST_MODE = 0, parameter DMA_SG_TRANSFER = 0, diff --git a/library/axi_dmac/dest_axi_mm.v b/library/axi_dmac/dest_axi_mm.v index 0d96ecc8def..88767bc24d3 100644 --- a/library/axi_dmac/dest_axi_mm.v +++ b/library/axi_dmac/dest_axi_mm.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,7 +39,7 @@ module dest_axi_mm #( parameter ID_WIDTH = 3, parameter DMA_DATA_WIDTH = 64, - parameter DMA_ADDR_WIDTH = 32, + parameter DMA_ADDR_WIDTH = 64, parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8), parameter BEATS_PER_BURST_WIDTH = 4, parameter MAX_BYTES_PER_BURST = 128, diff --git a/library/axi_dmac/dmac_2d_transfer.v b/library/axi_dmac/dmac_2d_transfer.v index 7ddaa65899a..58daa5c227b 100644 --- a/library/axi_dmac/dmac_2d_transfer.v +++ b/library/axi_dmac/dmac_2d_transfer.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,7 +38,7 @@ module dmac_2d_transfer #( parameter DMA_2D_TLAST_MODE = 0, // 0 - End of Frame; 1 - End of Line - parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_AXI_ADDR_WIDTH = 64, parameter DMA_LENGTH_WIDTH = 24, parameter BYTES_PER_BURST_WIDTH = 7, parameter BYTES_PER_BEAT_WIDTH_SRC = 3, diff --git a/library/axi_dmac/dmac_sg.v b/library/axi_dmac/dmac_sg.v index 48871fbc13d..e86f9c1c010 100644 --- a/library/axi_dmac/dmac_sg.v +++ b/library/axi_dmac/dmac_sg.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -36,7 +36,7 @@ `timescale 1ns/100ps module dmac_sg #( - parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_AXI_ADDR_WIDTH = 64, parameter DMA_DATA_WIDTH = 64, parameter DMA_LENGTH_WIDTH = 24, parameter AXI_LENGTH_WIDTH = 8, diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index ff33722538e..cc72c8c583a 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -44,7 +44,7 @@ module request_arb #( parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8), parameter DMA_TYPE_DEST = 0, parameter DMA_TYPE_SRC = 2, - parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_AXI_ADDR_WIDTH = 64, parameter ASYNC_CLK_REQ_SRC = 1, parameter ASYNC_CLK_SRC_DEST = 1, parameter ASYNC_CLK_DEST_REQ = 1, diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v index acad90ee2c9..4b16996cdd3 100644 --- a/library/axi_dmac/src_axi_mm.v +++ b/library/axi_dmac/src_axi_mm.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,7 +39,7 @@ module src_axi_mm #( parameter ID_WIDTH = 3, parameter DMA_DATA_WIDTH = 64, - parameter DMA_ADDR_WIDTH = 32, + parameter DMA_ADDR_WIDTH = 64, parameter BYTES_PER_BEAT_WIDTH = 3, parameter BEATS_PER_BURST_WIDTH = 4, parameter AXI_LENGTH_WIDTH = 8,