From ae5ad791d255b6fa9ae466ae874a83492780a8c9 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Thu, 23 Jan 2025 16:48:02 +0200 Subject: [PATCH 01/15] projects: ad9084_fmca_ebz: Initial commit Adds AD9084-EBZ (Apollo) base design for the following carriers: - vcu118 - vck190 - vpk180 - fm87 Signed-off-by: Bogdan Luncan --- projects/ad9084_ebz/Makefile | 7 + projects/ad9084_ebz/common/ad9084_ebz_bd.tcl | 1219 +++++++++++++++++ .../ad9084_ebz/common/ad9084_ebz_qsys.tcl | 646 +++++++++ projects/ad9084_ebz/common/ad9084_ebz_spi.v | 92 ++ projects/ad9084_ebz/common/hsci_phy_top.sv | 131 ++ .../ad9084_ebz/common/trigger_generator.v | 140 ++ .../ad9084_ebz/common/versal_hsci_phy.tcl | 43 + .../ad9084_ebz/common/versal_transceiver.tcl | 1179 ++++++++++++++++ projects/ad9084_ebz/fm87/Makefile | 32 + projects/ad9084_ebz/fm87/system_constr.sdc | 18 + projects/ad9084_ebz/fm87/system_project.tcl | 271 ++++ projects/ad9084_ebz/fm87/system_qsys.tcl | 66 + projects/ad9084_ebz/fm87/system_top.v | 427 ++++++ projects/ad9084_ebz/vck190/Makefile | 50 + projects/ad9084_ebz/vck190/system_bd.tcl | 86 ++ projects/ad9084_ebz/vck190/system_constr.xdc | 144 ++ projects/ad9084_ebz/vck190/system_project.tcl | 94 ++ projects/ad9084_ebz/vck190/system_top.v | 459 +++++++ projects/ad9084_ebz/vck190/timing_constr.tcl | 78 ++ projects/ad9084_ebz/vcu118/Makefile | 50 + projects/ad9084_ebz/vcu118/system_bd.tcl | 177 +++ projects/ad9084_ebz/vcu118/system_constr.xdc | 198 +++ projects/ad9084_ebz/vcu118/system_project.tcl | 99 ++ projects/ad9084_ebz/vcu118/system_top.v | 608 ++++++++ projects/ad9084_ebz/vcu118/timing_constr.xdc | 78 ++ projects/ad9084_ebz/vpk180/Makefile | 49 + projects/ad9084_ebz/vpk180/system_bd.tcl | 85 ++ projects/ad9084_ebz/vpk180/system_constr.xdc | 126 ++ projects/ad9084_ebz/vpk180/system_project.tcl | 94 ++ projects/ad9084_ebz/vpk180/system_top.v | 493 +++++++ projects/ad9084_ebz/vpk180/timing_constr.tcl | 79 ++ 31 files changed, 7318 insertions(+) create mode 100644 projects/ad9084_ebz/Makefile create mode 100755 projects/ad9084_ebz/common/ad9084_ebz_bd.tcl create mode 100644 projects/ad9084_ebz/common/ad9084_ebz_qsys.tcl create mode 100644 projects/ad9084_ebz/common/ad9084_ebz_spi.v create mode 100644 projects/ad9084_ebz/common/hsci_phy_top.sv create mode 100755 projects/ad9084_ebz/common/trigger_generator.v create mode 100755 projects/ad9084_ebz/common/versal_hsci_phy.tcl create mode 100644 projects/ad9084_ebz/common/versal_transceiver.tcl create mode 100755 projects/ad9084_ebz/fm87/Makefile create mode 100644 projects/ad9084_ebz/fm87/system_constr.sdc create mode 100644 projects/ad9084_ebz/fm87/system_project.tcl create mode 100644 projects/ad9084_ebz/fm87/system_qsys.tcl create mode 100644 projects/ad9084_ebz/fm87/system_top.v create mode 100755 projects/ad9084_ebz/vck190/Makefile create mode 100755 projects/ad9084_ebz/vck190/system_bd.tcl create mode 100644 projects/ad9084_ebz/vck190/system_constr.xdc create mode 100755 projects/ad9084_ebz/vck190/system_project.tcl create mode 100755 projects/ad9084_ebz/vck190/system_top.v create mode 100755 projects/ad9084_ebz/vck190/timing_constr.tcl create mode 100755 projects/ad9084_ebz/vcu118/Makefile create mode 100755 projects/ad9084_ebz/vcu118/system_bd.tcl create mode 100755 projects/ad9084_ebz/vcu118/system_constr.xdc create mode 100755 projects/ad9084_ebz/vcu118/system_project.tcl create mode 100755 projects/ad9084_ebz/vcu118/system_top.v create mode 100755 projects/ad9084_ebz/vcu118/timing_constr.xdc create mode 100755 projects/ad9084_ebz/vpk180/Makefile create mode 100755 projects/ad9084_ebz/vpk180/system_bd.tcl create mode 100644 projects/ad9084_ebz/vpk180/system_constr.xdc create mode 100755 projects/ad9084_ebz/vpk180/system_project.tcl create mode 100755 projects/ad9084_ebz/vpk180/system_top.v create mode 100755 projects/ad9084_ebz/vpk180/timing_constr.tcl diff --git a/projects/ad9084_ebz/Makefile b/projects/ad9084_ebz/Makefile new file mode 100644 index 00000000000..68a7ed005cb --- /dev/null +++ b/projects/ad9084_ebz/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl new file mode 100755 index 00000000000..4d49deaf02b --- /dev/null +++ b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl @@ -0,0 +1,1219 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +if {![info exists ADI_PHY_SEL]} { + set ADI_PHY_SEL 1 +} + +source ../../../projects/common/xilinx/data_offload_bd.tcl +source ../../../library/jesd204/scripts/jesd204.tcl + +# Common parameter for TX and RX +set JESD_MODE $ad_project_params(JESD_MODE) +set RX_LANE_RATE $ad_project_params(RX_LANE_RATE) +set TX_LANE_RATE $ad_project_params(TX_LANE_RATE) + +if {$ASYMMETRIC_A_B_MODE} { + set RX_B_LANE_RATE $ad_project_params(RX_B_LANE_RATE) + set TX_B_LANE_RATE $ad_project_params(TX_B_LANE_RATE) +} + +set HSCI_ENABLE [ expr { [info exists ad_project_params(HSCI_ENABLE)] \ + ? $ad_project_params(HSCI_ENABLE) : 1 } ] +set TDD_SUPPORT [ expr { [info exists ad_project_params(TDD_SUPPORT)] \ + ? $ad_project_params(TDD_SUPPORT) : 0 } ] +set SHARED_DEVCLK [ expr { [info exists ad_project_params(SHARED_DEVCLK)] \ + ? $ad_project_params(SHARED_DEVCLK) : 0 } ] + +if {$TDD_SUPPORT && !$SHARED_DEVCLK} { + error "ERROR: Cannot enable TDD support without shared deviceclocks!" +} + +set adc_do_mem_type [ expr { [info exists ad_project_params(ADC_DO_MEM_TYPE)] \ + ? $ad_project_params(ADC_DO_MEM_TYPE) : 0 } ] +set dac_do_mem_type [ expr { [info exists ad_project_params(DAC_DO_MEM_TYPE)] \ + ? $ad_project_params(DAC_DO_MEM_TYPE) : 0 } ] + +set do_axi_data_width [ expr { [info exists do_axi_data_width] \ + ? $do_axi_data_width : 256 } ] + +if {$JESD_MODE == "8B10B"} { + set DATAPATH_WIDTH 4 + set NP12_DATAPATH_WIDTH 6 + set ENCODER_SEL 1 +} else { + set DATAPATH_WIDTH 8 + set NP12_DATAPATH_WIDTH 12 + set ENCODER_SEL 2 +} + +# These are max values specific to the board +set MAX_RX_LANES_PER_LINK 12 +set MAX_TX_LANES_PER_LINK 12 +set MAX_RX_LINKS [expr $ASYMMETRIC_A_B_MODE ? 1 : 2] +set MAX_TX_LINKS [expr $ASYMMETRIC_A_B_MODE ? 1 : 2] +set MAX_RX_LANES [expr $MAX_RX_LANES_PER_LINK*$MAX_RX_LINKS] +set MAX_TX_LANES [expr $MAX_TX_LANES_PER_LINK*$MAX_TX_LINKS] +set MAX_APOLLO_LANES 24 + +# RX parameters +set RX_NUM_LINKS $ad_project_params(RX_NUM_LINKS) +if {$ASYMMETRIC_A_B_MODE} { + set RX_NUM_LINKS 1 +} + +# RX JESD parameter per link +set RX_JESD_M $ad_project_params(RX_JESD_M) +set RX_JESD_L $ad_project_params(RX_JESD_L) +set RX_JESD_S $ad_project_params(RX_JESD_S) +set RX_JESD_NP $ad_project_params(RX_JESD_NP) + +set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS] +set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS] +set RX_SAMPLES_PER_FRAME $RX_JESD_S +set RX_SAMPLE_WIDTH $RX_JESD_NP + +set RX_DMA_SAMPLE_WIDTH $RX_JESD_NP +if {$RX_DMA_SAMPLE_WIDTH == 12} { + set RX_DMA_SAMPLE_WIDTH 16 +} + +set RX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_JESD_L $RX_JESD_M $RX_JESD_S $RX_JESD_NP] + +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8* $RX_DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] + +# TX parameters +set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS) +if {$ASYMMETRIC_A_B_MODE} { + set TX_NUM_LINKS 1 +} + +# TX JESD parameter per link +set TX_JESD_M $ad_project_params(TX_JESD_M) +set TX_JESD_L $ad_project_params(TX_JESD_L) +set TX_JESD_S $ad_project_params(TX_JESD_S) +set TX_JESD_NP $ad_project_params(TX_JESD_NP) + +set TX_NUM_OF_LANES [expr $TX_JESD_L * $TX_NUM_LINKS] +set TX_NUM_OF_CONVERTERS [expr $TX_JESD_M * $TX_NUM_LINKS] +set TX_SAMPLES_PER_FRAME $TX_JESD_S +set TX_SAMPLE_WIDTH $TX_JESD_NP + +set TX_DMA_SAMPLE_WIDTH $TX_JESD_NP +if {$TX_DMA_SAMPLE_WIDTH == 12} { + set TX_DMA_SAMPLE_WIDTH 16 +} + +set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_JESD_L $TX_JESD_M $TX_JESD_S $TX_JESD_NP] + +set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8* $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] + +set adc_data_offload_name apollo_rx_data_offload +set adc_data_width [expr $RX_DMA_SAMPLE_WIDTH*$RX_NUM_OF_CONVERTERS*$RX_SAMPLES_PER_CHANNEL] +set adc_dma_data_width $adc_data_width +set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))] + +set dac_data_offload_name apollo_tx_data_offload +set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_PER_CHANNEL] +set dac_dma_data_width $dac_data_width +set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))] + +set num_quads_a [expr int(ceil(1.0 * $RX_NUM_OF_LANES / 4))] +set num_quads_b 0 + +if {$ASYMMETRIC_A_B_MODE} { + # RX B Side JESD parameter per link + set RX_B_JESD_M $ad_project_params(RX_B_JESD_M) + set RX_B_JESD_L $ad_project_params(RX_B_JESD_L) + set RX_B_JESD_S $ad_project_params(RX_B_JESD_S) + set RX_B_JESD_NP $ad_project_params(RX_B_JESD_NP) + + set RX_B_NUM_OF_LANES $RX_B_JESD_L + set RX_B_NUM_OF_CONVERTERS $RX_B_JESD_M + set RX_B_SAMPLES_PER_FRAME $RX_B_JESD_S + set RX_B_SAMPLE_WIDTH $RX_B_JESD_NP + + set RX_B_DMA_SAMPLE_WIDTH $RX_B_JESD_NP + if {$RX_B_DMA_SAMPLE_WIDTH == 12} { + set RX_B_DMA_SAMPLE_WIDTH 16 + } + + set RX_B_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_B_JESD_L $RX_B_JESD_M $RX_B_JESD_S $RX_B_JESD_NP] + + set RX_B_SAMPLES_PER_CHANNEL [expr $RX_B_NUM_OF_LANES * 8 * $RX_B_DATAPATH_WIDTH / ($RX_B_NUM_OF_CONVERTERS * $RX_B_SAMPLE_WIDTH)] + + # TX B Side JESD parameter per link + set TX_B_JESD_M $ad_project_params(TX_B_JESD_M) + set TX_B_JESD_L $ad_project_params(TX_B_JESD_L) + set TX_B_JESD_S $ad_project_params(TX_B_JESD_S) + set TX_B_JESD_NP $ad_project_params(TX_B_JESD_NP) + + set TX_B_NUM_OF_LANES $TX_B_JESD_L + set TX_B_NUM_OF_CONVERTERS $TX_B_JESD_M + set TX_B_SAMPLES_PER_FRAME $TX_B_JESD_S + set TX_B_SAMPLE_WIDTH $TX_B_JESD_NP + + set TX_B_DMA_SAMPLE_WIDTH $TX_B_JESD_NP + if {$TX_B_DMA_SAMPLE_WIDTH == 12} { + set TX_B_DMA_SAMPLE_WIDTH 16 + } + + set TX_B_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_B_JESD_L $TX_B_JESD_M $TX_B_JESD_S $TX_B_JESD_NP] + + set TX_B_SAMPLES_PER_CHANNEL [expr $TX_B_NUM_OF_LANES * 8 * $TX_B_DATAPATH_WIDTH / ($TX_B_NUM_OF_CONVERTERS * $TX_B_SAMPLE_WIDTH)] + + set adc_b_data_offload_name apollo_rx_b_data_offload + set adc_b_data_width [expr $RX_B_DMA_SAMPLE_WIDTH*$RX_B_NUM_OF_CONVERTERS*$RX_B_SAMPLES_PER_CHANNEL] + set adc_b_dma_data_width $adc_b_data_width + set adc_b_fifo_address_width [expr int(ceil(log(($adc_b_fifo_samples_per_converter*$RX_B_NUM_OF_CONVERTERS) / ($adc_b_data_width/$RX_B_DMA_SAMPLE_WIDTH))/log(2)))] + + set dac_b_data_offload_name apollo_tx_b_data_offload + set dac_b_data_width [expr $TX_B_DMA_SAMPLE_WIDTH*$TX_B_NUM_OF_CONVERTERS*$TX_B_SAMPLES_PER_CHANNEL] + set dac_b_dma_data_width $dac_b_data_width + set dac_b_fifo_address_width [expr int(ceil(log(($dac_b_fifo_samples_per_converter*$TX_B_NUM_OF_CONVERTERS) / ($dac_b_data_width/$TX_B_DMA_SAMPLE_WIDTH))/log(2)))] + + set num_quads_b [expr int(ceil(1.0 * $RX_B_NUM_OF_LANES / 4))] +} + +set num_quads [expr $num_quads_a + $num_quads_b] + +create_bd_port -dir I rx_device_clk +create_bd_port -dir I tx_device_clk +create_bd_port -dir I rx_b_device_clk +create_bd_port -dir I tx_b_device_clk + +##AXI_HSCI IP +if {$HSCI_ENABLE} { + if {$ADI_PHY_SEL} { + create_bd_port -dir O selectio_clk_in + create_bd_port -dir O hsci_pll_reset + create_bd_port -dir O -from 7 -to 0 hsci_menc_clk + create_bd_port -dir O -from 7 -to 0 hsci_data_out + create_bd_port -dir I -from 7 -to 0 hsci_data_in + create_bd_port -dir I hsci_pclk + create_bd_port -dir I hsci_rst_seq_done + create_bd_port -dir I hsci_pll_locked + create_bd_port -dir I hsci_vtc_rdy_bsc_tx + create_bd_port -dir I hsci_dly_rdy_bsc_tx + create_bd_port -dir I hsci_vtc_rdy_bsc_rx + create_bd_port -dir I hsci_dly_rdy_bsc_rx + + ad_ip_instance axi_hsci axi_hsci_0 + ad_connect axi_hsci_0/hsci_miso_data hsci_data_in + ad_connect axi_hsci_0/hsci_menc_clk hsci_menc_clk + ad_connect axi_hsci_0/hsci_pclk hsci_pclk + ad_connect axi_hsci_0/hsci_rst_seq_done hsci_rst_seq_done + ad_connect axi_hsci_0/hsci_pll_locked hsci_pll_locked + ad_connect axi_hsci_0/hsci_vtc_rdy_bsc_tx hsci_vtc_rdy_bsc_tx + ad_connect axi_hsci_0/hsci_dly_rdy_bsc_tx hsci_dly_rdy_bsc_tx + ad_connect axi_hsci_0/hsci_vtc_rdy_bsc_rx hsci_vtc_rdy_bsc_rx + ad_connect axi_hsci_0/hsci_dly_rdy_bsc_rx hsci_dly_rdy_bsc_rx + ad_connect hsci_data_out axi_hsci_0/hsci_mosi_data + ad_connect hsci_pll_reset axi_hsci_0/hsci_pll_reset + + ad_ip_instance axi_clkgen axi_hsci_clkgen + ad_ip_parameter axi_hsci_clkgen CONFIG.ID 1 + ad_ip_parameter axi_hsci_clkgen CONFIG.CLKIN_PERIOD 10 + ad_ip_parameter axi_hsci_clkgen CONFIG.VCO_DIV 1 + ad_ip_parameter axi_hsci_clkgen CONFIG.VCO_MUL 8 + ad_ip_parameter axi_hsci_clkgen CONFIG.CLK0_DIV 4 + + ad_connect axi_ddr_cntrl/addn_ui_clkout1 axi_hsci_clkgen/clk + ad_connect selectio_clk_in axi_hsci_clkgen/clk_0 + } else { + source ../common/versal_hsci_phy.tcl + create_hsci_phy hsci_phy $HSCI_BANKS + + ad_ip_instance axi_hsci axi_hsci_0 + + create_bd_port -dir O intf_rdy + create_bd_port -dir O fifo_empty + create_bd_port -dir O data_out_p + create_bd_port -dir O data_out_n + create_bd_port -dir O clk_out_p + create_bd_port -dir O clk_out_n + create_bd_port -dir O -from 7 -to 0 data_to_fabric + create_bd_port -dir O -from 7 -to 0 hsci_data_out + + create_bd_port -dir I fifo_rd_en + create_bd_port -dir I data_in_p + create_bd_port -dir I data_in_n + create_bd_port -dir I clk_in_p + create_bd_port -dir I clk_in_n + create_bd_port -dir I -from 7 -to 0 hsci_data_in + create_bd_port -dir I -from 7 -to 0 data_from_fabric + + ad_connect axi_hsci_0/hsci_miso_data hsci_data_in + ad_connect hsci_data_out axi_hsci_0/hsci_mosi_data + + ad_connect hsci_phy/data_from_fabric_data_out data_from_fabric + ad_connect hsci_phy/data_from_fabric_clk_out axi_hsci_0/hsci_menc_clk + + ad_connect hsci_phy/fifo_rd_en fifo_rd_en + ad_connect hsci_phy/data_in_p data_in_p + ad_connect hsci_phy/data_in_n data_in_n + ad_connect hsci_phy/clk_in_p clk_in_p + ad_connect hsci_phy/clk_in_n clk_in_n + ad_connect hsci_phy/bank0_pll_clkout0 hsci_phy/fifo_rd_clk + ad_connect hsci_phy/bank0_pll_clkout0 axi_hsci_0/hsci_pclk + ad_connect hsci_phy/bank0_pll_clkout0 hsci_phy/ctrl_clk + ad_connect hsci_phy/en_vtc VCC + ad_connect hsci_phy/t_data_out GND + ad_connect hsci_phy/t_clk_out GND + + ad_ip_instance xlconcat hsci_pll_locked_concat [list \ + NUM_PORTS ${HSCI_BANKS} \ + ] + ad_connect hsci_pll_locked_concat/In0 hsci_phy/bank0_pll_locked + if {$HSCI_BANKS > 1} { + ad_connect hsci_pll_locked_concat/In1 hsci_phy/bank1_pll_locked + } + + ad_connect hsci_pll_locked_concat/dout axi_hsci_0/hsci_pll_locked + + ad_connect hsci_phy/phy_rdy axi_hsci_0/hsci_vtc_rdy_bsc_tx + ad_connect hsci_phy/dly_rdy axi_hsci_0/hsci_dly_rdy_bsc_tx + ad_connect hsci_phy/phy_rdy axi_hsci_0/hsci_vtc_rdy_bsc_rx + ad_connect hsci_phy/dly_rdy axi_hsci_0/hsci_dly_rdy_bsc_rx + ad_connect hsci_phy/intf_rdy axi_hsci_0/hsci_rst_seq_done + + ad_connect intf_rdy hsci_phy/intf_rdy + ad_connect fifo_empty hsci_phy/fifo_empty + ad_connect data_to_fabric hsci_phy/data_to_fabric_data_in + ad_connect data_out_p hsci_phy/data_out_p + ad_connect data_out_n hsci_phy/data_out_n + ad_connect clk_out_p hsci_phy/clk_out_p + ad_connect clk_out_n hsci_phy/clk_out_n + + ad_ip_instance axi_clkgen axi_hsci_clkgen + ad_ip_parameter axi_hsci_clkgen CONFIG.ID 1 + ad_ip_parameter axi_hsci_clkgen CONFIG.CLKIN_PERIOD 10 + ad_ip_parameter axi_hsci_clkgen CONFIG.VCO_DIV 1 + ad_ip_parameter axi_hsci_clkgen CONFIG.VCO_MUL 30 + ad_ip_parameter axi_hsci_clkgen CONFIG.CLK0_DIV 15 + + ad_connect $sys_cpu_clk axi_hsci_clkgen/clk + ad_connect axi_hsci_0/hsci_pll_reset hsci_phy/rst + for {set i 0} {$i < $HSCI_BANKS} {incr i} { + ad_connect axi_hsci_clkgen/clk_0 hsci_phy/bank${i}_pll_clkin + ad_connect axi_hsci_0/hsci_pll_reset hsci_phy/bank${i}_pll_rst_pll + } + } +} + +# common xcvr +if {$ASYMMETRIC_A_B_MODE} { + set MAX_RX_LANE_RATE [expr max($RX_LANE_RATE, $RX_B_LANE_RATE)] + set MAX_TX_LANE_RATE [expr max($TX_LANE_RATE, $TX_B_LANE_RATE)] +} else { + set MAX_RX_LANE_RATE $RX_LANE_RATE + set MAX_TX_LANE_RATE $TX_LANE_RATE +} + +if {$ADI_PHY_SEL} { + ad_ip_instance util_adxcvr util_apollo_xcvr + ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_FBDIV_4_5 5 + ad_ip_parameter util_apollo_xcvr CONFIG.TX_NUM_OF_LANES $MAX_APOLLO_LANES + ad_ip_parameter util_apollo_xcvr CONFIG.RX_NUM_OF_LANES $MAX_APOLLO_LANES + ad_ip_parameter util_apollo_xcvr CONFIG.RX_OUT_DIV 1 + ad_ip_parameter util_apollo_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter util_apollo_xcvr CONFIG.RX_LANE_RATE $MAX_RX_LANE_RATE + ad_ip_parameter util_apollo_xcvr CONFIG.TX_LANE_RATE $MAX_TX_LANE_RATE + + ad_ip_instance axi_adxcvr axi_apollo_rx_xcvr + ad_ip_parameter axi_apollo_rx_xcvr CONFIG.ID 0 + ad_ip_parameter axi_apollo_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter axi_apollo_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES + ad_ip_parameter axi_apollo_rx_xcvr CONFIG.TX_OR_RX_N 0 + ad_ip_parameter axi_apollo_rx_xcvr CONFIG.QPLL_ENABLE 0 + ad_ip_parameter axi_apollo_rx_xcvr CONFIG.LPM_OR_DFE_N 1 + ad_ip_parameter axi_apollo_rx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0 + + ad_ip_instance axi_adxcvr axi_apollo_tx_xcvr + ad_ip_parameter axi_apollo_tx_xcvr CONFIG.ID 0 + ad_ip_parameter axi_apollo_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter axi_apollo_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES + ad_ip_parameter axi_apollo_tx_xcvr CONFIG.TX_OR_RX_N 1 + ad_ip_parameter axi_apollo_tx_xcvr CONFIG.QPLL_ENABLE 1 + ad_ip_parameter axi_apollo_tx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0 +} else { + source ../common/versal_transceiver.tcl + + # Reset gpios + create_bd_port -dir O gt_powergood + create_bd_port -dir I gt_reset + create_bd_port -dir I gt_reset_rx_datapath + create_bd_port -dir I gt_reset_rx_pll_and_datapath + create_bd_port -dir I gt_reset_tx_datapath + create_bd_port -dir I gt_reset_tx_pll_and_datapath + create_bd_port -dir O rx_resetdone + create_bd_port -dir O tx_resetdone + + create_bd_port -dir I gt_b_reset + create_bd_port -dir I gt_b_reset_rx_datapath + create_bd_port -dir I gt_b_reset_rx_pll_and_datapath + create_bd_port -dir I gt_b_reset_tx_datapath + create_bd_port -dir I gt_b_reset_tx_pll_and_datapath + create_bd_port -dir O rx_b_resetdone + create_bd_port -dir O tx_b_resetdone + + create_bd_port -dir I ref_clk_a + create_bd_port -dir I ref_clk_b + create_bd_port -dir I rx_sysref_0 + create_bd_port -dir I tx_sysref_0 + create_bd_port -dir I rx_sysref_12 + create_bd_port -dir I tx_sysref_12 + create_bd_port -dir O rx_sync_12 + create_bd_port -dir I tx_sync_12 + create_bd_port -dir O -from [expr $RX_NUM_LINKS - 1] -to 0 rx_sync_0 + create_bd_port -dir I -from [expr $RX_NUM_LINKS - 1] -to 0 tx_sync_0 + + set REF_CLK_RATE $ad_project_params(REF_CLK_RATE) + # instantiate versal phy + create_versal_phy jesd204_phy $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX + # reset generator + ad_ip_instance proc_sys_reset rx_device_clk_rstgen + ad_connect rx_device_clk rx_device_clk_rstgen/slowest_sync_clk + ad_connect $sys_cpu_resetn rx_device_clk_rstgen/ext_reset_in + + ad_ip_instance proc_sys_reset tx_device_clk_rstgen + ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk + ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in + + ad_connect gt_reset jesd204_phy/gtreset_in + ad_connect gt_reset_rx_datapath jesd204_phy/gtreset_rx_datapath + ad_connect gt_reset_rx_pll_and_datapath jesd204_phy/gtreset_rx_pll_and_datapath + ad_connect gt_reset_tx_datapath jesd204_phy/gtreset_tx_datapath + ad_connect gt_reset_tx_pll_and_datapath jesd204_phy/gtreset_tx_pll_and_datapath + ad_connect rx_resetdone jesd204_phy/rx_resetdone + ad_connect tx_resetdone jesd204_phy/tx_resetdone + + # gt powergood + ad_ip_instance xlconcat gt_powergood_concat [list \ + NUM_PORTS 2 \ + ] + ad_ip_instance util_reduced_logic gt_powergood_and [list \ + C_SIZE $num_quads \ + ] + ad_connect jesd204_phy/gtpowergood gt_powergood_concat/In0 + if {!$ASYMMETRIC_A_B_MODE} { + ad_connect VCC gt_powergood_concat/In1 + } + ad_connect gt_powergood_concat/dout gt_powergood_and/Op1 + ad_connect gt_powergood_and/Res gt_powergood +} + +if {$ASYMMETRIC_A_B_MODE} { + if ($ADI_PHY_SEL) { + ad_ip_instance axi_adxcvr axi_apollo_rx_b_xcvr + ad_ip_parameter axi_apollo_rx_b_xcvr CONFIG.ID 0 + ad_ip_parameter axi_apollo_rx_b_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter axi_apollo_rx_b_xcvr CONFIG.NUM_OF_LANES $RX_B_NUM_OF_LANES + ad_ip_parameter axi_apollo_rx_b_xcvr CONFIG.TX_OR_RX_N 0 + ad_ip_parameter axi_apollo_rx_b_xcvr CONFIG.QPLL_ENABLE 0 + ad_ip_parameter axi_apollo_rx_b_xcvr CONFIG.LPM_OR_DFE_N 1 + ad_ip_parameter axi_apollo_rx_b_xcvr CONFIG.SYS_CLK_SEL 0x2 ; # QPLL1 + + ad_ip_instance axi_adxcvr axi_apollo_tx_b_xcvr + ad_ip_parameter axi_apollo_tx_b_xcvr CONFIG.ID 0 + ad_ip_parameter axi_apollo_tx_b_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter axi_apollo_tx_b_xcvr CONFIG.NUM_OF_LANES $TX_B_NUM_OF_LANES + ad_ip_parameter axi_apollo_tx_b_xcvr CONFIG.TX_OR_RX_N 1 + ad_ip_parameter axi_apollo_tx_b_xcvr CONFIG.QPLL_ENABLE 1 + ad_ip_parameter axi_apollo_tx_b_xcvr CONFIG.SYS_CLK_SEL 0x2 ; # QPLL1 + } else { + # instantiate versal phy + create_versal_phy jesd204_phy_b $JESD_MODE $RX_B_NUM_OF_LANES $TX_B_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX + + ad_connect gt_b_reset jesd204_phy_b/gtreset_in + ad_connect gt_b_reset_rx_datapath jesd204_phy_b/gtreset_rx_datapath + ad_connect gt_b_reset_rx_pll_and_datapath jesd204_phy_b/gtreset_rx_pll_and_datapath + ad_connect gt_b_reset_tx_datapath jesd204_phy_b/gtreset_tx_datapath + ad_connect gt_b_reset_tx_pll_and_datapath jesd204_phy_b/gtreset_tx_pll_and_datapath + ad_connect rx_b_resetdone jesd204_phy_b/rx_resetdone + ad_connect tx_b_resetdone jesd204_phy_b/tx_resetdone + + ad_connect jesd204_phy_b/gtpowergood gt_powergood_concat/In1 + # reset generator + ad_ip_instance proc_sys_reset rx_b_device_clk_rstgen + ad_connect rx_b_device_clk rx_b_device_clk_rstgen/slowest_sync_clk + ad_connect $sys_cpu_resetn rx_b_device_clk_rstgen/ext_reset_in + + ad_ip_instance proc_sys_reset tx_b_device_clk_rstgen + ad_connect tx_b_device_clk tx_b_device_clk_rstgen/slowest_sync_clk + ad_connect $sys_cpu_resetn tx_b_device_clk_rstgen/ext_reset_in + } +} + +# adc peripherals + +adi_axi_jesd204_rx_create axi_apollo_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_DATAPATH_WIDTH + +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.SYSREF_IOB false +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 1 + +adi_tpl_jesd204_rx_create rx_apollo_tpl_core $RX_NUM_OF_LANES \ + $RX_NUM_OF_CONVERTERS \ + $RX_SAMPLES_PER_FRAME \ + $RX_SAMPLE_WIDTH \ + $RX_DATAPATH_WIDTH \ + $RX_DMA_SAMPLE_WIDTH + +ad_ip_instance util_cpack2 util_apollo_cpack [list \ + NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH \ +] + +set adc_data_offload_size [expr $adc_data_width / 8 * 2**$adc_fifo_address_width] +ad_data_offload_create $adc_data_offload_name \ + 0 \ + $adc_do_mem_type \ + $adc_data_offload_size \ + $adc_data_width \ + $adc_data_width \ + $do_axi_data_width \ + $SHARED_DEVCLK + +ad_ip_instance axi_dmac axi_apollo_rx_dma +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.ID 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.AXI_SLICE_SRC 1 +ad_ip_parameter axi_apollo_rx_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_apollo_rx_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_LENGTH_WIDTH 24 +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096 +ad_ip_parameter axi_apollo_rx_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_data_width +if {$ADI_PHY_SEL} { + ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_data_width +} else { + # Versal limitation + ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_data_width)] +} + +if {$ASYMMETRIC_A_B_MODE} { + adi_axi_jesd204_rx_create axi_apollo_rx_b_jesd $RX_B_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL + ad_ip_parameter axi_apollo_rx_b_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_B_DATAPATH_WIDTH + + ad_ip_parameter axi_apollo_rx_b_jesd/rx CONFIG.SYSREF_IOB false + ad_ip_parameter axi_apollo_rx_b_jesd/rx CONFIG.NUM_INPUT_PIPELINE 1 + + adi_tpl_jesd204_rx_create rx_b_apollo_tpl_core $RX_B_NUM_OF_LANES \ + $RX_B_NUM_OF_CONVERTERS \ + $RX_B_SAMPLES_PER_FRAME \ + $RX_B_SAMPLE_WIDTH \ + $RX_B_DATAPATH_WIDTH \ + $RX_B_DMA_SAMPLE_WIDTH + + ad_ip_instance util_cpack2 util_apollo_cpack_b [list \ + NUM_OF_CHANNELS $RX_B_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $RX_B_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $RX_B_DMA_SAMPLE_WIDTH \ + ] + + set adc_b_data_offload_size [expr $adc_b_data_width / 8 * 2**$adc_b_fifo_address_width] + ad_data_offload_create $adc_b_data_offload_name \ + 0 \ + $adc_do_mem_type \ + $adc_b_data_offload_size \ + $adc_b_data_width \ + $adc_b_data_width \ + $do_axi_data_width \ + $SHARED_DEVCLK + + ad_ip_instance axi_dmac axi_apollo_rx_b_dma + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.DMA_TYPE_SRC 1 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.DMA_TYPE_DEST 0 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.ID 0 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.AXI_SLICE_SRC 1 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.AXI_SLICE_DEST 1 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.SYNC_TRANSFER_START 0 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.DMA_LENGTH_WIDTH 24 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.DMA_2D_TRANSFER 0 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.MAX_BYTES_PER_BURST 4096 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.CYCLIC 0 + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_b_data_width + if {$ADI_PHY_SEL} { + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_b_data_width + } else { + # Versal limitation + ad_ip_parameter axi_apollo_rx_b_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_b_data_width)] + } +} + +# dac peripherals + +adi_axi_jesd204_tx_create axi_apollo_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL +ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.TPL_DATA_PATH_WIDTH $TX_DATAPATH_WIDTH + +ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.SYSREF_IOB false +#ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 + +adi_tpl_jesd204_tx_create tx_apollo_tpl_core $TX_NUM_OF_LANES \ + $TX_NUM_OF_CONVERTERS \ + $TX_SAMPLES_PER_FRAME \ + $TX_SAMPLE_WIDTH \ + $TX_DATAPATH_WIDTH \ + $TX_DMA_SAMPLE_WIDTH + +ad_ip_parameter tx_apollo_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0 + +ad_ip_instance util_upack2 util_apollo_upack [list \ + NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \ +] + +set dac_data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width] +ad_data_offload_create $dac_data_offload_name \ + 1 \ + $dac_do_mem_type \ + $dac_data_offload_size \ + $dac_data_width \ + $dac_data_width \ + $do_axi_data_width \ + $SHARED_DEVCLK + +ad_ip_instance axi_dmac axi_apollo_tx_dma +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_apollo_tx_dma CONFIG.ID 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.AXI_SLICE_SRC 1 +ad_ip_parameter axi_apollo_tx_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_apollo_tx_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_LENGTH_WIDTH 24 +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_apollo_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096 +if {$ADI_PHY_SEL} { + ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC $dac_data_width +} else { + # Versal limitation + ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_data_width)] +} +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width + +if {$ASYMMETRIC_A_B_MODE} { + adi_axi_jesd204_tx_create axi_apollo_tx_b_jesd $TX_B_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL + ad_ip_parameter axi_apollo_tx_b_jesd/tx CONFIG.TPL_DATA_PATH_WIDTH $TX_B_DATAPATH_WIDTH + + ad_ip_parameter axi_apollo_tx_b_jesd/tx CONFIG.SYSREF_IOB false + #ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 + + adi_tpl_jesd204_tx_create tx_b_apollo_tpl_core $TX_B_NUM_OF_LANES \ + $TX_B_NUM_OF_CONVERTERS \ + $TX_B_SAMPLES_PER_FRAME \ + $TX_B_SAMPLE_WIDTH \ + $TX_B_DATAPATH_WIDTH \ + $TX_B_DMA_SAMPLE_WIDTH + + ad_ip_parameter tx_b_apollo_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0 + + ad_ip_instance util_upack2 util_apollo_upack_b [list \ + NUM_OF_CHANNELS $TX_B_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $TX_B_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $TX_B_DMA_SAMPLE_WIDTH \ + ] + + set dac_b_data_offload_size [expr $dac_b_data_width / 8 * 2**$dac_b_fifo_address_width] + ad_data_offload_create $dac_b_data_offload_name \ + 1 \ + $dac_do_mem_type \ + $dac_b_data_offload_size \ + $dac_b_data_width \ + $dac_b_data_width \ + $do_axi_data_width \ + $SHARED_DEVCLK + + ad_ip_instance axi_dmac axi_apollo_tx_b_dma + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.DMA_TYPE_SRC 0 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.DMA_TYPE_DEST 1 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.ID 0 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.AXI_SLICE_SRC 1 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.AXI_SLICE_DEST 1 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.SYNC_TRANSFER_START 0 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.DMA_LENGTH_WIDTH 24 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.DMA_2D_TRANSFER 0 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.CYCLIC 1 + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.MAX_BYTES_PER_BURST 4096 + if {$ADI_PHY_SEL} { + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.DMA_DATA_WIDTH_SRC $dac_b_data_width + } else { + # Versal limitation + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_b_data_width)] + } + ad_ip_parameter axi_apollo_tx_b_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_b_data_width +} + +# reference clocks & resets + +if {$ADI_PHY_SEL} { + for {set i 0} {$i < $MAX_APOLLO_LANES} {incr i} { + set quad_index [expr int($i / 4)] + if {[expr $i % 4] == 0} { + create_bd_port -dir I ref_clk_q$quad_index + ad_xcvrpll ref_clk_q$quad_index util_apollo_xcvr/qpll_ref_clk_$i + } + ad_xcvrpll ref_clk_q$quad_index util_apollo_xcvr/cpll_ref_clk_$i + } + + for {set i 0} {$i < [expr max($MAX_TX_LANES,$MAX_RX_LANES)]} {incr i} { + set j [expr $i + [expr max($MAX_TX_LANES,$MAX_RX_LANES)]] + ad_xcvrpll axi_apollo_tx_xcvr/up_pll_rst util_apollo_xcvr/up_qpll_rst_${i} + ad_xcvrpll axi_apollo_rx_xcvr/up_pll_rst util_apollo_xcvr/up_cpll_rst_${i} + ad_xcvrpll axi_apollo_tx_b_xcvr/up_pll_rst util_apollo_xcvr/up_qpll_rst_${j} + ad_xcvrpll axi_apollo_rx_b_xcvr/up_pll_rst util_apollo_xcvr/up_cpll_rst_${j} + } + + ad_connect $sys_cpu_resetn util_apollo_xcvr/up_rstn + ad_connect $sys_cpu_clk util_apollo_xcvr/up_clk +} else { + ad_connect ref_clk_a jesd204_phy/GT_REFCLK + + for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} { + ad_connect axi_apollo_rx_jesd/rx_phy${j} jesd204_phy/rx${j} + ad_connect axi_apollo_tx_jesd/tx_phy${j} jesd204_phy/tx${j} + } + + ad_connect jesd204_phy/rxusrclk_out /axi_apollo_rx_jesd/link_clk + ad_connect rx_device_clk /axi_apollo_rx_jesd/device_clk + + ad_connect jesd204_phy/txusrclk_out /axi_apollo_tx_jesd/link_clk + ad_connect tx_device_clk /axi_apollo_tx_jesd/device_clk + + ad_connect axi_apollo_rx_jesd/sysref rx_sysref_0 + ad_connect axi_apollo_tx_jesd/sysref tx_sysref_0 + + ad_connect $sys_cpu_clk jesd204_phy/s_axi_clk + ad_connect $sys_cpu_resetn jesd204_phy/s_axi_resetn + + if {$JESD_MODE == "8B10B"} { + ad_connect axi_apollo_rx_jesd/phy_en_char_align jesd204_phy/en_char_align + ad_connect axi_apollo_rx_jesd/sync rx_sync_0 + } else { + ad_connect GND jesd204_phy/en_char_align + } + if {$JESD_MODE == "8B10B"} { + ad_connect axi_apollo_tx_jesd/sync tx_sync_0 + } + + if {$ASYMMETRIC_A_B_MODE} { + ad_connect ref_clk_b jesd204_phy_b/GT_REFCLK + + for {set j 0} {$j < $RX_B_NUM_OF_LANES} {incr j} { + ad_connect axi_apollo_rx_b_jesd/rx_phy${j} jesd204_phy_b/rx${j} + ad_connect axi_apollo_tx_b_jesd/tx_phy${j} jesd204_phy_b/tx${j} + } + + ad_connect jesd204_phy_b/rxusrclk_out /axi_apollo_rx_b_jesd/link_clk + ad_connect rx_b_device_clk /axi_apollo_rx_b_jesd/device_clk + + ad_connect jesd204_phy_b/txusrclk_out /axi_apollo_tx_b_jesd/link_clk + ad_connect tx_b_device_clk /axi_apollo_tx_b_jesd/device_clk + + ad_connect axi_apollo_rx_b_jesd/sysref rx_sysref_12 + ad_connect axi_apollo_tx_b_jesd/sysref tx_sysref_12 + + ad_connect $sys_cpu_clk jesd204_phy_b/s_axi_clk + ad_connect $sys_cpu_resetn jesd204_phy_b/s_axi_resetn + if {$JESD_MODE == "8B10B"} { + ad_connect axi_apollo_rx_b_jesd/phy_en_char_align jesd204_phy_b/en_char_align + ad_connect axi_apollo_rx_b_jesd/sync rx_sync_12 + } else { + ad_connect GND jesd204_phy_b/en_char_align + } + if {$JESD_MODE == "8B10B"} { + ad_connect axi_apollo_tx_b_jesd/sync tx_sync_0 + } + } + + # Export serial interfaces + for {set j 0} {$j < $num_quads} {incr j} { + if {$j < $num_quads_a} { + create_bd_port -dir I -from 3 -to 0 rx_${j}_p + create_bd_port -dir I -from 3 -to 0 rx_${j}_n + create_bd_port -dir O -from 3 -to 0 tx_${j}_p + create_bd_port -dir O -from 3 -to 0 tx_${j}_n + ad_connect rx_${j}_p jesd204_phy/rx_${j}_p + ad_connect rx_${j}_n jesd204_phy/rx_${j}_n + ad_connect tx_${j}_p jesd204_phy/tx_${j}_p + ad_connect tx_${j}_n jesd204_phy/tx_${j}_n + } else { + set jj [expr $j - $num_quads_a] + create_bd_port -dir I -from 3 -to 0 rx_${j}_p + create_bd_port -dir I -from 3 -to 0 rx_${j}_n + create_bd_port -dir O -from 3 -to 0 tx_${j}_p + create_bd_port -dir O -from 3 -to 0 tx_${j}_n + ad_connect rx_${j}_p jesd204_phy_b/rx_${jj}_p + ad_connect rx_${j}_n jesd204_phy_b/rx_${jj}_n + ad_connect tx_${j}_p jesd204_phy_b/tx_${jj}_p + ad_connect tx_${j}_n jesd204_phy_b/tx_${jj}_n + } + } + + if {$num_quads < $MAX_NUMBER_OF_QUADS} { + # Create dummy ports for non-existing lanes + for {set j $num_quads} {$j < $MAX_NUMBER_OF_QUADS} {incr j} { + create_bd_port -dir I -from 3 -to 0 rx_${j}_p + create_bd_port -dir I -from 3 -to 0 rx_${j}_n + create_bd_port -dir O -from 3 -to 0 tx_${j}_p + create_bd_port -dir O -from 3 -to 0 tx_${j}_n + } + # for {set j $num_quads_b} {$j < 1} {incr j} { + # create_bd_port -dir I -from 3 -to 0 GT_Serial _${j}_0_grx_p + # create_bd_port -dir I -from 3 -to 0 GT_Serial_${j}_0_grx_n + # create_bd_port -dir O -from 3 -to 0 GT_Serial_${j}_0_gtx_p + # create_bd_port -dir O -from 3 -to 0 GT_Serial_${j}_0_gtx_n + # } + + # for {set j $num_quads_a} {$j < 2} {incr j} { + # create_bd_port -dir I -from 3 -to 0 GT_Serial_A_${j}_0_grx_p + # create_bd_port -dir I -from 3 -to 0 GT_Serial_A_${j}_0_grx_n + # create_bd_port -dir O -from 3 -to 0 GT_Serial_A_${j}_0_gtx_p + # create_bd_port -dir O -from 3 -to 0 GT_Serial_A_${j}_0_gtx_n + # } + } +} + +# connections (adc) +# map the logical lane $n onto the physical lane $lane_map[$n] +# n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 +# lane_map = {11 2 3 5 10 1 9 0 6 7 8 4 15 21 17 16 14 18 13 19 20 23 12 22} +# + +if {$ASYMMETRIC_A_B_MODE} { + if {$ADI_PHY_SEL} { + # set lane_map {11 2 3 5 10 1 9 0 6 7 8 4} + ad_xcvrcon util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd {0 1 2 3 4 5 6 7 8 9 10 11} {} rx_device_clk $MAX_RX_LANES + + # set lane_map {15 21 17 16 14 18 13 19 20 23 12 22} + ad_xcvrcon util_apollo_xcvr axi_apollo_rx_b_xcvr axi_apollo_rx_b_jesd {12 13 14 15 16 17 18 19 20 21 22 23} {} rx_b_device_clk $MAX_RX_LANES + } +} else { + set max_lane_map {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23} + # set lane_map {} + + # for {set i 0} {$i < $RX_NUM_LINKS} {incr i} { + # for {set j 0} {$j < $RX_JESD_L} {incr j} { + # set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j] + # lappend lane_map [lindex $max_lane_map $cur_lane] + # } + # } + if {$ADI_PHY_SEL} { + ad_xcvrcon util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd $max_lane_map {} rx_device_clk $MAX_RX_LANES + create_bd_port -dir I rx_sysref_12 + create_bd_port -dir O rx_sync_12 + } +} + +# connections (dac) +# map the logical lane $n onto the physical lane $lane_map[$n] +# n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 +# lane_map = {11 5 10 6 8 4 9 7 1 2 0 3 15 16 14 19 12 20 13 17 21 22 18 23} +# + +if {$ASYMMETRIC_A_B_MODE} { + if {$ADI_PHY_SEL} { + # set lane_map {11 5 10 6 8 4 9 7 1 2 0 3} + ad_xcvrcon util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd {0 1 2 3 4 5 6 7 8 9 10 11} {} tx_device_clk $MAX_TX_LANES + + # set lane_map {15 16 14 19 12 20 13 17 21 22 18 23} + ad_xcvrcon util_apollo_xcvr axi_apollo_tx_b_xcvr axi_apollo_tx_b_jesd {12 13 14 15 16 17 18 19 20 21 22 23} {} tx_b_device_clk $MAX_TX_LANES + } +} else { + set max_lane_map {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23} + # set lane_map {} + + # for {set i 0} {$i < $TX_NUM_LINKS} {incr i} { + # for {set j 0} {$j < $TX_JESD_L} {incr j} { + # set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j] + # lappend lane_map [lindex $max_lane_map $cur_lane] + # } + # } + if {$ADI_PHY_SEL} { + ad_xcvrcon util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd $max_lane_map {} tx_device_clk $MAX_TX_LANES + create_bd_port -dir I tx_sysref_12 + create_bd_port -dir I tx_sync_12 + } +} + +# device clock domain +ad_connect rx_device_clk rx_apollo_tpl_core/link_clk +ad_connect rx_device_clk util_apollo_cpack/clk +ad_connect rx_device_clk $adc_data_offload_name/s_axis_aclk + +ad_connect tx_device_clk tx_apollo_tpl_core/link_clk +ad_connect tx_device_clk util_apollo_upack/clk +ad_connect tx_device_clk $dac_data_offload_name/m_axis_aclk + +if {$ASYMMETRIC_A_B_MODE} { + ad_connect rx_b_device_clk rx_b_apollo_tpl_core/link_clk + ad_connect rx_b_device_clk util_apollo_cpack_b/clk + ad_connect rx_b_device_clk $adc_b_data_offload_name/s_axis_aclk + + ad_connect tx_b_device_clk tx_b_apollo_tpl_core/link_clk + ad_connect tx_b_device_clk util_apollo_upack_b/clk + ad_connect tx_b_device_clk $dac_b_data_offload_name/m_axis_aclk +} + +# Clocks +ad_connect $sys_dma_clk $adc_data_offload_name/m_axis_aclk +ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk + +ad_connect $sys_dma_clk axi_apollo_rx_dma/s_axis_aclk +ad_connect $sys_dma_clk axi_apollo_tx_dma/m_axis_aclk +ad_connect $sys_cpu_clk $dac_data_offload_name/s_axi_aclk +ad_connect $sys_cpu_clk $adc_data_offload_name/s_axi_aclk + +if {$ASYMMETRIC_A_B_MODE} { + ad_connect $sys_dma_clk $adc_b_data_offload_name/m_axis_aclk + ad_connect $sys_dma_clk $dac_b_data_offload_name/s_axis_aclk + + ad_connect $sys_dma_clk axi_apollo_rx_b_dma/s_axis_aclk + ad_connect $sys_dma_clk axi_apollo_tx_b_dma/m_axis_aclk + ad_connect $sys_cpu_clk $dac_b_data_offload_name/s_axi_aclk + ad_connect $sys_cpu_clk $adc_b_data_offload_name/s_axi_aclk +} + +# Resets +# create_bd_port -dir O rx_device_clk_rstn +# ad_connect rx_device_clk_rstn rx_device_clk_rstgen/peripheral_aresetn + +ad_connect rx_device_clk_rstgen/peripheral_aresetn $adc_data_offload_name/s_axis_aresetn +ad_connect $sys_dma_resetn $adc_data_offload_name/m_axis_aresetn +ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn +ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn + +ad_connect $sys_dma_resetn axi_apollo_rx_dma/m_dest_axi_aresetn +ad_connect $sys_dma_resetn axi_apollo_tx_dma/m_src_axi_aresetn +ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn +ad_connect $sys_cpu_resetn $adc_data_offload_name/s_axi_aresetn + +if {$ASYMMETRIC_A_B_MODE} { + ad_connect rx_b_device_clk_rstgen/peripheral_aresetn $adc_b_data_offload_name/s_axis_aresetn + ad_connect $sys_dma_resetn $adc_b_data_offload_name/m_axis_aresetn + ad_connect tx_b_device_clk_rstgen/peripheral_aresetn $dac_b_data_offload_name/m_axis_aresetn + ad_connect $sys_dma_resetn $dac_b_data_offload_name/s_axis_aresetn + + ad_connect $sys_dma_resetn axi_apollo_rx_b_dma/m_dest_axi_aresetn + ad_connect $sys_dma_resetn axi_apollo_tx_b_dma/m_src_axi_aresetn + ad_connect $sys_cpu_resetn $dac_b_data_offload_name/s_axi_aresetn + ad_connect $sys_cpu_resetn $adc_b_data_offload_name/s_axi_aresetn +} + +# +# connect adc dataflow +# +# Connect Link Layer to Transport Layer +# +ad_connect axi_apollo_rx_jesd/rx_sof rx_apollo_tpl_core/link_sof +ad_connect axi_apollo_rx_jesd/rx_data_tdata rx_apollo_tpl_core/link_data +ad_connect axi_apollo_rx_jesd/rx_data_tvalid rx_apollo_tpl_core/link_valid + +ad_connect rx_apollo_tpl_core/adc_valid_0 util_apollo_cpack/fifo_wr_en +for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { + ad_connect rx_apollo_tpl_core/adc_enable_$i util_apollo_cpack/enable_$i + ad_connect rx_apollo_tpl_core/adc_data_$i util_apollo_cpack/fifo_wr_data_$i +} +ad_connect rx_apollo_tpl_core/adc_dovf util_apollo_cpack/fifo_wr_overflow + +ad_connect util_apollo_cpack/packed_fifo_wr_data $adc_data_offload_name/s_axis_tdata +ad_connect util_apollo_cpack/packed_fifo_wr_en $adc_data_offload_name/s_axis_tvalid +ad_connect $adc_data_offload_name/s_axis_tlast GND +ad_connect $adc_data_offload_name/s_axis_tkeep VCC + +ad_connect $adc_data_offload_name/m_axis axi_apollo_rx_dma/s_axis + +if {$ASYMMETRIC_A_B_MODE} { + ad_connect axi_apollo_rx_b_jesd/rx_sof rx_b_apollo_tpl_core/link_sof + ad_connect axi_apollo_rx_b_jesd/rx_data_tdata rx_b_apollo_tpl_core/link_data + ad_connect axi_apollo_rx_b_jesd/rx_data_tvalid rx_b_apollo_tpl_core/link_valid + + ad_connect rx_b_apollo_tpl_core/adc_valid_0 util_apollo_cpack_b/fifo_wr_en + for {set i 0} {$i < $RX_B_NUM_OF_CONVERTERS} {incr i} { + ad_connect rx_b_apollo_tpl_core/adc_enable_$i util_apollo_cpack_b/enable_$i + ad_connect rx_b_apollo_tpl_core/adc_data_$i util_apollo_cpack_b/fifo_wr_data_$i + } + ad_connect rx_b_apollo_tpl_core/adc_dovf util_apollo_cpack_b/fifo_wr_overflow + + ad_connect util_apollo_cpack_b/packed_fifo_wr_data $adc_b_data_offload_name/s_axis_tdata + ad_connect util_apollo_cpack_b/packed_fifo_wr_en $adc_b_data_offload_name/s_axis_tvalid + ad_connect $adc_b_data_offload_name/s_axis_tlast GND + ad_connect $adc_b_data_offload_name/s_axis_tkeep VCC + + ad_connect $adc_b_data_offload_name/m_axis axi_apollo_rx_b_dma/s_axis +} + +# connect dac dataflow +# + +# Connect Link Layer to Transport Layer +# +ad_connect tx_apollo_tpl_core/link axi_apollo_tx_jesd/tx_data + +ad_connect tx_apollo_tpl_core/dac_valid_0 util_apollo_upack/fifo_rd_en +for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { + ad_connect util_apollo_upack/fifo_rd_data_$i tx_apollo_tpl_core/dac_data_$i + ad_connect tx_apollo_tpl_core/dac_enable_$i util_apollo_upack/enable_$i +} + +ad_connect $dac_data_offload_name/s_axis axi_apollo_tx_dma/m_axis + +ad_connect util_apollo_upack/s_axis $dac_data_offload_name/m_axis + +ad_connect $dac_data_offload_name/init_req axi_apollo_tx_dma/m_axis_xfer_req +ad_connect $adc_data_offload_name/init_req axi_apollo_rx_dma/s_axis_xfer_req +ad_connect tx_apollo_tpl_core/dac_dunf GND + +if {$ASYMMETRIC_A_B_MODE} { + ad_connect tx_b_apollo_tpl_core/link axi_apollo_tx_b_jesd/tx_data + + ad_connect tx_b_apollo_tpl_core/dac_valid_0 util_apollo_upack_b/fifo_rd_en + for {set i 0} {$i < $TX_B_NUM_OF_CONVERTERS} {incr i} { + ad_connect util_apollo_upack_b/fifo_rd_data_$i tx_b_apollo_tpl_core/dac_data_$i + ad_connect tx_b_apollo_tpl_core/dac_enable_$i util_apollo_upack_b/enable_$i + } + + ad_connect $dac_b_data_offload_name/s_axis axi_apollo_tx_b_dma/m_axis + + ad_connect util_apollo_upack_b/s_axis $dac_b_data_offload_name/m_axis + + ad_connect $dac_b_data_offload_name/init_req axi_apollo_tx_b_dma/m_axis_xfer_req + ad_connect $adc_b_data_offload_name/init_req axi_apollo_rx_b_dma/s_axis_xfer_req + ad_connect tx_b_apollo_tpl_core/dac_dunf GND +} + +# interconnect (cpu) + +if {$ADI_PHY_SEL} { + ad_cpu_interconnect 0x44a60000 axi_apollo_rx_xcvr + ad_cpu_interconnect 0x44b60000 axi_apollo_tx_xcvr +} else { + # ad_cpu_interconnect 0x44a40000 jesd204_phy +} +ad_cpu_interconnect 0x44a10000 rx_apollo_tpl_core +ad_cpu_interconnect 0x44b10000 tx_apollo_tpl_core +ad_cpu_interconnect 0x44a90000 axi_apollo_rx_jesd +ad_cpu_interconnect 0x44b90000 axi_apollo_tx_jesd +ad_cpu_interconnect 0x7c420000 axi_apollo_rx_dma +ad_cpu_interconnect 0x7c430000 axi_apollo_tx_dma +ad_cpu_interconnect 0x7c440000 $dac_data_offload_name +ad_cpu_interconnect 0x7c450000 $adc_data_offload_name +if {$HSCI_ENABLE} { + ad_cpu_interconnect 0x44ad0000 axi_hsci_clkgen + ad_cpu_interconnect 0x7c500000 axi_hsci_0 +} +# Reserved for TDD! 0x7c460000 + +if {$ASYMMETRIC_A_B_MODE} { + if {$ADI_PHY_SEL} { + ad_cpu_interconnect 0x44aa0000 axi_apollo_rx_b_xcvr + ad_cpu_interconnect 0x44ba0000 axi_apollo_tx_b_xcvr + } else { + # ad_cpu_interconnect 0x45a40000 jesd204_phy_b + } + ad_cpu_interconnect 0x44ab0000 rx_b_apollo_tpl_core + ad_cpu_interconnect 0x44bb0000 tx_b_apollo_tpl_core + ad_cpu_interconnect 0x44ac0000 axi_apollo_rx_b_jesd + ad_cpu_interconnect 0x44bc0000 axi_apollo_tx_b_jesd + ad_cpu_interconnect 0x7c470000 axi_apollo_rx_b_dma + ad_cpu_interconnect 0x7c480000 axi_apollo_tx_b_dma + ad_cpu_interconnect 0x7c490000 $dac_b_data_offload_name + ad_cpu_interconnect 0x7c4a0000 $adc_b_data_offload_name +} + +# interconnect (gt/adc) + +if ${ADI_PHY_SEL} { + ad_mem_hp0_interconnect $sys_cpu_clk axi_apollo_rx_xcvr/m_axi +} +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_dma_clk axi_apollo_rx_dma/m_dest_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect $sys_dma_clk axi_apollo_tx_dma/m_src_axi + +if {$ASYMMETRIC_A_B_MODE} { + if ${ADI_PHY_SEL} { + ad_mem_hp0_interconnect $sys_cpu_clk axi_apollo_rx_b_xcvr/m_axi + } + ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 + ad_mem_hp1_interconnect $sys_dma_clk axi_apollo_rx_b_dma/m_dest_axi + ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 + ad_mem_hp2_interconnect $sys_dma_clk axi_apollo_tx_b_dma/m_src_axi +} + +# interrupts + +ad_cpu_interrupt ps-13 mb-12 axi_apollo_rx_dma/irq +ad_cpu_interrupt ps-12 mb-13 axi_apollo_tx_dma/irq +ad_cpu_interrupt ps-11 mb-14 axi_apollo_rx_jesd/irq +ad_cpu_interrupt ps-10 mb-15 axi_apollo_tx_jesd/irq + +if {$ASYMMETRIC_A_B_MODE} { + ad_cpu_interrupt ps-4 mb-5 axi_apollo_rx_b_dma/irq + ad_cpu_interrupt ps-3 mb-6 axi_apollo_tx_b_dma/irq + ad_cpu_interrupt ps-2 mb-7 axi_apollo_rx_b_jesd/irq + ad_cpu_interrupt ps-1 mb-8 axi_apollo_tx_b_jesd/irq +} + +# +# Sync at TPL level +# + +create_bd_port -dir I ext_sync_in + +# Enable ADC external sync +ad_ip_parameter rx_apollo_tpl_core/adc_tpl_core CONFIG.EXT_SYNC 1 +ad_connect ext_sync_in rx_apollo_tpl_core/adc_tpl_core/adc_sync_in + +# Enable DAC external sync +ad_ip_parameter tx_apollo_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1 +ad_connect ext_sync_in tx_apollo_tpl_core/dac_tpl_core/dac_sync_in + +ad_ip_instance util_vector_logic manual_sync_or [list \ + C_SIZE 1 \ + C_OPERATION {or} \ +] + +ad_connect rx_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or/Op1 +ad_connect tx_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or/Op2 + +if {$ASYMMETRIC_A_B_MODE == 0} { + ad_connect manual_sync_or/Res tx_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_in + ad_connect manual_sync_or/Res rx_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_in +} else { + # Enable ADC B side external sync + ad_ip_parameter rx_b_apollo_tpl_core/adc_tpl_core CONFIG.EXT_SYNC 1 + ad_connect ext_sync_in rx_b_apollo_tpl_core/adc_tpl_core/adc_sync_in + + # Enable DAC B side external sync + ad_ip_parameter tx_b_apollo_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1 + ad_connect ext_sync_in tx_b_apollo_tpl_core/dac_tpl_core/dac_sync_in + + ad_ip_instance util_vector_logic manual_sync_or_b [list \ + C_SIZE 1 \ + C_OPERATION {or} \ + ] + + ad_connect rx_b_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or_b/Op1 + ad_connect tx_b_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or_b/Op2 + + ad_ip_instance util_vector_logic manual_sync_or_res [list \ + C_SIZE 1 \ + C_OPERATION {or} \ + ] + + ad_connect manual_sync_or/Res manual_sync_or_res/Op1 + ad_connect manual_sync_or_b/Res manual_sync_or_res/Op2 + + ad_connect manual_sync_or_res/Res tx_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_in + ad_connect manual_sync_or_res/Res rx_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_in + ad_connect manual_sync_or_res/Res tx_b_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_in + ad_connect manual_sync_or_res/Res rx_b_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_in +} + +# Reset pack cores +ad_ip_instance util_reduced_logic cpack_rst_logic +ad_ip_parameter cpack_rst_logic config.c_operation {or} +ad_ip_parameter cpack_rst_logic config.c_size {3} + +ad_ip_instance util_vector_logic rx_do_rstout_logic +ad_ip_parameter rx_do_rstout_logic config.c_operation {not} +ad_ip_parameter rx_do_rstout_logic config.c_size {1} + +ad_connect $adc_data_offload_name/s_axis_tready rx_do_rstout_logic/Op1 + +ad_ip_instance xlconcat cpack_reset_sources +ad_ip_parameter cpack_reset_sources config.num_ports {3} +ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0 +ad_connect rx_apollo_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1 +ad_connect rx_do_rstout_logic/res cpack_reset_sources/in2 + +ad_connect cpack_reset_sources/dout cpack_rst_logic/op1 +ad_connect cpack_rst_logic/res util_apollo_cpack/reset + +if {$ASYMMETRIC_A_B_MODE} { + ad_ip_instance util_reduced_logic cpack_b_rst_logic + ad_ip_parameter cpack_b_rst_logic config.c_operation {or} + ad_ip_parameter cpack_b_rst_logic config.c_size {3} + + ad_ip_instance util_vector_logic rx_b_do_rstout_logic + ad_ip_parameter rx_b_do_rstout_logic config.c_operation {not} + ad_ip_parameter rx_b_do_rstout_logic config.c_size {1} + + ad_connect $adc_b_data_offload_name/s_axis_tready rx_b_do_rstout_logic/Op1 + + ad_ip_instance xlconcat cpack_b_reset_sources + ad_ip_parameter cpack_b_reset_sources config.num_ports {3} + ad_connect rx_b_device_clk_rstgen/peripheral_reset cpack_b_reset_sources/in0 + ad_connect rx_b_apollo_tpl_core/adc_tpl_core/adc_rst cpack_b_reset_sources/in1 + ad_connect rx_b_do_rstout_logic/res cpack_b_reset_sources/in2 + + ad_connect cpack_b_reset_sources/dout cpack_b_rst_logic/op1 + ad_connect cpack_b_rst_logic/res util_apollo_cpack_b/reset +} + +# Reset unpack cores +ad_ip_instance util_reduced_logic upack_rst_logic +ad_ip_parameter upack_rst_logic config.c_operation {or} +ad_ip_parameter upack_rst_logic config.c_size {2} + +ad_ip_instance xlconcat upack_reset_sources +ad_ip_parameter upack_reset_sources config.num_ports {2} +ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0 +ad_connect tx_apollo_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1 + +ad_connect upack_reset_sources/dout upack_rst_logic/op1 +ad_connect upack_rst_logic/res util_apollo_upack/reset + +if {$ASYMMETRIC_A_B_MODE} { + ad_ip_instance util_reduced_logic upack_b_rst_logic + ad_ip_parameter upack_b_rst_logic config.c_operation {or} + ad_ip_parameter upack_b_rst_logic config.c_size {2} + + ad_ip_instance xlconcat upack_b_reset_sources + ad_ip_parameter upack_b_reset_sources config.num_ports {2} + ad_connect tx_b_device_clk_rstgen/peripheral_reset upack_b_reset_sources/in0 + ad_connect tx_b_apollo_tpl_core/dac_tpl_core/dac_rst upack_b_reset_sources/in1 + + ad_connect upack_b_reset_sources/dout upack_b_rst_logic/op1 + ad_connect upack_b_rst_logic/res util_apollo_upack_b/reset +} + +if {$TDD_SUPPORT} { + ad_ip_instance util_tdd_sync tdd_sync_0 + ad_connect tx_device_clk tdd_sync_0/clk + ad_connect tx_device_clk_rstgen/peripheral_aresetn tdd_sync_0/rstn + ad_connect tdd_sync_0/sync_in GND + ad_connect tdd_sync_0/sync_mode GND + ad_ip_parameter tdd_sync_0 CONFIG.TDD_SYNC_PERIOD 250000000; # More or less 1 PPS ;) + + ad_ip_instance axi_tdd axi_tdd_0 [list ASYNC_TDD_SYNC 0] + ad_connect tx_device_clk axi_tdd_0/clk + ad_connect tx_device_clk_rstgen/peripheral_reset axi_tdd_0/rst + ad_connect $sys_cpu_clk axi_tdd_0/s_axi_aclk + ad_connect $sys_cpu_resetn axi_tdd_0/s_axi_aresetn + ad_cpu_interconnect 0x7c460000 axi_tdd_0 + + ad_connect tdd_sync_0/sync_out axi_tdd_0/tdd_sync + + delete_bd_objs [get_bd_nets apollo_adc_fifo_dma_wr] + + ad_connect axi_tdd_0/tdd_tx_valid $dac_data_offload_name/sync_ext + ad_connect axi_tdd_0/tdd_rx_valid $adc_data_offload_name/sync_ext + +} else { + ad_connect GND $dac_data_offload_name/sync_ext + ad_connect GND $adc_data_offload_name/sync_ext + + if {$ASYMMETRIC_A_B_MODE} { + ad_connect GND $dac_b_data_offload_name/sync_ext + ad_connect GND $adc_b_data_offload_name/sync_ext + } +} \ No newline at end of file diff --git a/projects/ad9084_ebz/common/ad9084_ebz_qsys.tcl b/projects/ad9084_ebz/common/ad9084_ebz_qsys.tcl new file mode 100644 index 00000000000..c867807b107 --- /dev/null +++ b/projects/ad9084_ebz/common/ad9084_ebz_qsys.tcl @@ -0,0 +1,646 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Common parameter for TX and RX +set JESD_MODE $ad_project_params(JESD_MODE) +set RX_LANE_RATE [expr $ad_project_params(RX_LANE_RATE) * 1000] +set TX_LANE_RATE [expr $ad_project_params(TX_LANE_RATE) * 1000] + +set ASYMMETRIC_A_B_MODE [ expr { [info exists ad_project_params(ASYMMETRIC_A_B_MODE)] \ + ? $ad_project_params(ASYMMETRIC_A_B_MODE) : 0 } ] +if {$ASYMMETRIC_A_B_MODE} { + error "ASYMMETRIC_A_B_MODE not supported for this carrier!" +} + +set HSCI_ENABLE [ expr { [info exists ad_project_params(HSCI_ENABLE)] \ + ? $ad_project_params(HSCI_ENABLE) : 0 } ] +set adc_do_mem_type [ expr { [info exists ad_project_params(ADC_DO_MEM_TYPE)] \ + ? $ad_project_params(ADC_DO_MEM_TYPE) : 0 } ] +set dac_do_mem_type [ expr { [info exists ad_project_params(DAC_DO_MEM_TYPE)] \ + ? $ad_project_params(DAC_DO_MEM_TYPE) : 0 } ] +set do_axi_data_width [ expr { [info exists do_axi_data_width] \ + ? $do_axi_data_width : 256 } ] + +if {$JESD_MODE == "8B10B"} { + set ENCODER_SEL 1 +} else { + set ENCODER_SEL 2 +} + +# These are max values specific to the board +set MAX_RX_LANES_PER_LINK 12 +set MAX_TX_LANES_PER_LINK 12 +set MAX_RX_LINKS [expr $ASYMMETRIC_A_B_MODE ? 1 : 2] +set MAX_TX_LINKS [expr $ASYMMETRIC_A_B_MODE ? 1 : 2] +set MAX_RX_LANES [expr $MAX_RX_LANES_PER_LINK*$MAX_RX_LINKS] +set MAX_TX_LANES [expr $MAX_TX_LANES_PER_LINK*$MAX_TX_LINKS] +set MAX_APOLLO_LANES 24 + +# RX parameters +set RX_NUM_LINKS $ad_project_params(RX_NUM_LINKS) + +# RX JESD parameter per link +set RX_JESD_M $ad_project_params(RX_JESD_M) +set RX_JESD_L $ad_project_params(RX_JESD_L) +set RX_JESD_S $ad_project_params(RX_JESD_S) +set RX_JESD_NP $ad_project_params(RX_JESD_NP) + +set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS] +set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS] +set RX_SAMPLES_PER_FRAME $RX_JESD_S +set RX_SAMPLE_WIDTH $RX_JESD_NP + +set RX_DMA_SAMPLE_WIDTH $RX_JESD_NP +if {$RX_DMA_SAMPLE_WIDTH == 12} { + set RX_DMA_SAMPLE_WIDTH 16 +} + +if {$JESD_MODE == "8B10B"} { + set RX_DATAPATH_WIDTH 4 + if {$RX_JESD_NP == 12} { + set RX_DATAPATH_WIDTH 6 + } +} else { + set RX_DATAPATH_WIDTH 8 + if {$RX_JESD_NP == 12} { + set RX_DATAPATH_WIDTH 12 + } +} + +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8* $RX_DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] + +# TX parameters +set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS) +if {$ASYMMETRIC_A_B_MODE} { + set TX_NUM_LINKS 1 +} + +# TX JESD parameter per link +set TX_JESD_M $ad_project_params(TX_JESD_M) +set TX_JESD_L $ad_project_params(TX_JESD_L) +set TX_JESD_S $ad_project_params(TX_JESD_S) +set TX_JESD_NP $ad_project_params(TX_JESD_NP) + +set TX_NUM_OF_LANES [expr $TX_JESD_L * $TX_NUM_LINKS] +set TX_NUM_OF_CONVERTERS [expr $TX_JESD_M * $TX_NUM_LINKS] +set TX_SAMPLES_PER_FRAME $TX_JESD_S +set TX_SAMPLE_WIDTH $TX_JESD_NP + +set TX_DMA_SAMPLE_WIDTH $TX_JESD_NP +if {$TX_DMA_SAMPLE_WIDTH == 12} { + set TX_DMA_SAMPLE_WIDTH 16 +} + +if {$JESD_MODE == "8B10B"} { + set TX_DATAPATH_WIDTH 4 + if {$TX_JESD_NP == 12} { + set TX_DATAPATH_WIDTH 6 + } +} else { + set TX_DATAPATH_WIDTH 8 + if {$TX_JESD_NP == 12} { + set TX_DATAPATH_WIDTH 12 + } +} + +set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8* $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] + +set adc_fifo_name apollo_rx_fifo +set adc_data_width [expr $RX_DMA_SAMPLE_WIDTH*$RX_NUM_OF_CONVERTERS*$RX_SAMPLES_PER_CHANNEL] +set adc_dma_data_width $adc_data_width +set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))] + +set dac_fifo_name apollo_tx_fifo +set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_PER_CHANNEL] +set dac_dma_data_width $dac_data_width +set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))] + +# RX B JESD parameter per link +if {$ASYMMETRIC_A_B_MODE} { + set RX_B_JESD_M $ad_project_params(RX_B_JESD_M) + set RX_B_JESD_L $ad_project_params(RX_B_JESD_L) + set RX_B_JESD_S $ad_project_params(RX_B_JESD_S) + set RX_B_JESD_NP $ad_project_params(RX_B_JESD_NP) + + set RX_B_NUM_OF_LANES [expr $RX_B_JESD_L * $RX_NUM_LINKS] + set RX_B_NUM_OF_CONVERTERS [expr $RX_B_JESD_M * $RX_NUM_LINKS] + set RX_B_SAMPLES_PER_FRAME $RX_B_JESD_S + set RX_B_SAMPLE_WIDTH $RX_B_JESD_NP + + set RX_B_DMA_SAMPLE_WIDTH $RX_B_JESD_NP + if {$RX_B_DMA_SAMPLE_WIDTH == 12} { + set RX_B_DMA_SAMPLE_WIDTH 16 + } + + if {$JESD_MODE == "8B10B"} { + set RX_B_DATAPATH_WIDTH 4 + if {$RX_B_JESD_NP == 12} { + set RX_B_DATAPATH_WIDTH 6 + } + } else { + set RX_B_DATAPATH_WIDTH 8 + if {$RX_B_JESD_NP == 12} { + set RX_B_DATAPATH_WIDTH 12 + } + } + + set RX_B_SAMPLES_PER_CHANNEL [expr $RX_B_NUM_OF_LANES * 8* $RX_B_DATAPATH_WIDTH / ($RX_B_NUM_OF_CONVERTERS * $RX_B_SAMPLE_WIDTH)] + + set adc_b_fifo_name apollo_rx_b_fifo + set adc_b_data_width [expr $RX_B_DMA_SAMPLE_WIDTH*$RX_B_NUM_OF_CONVERTERS*$RX_B_SAMPLES_PER_CHANNEL] + set adc_b_dma_data_width $adc_data_width + set adc_b_fifo_address_width [expr int(ceil(log(($adc_b_fifo_samples_per_converter*$RX_B_NUM_OF_CONVERTERS) / ($adc_b_data_width/$RX_B_DMA_SAMPLE_WIDTH))/log(2)))] +} else { + set RX_B_JESD_M 0 + set RX_B_JESD_L 0 + set RX_B_JESD_S 1 + set RX_B_JESD_NP 16 + + set RX_B_NUM_OF_LANES [expr $RX_B_JESD_L * $RX_NUM_LINKS] + set RX_B_NUM_OF_CONVERTERS [expr $RX_B_JESD_M * $RX_NUM_LINKS] + set RX_B_SAMPLES_PER_FRAME $RX_B_JESD_S + set RX_B_SAMPLE_WIDTH $RX_B_JESD_NP +} + +# TX parameters +set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS) +if {$ASYMMETRIC_A_B_MODE} { + set TX_NUM_LINKS 1 +} + +# TX JESD parameter per link +if {$ASYMMETRIC_A_B_MODE} { + set TX_B_JESD_M $ad_project_params(TX_B_JESD_M) + set TX_B_JESD_L $ad_project_params(TX_B_JESD_L) + set TX_B_JESD_S $ad_project_params(TX_B_JESD_S) + set TX_B_JESD_NP $ad_project_params(TX_B_JESD_NP) + + set TX_B_NUM_OF_LANES [expr $TX_B_JESD_L * $TX_NUM_LINKS] + set TX_B_NUM_OF_CONVERTERS [expr $TX_B_JESD_M * $TX_NUM_LINKS] + set TX_B_SAMPLES_PER_FRAME $TX_B_JESD_S + set TX_B_SAMPLE_WIDTH $TX_B_JESD_NP + + set TX_B_DMA_SAMPLE_WIDTH $TX_B_JESD_NP + if {$TX_B_DMA_SAMPLE_WIDTH == 12} { + set TX_B_DMA_SAMPLE_WIDTH 16 + } + + if {$JESD_MODE == "8B10B"} { + set TX_B_DATAPATH_WIDTH 4 + if {$TX_B_JESD_NP == 12} { + set TX_B_DATAPATH_WIDTH 6 + } + } else { + set TX_B_DATAPATH_WIDTH 8 + if {$TX_B_JESD_NP == 12} { + set TX_DATAPATH_WIDTH 12 + } + } + + set TX_B_SAMPLES_PER_CHANNEL [expr $TX_B_NUM_OF_LANES * 8* $TX_B_DATAPATH_WIDTH / ($TX_B_NUM_OF_CONVERTERS * $TX_B_SAMPLE_WIDTH)] + + set dac_b_fifo_name apollo_tx_b_fifo + set dac_b_data_width [expr $TX_B_DMA_SAMPLE_WIDTH*$TX_B_NUM_OF_CONVERTERS*$TX_B_SAMPLES_PER_CHANNEL] + set dac_b_dma_data_width $dac_data_width + set dac_b_fifo_address_width [expr int(ceil(log(($dac_b_fifo_samples_per_converter*$TX_B_NUM_OF_CONVERTERS) / ($dac_b_data_width/$TX_B_DMA_SAMPLE_WIDTH))/log(2)))] +} else { + set TX_B_JESD_M 0 + set TX_B_JESD_L 0 + set TX_B_JESD_S 1 + set TX_B_JESD_NP 16 + + set TX_B_NUM_OF_LANES [expr $TX_B_JESD_L * $TX_NUM_LINKS] + set TX_B_NUM_OF_CONVERTERS [expr $TX_B_JESD_M * $TX_NUM_LINKS] + set TX_B_SAMPLES_PER_FRAME $TX_B_JESD_S + set TX_B_SAMPLE_WIDTH $TX_B_JESD_NP +} + +# Reference Clock Rate = Lane Rate / 40 or Lane Rate / 66 +set REF_CLK_RATE $ad_project_params(REF_CLK_RATE) + +# Device Clock Rate +set DEVICE_CLK_RATE [expr $ad_project_params(DEVICE_CLK_RATE)*1000000] + +# JESD204B clock bridges + +add_instance rx_device_clk altera_clock_bridge +set_instance_parameter_value rx_device_clk {EXPLICIT_CLOCK_RATE} $DEVICE_CLK_RATE + +add_instance tx_device_clk altera_clock_bridge +set_instance_parameter_value tx_device_clk {EXPLICIT_CLOCK_RATE} $DEVICE_CLK_RATE + +# RX JESD204 PHY-Link layer + +add_instance apollo_rx_jesd204 adi_jesd204 +set_instance_parameter_value apollo_rx_jesd204 {ID} {0} +set_instance_parameter_value apollo_rx_jesd204 {LINK_MODE} $ENCODER_SEL +set_instance_parameter_value apollo_rx_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value apollo_rx_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value apollo_rx_jesd204 {LANE_RATE} $RX_LANE_RATE +set_instance_parameter_value apollo_rx_jesd204 {SYSCLK_FREQUENCY} {100.0} +set_instance_parameter_value apollo_rx_jesd204 {REFCLK_FREQUENCY} $REF_CLK_RATE +set_instance_parameter_value apollo_rx_jesd204 {INPUT_PIPELINE_STAGES} {2} +set_instance_parameter_value apollo_rx_jesd204 {NUM_OF_LANES} [expr $RX_NUM_OF_LANES + $RX_B_NUM_OF_LANES] +set_instance_parameter_value apollo_rx_jesd204 {EXT_DEVICE_CLK_EN} {1} +set_instance_parameter_value apollo_rx_jesd204 {DATA_PATH_WIDTH} $RX_DATAPATH_WIDTH +set_instance_parameter_value apollo_rx_jesd204 {TPL_DATA_PATH_WIDTH} $RX_DATAPATH_WIDTH + +add_instance apollo_rx_tpl ad_ip_jesd204_tpl_adc +set_instance_parameter_value apollo_rx_tpl {ID} {0} +set_instance_parameter_value apollo_rx_tpl {NUM_CHANNELS} [expr $RX_NUM_OF_CONVERTERS + $RX_B_NUM_OF_CONVERTERS] +set_instance_parameter_value apollo_rx_tpl {NUM_LANES} [expr $RX_NUM_OF_LANES + $RX_B_NUM_OF_LANES] +set_instance_parameter_value apollo_rx_tpl {BITS_PER_SAMPLE} $RX_SAMPLE_WIDTH +set_instance_parameter_value apollo_rx_tpl {CONVERTER_RESOLUTION} $RX_SAMPLE_WIDTH +set_instance_parameter_value apollo_rx_tpl {TWOS_COMPLEMENT} {1} +set_instance_parameter_value apollo_rx_tpl {OCTETS_PER_BEAT} $RX_DATAPATH_WIDTH +set_instance_parameter_value apollo_rx_tpl {DMA_BITS_PER_SAMPLE} $RX_DMA_SAMPLE_WIDTH + +# TX JESD204 PHY+Link + +add_instance apollo_tx_jesd204 adi_jesd204 +set_instance_parameter_value apollo_tx_jesd204 {ID} {0} +set_instance_parameter_value apollo_tx_jesd204 {LINK_MODE} $ENCODER_SEL +set_instance_parameter_value apollo_tx_jesd204 {TX_OR_RX_N} {1} +set_instance_parameter_value apollo_tx_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value apollo_tx_jesd204 {LANE_RATE} $TX_LANE_RATE +set_instance_parameter_value apollo_tx_jesd204 {SYSCLK_FREQUENCY} {100.0} +set_instance_parameter_value apollo_tx_jesd204 {REFCLK_FREQUENCY} $REF_CLK_RATE +set_instance_parameter_value apollo_tx_jesd204 {NUM_OF_LANES} [expr $TX_NUM_OF_LANES + $TX_B_NUM_OF_LANES] +set_instance_parameter_value apollo_tx_jesd204 {EXT_DEVICE_CLK_EN} {1} +set_instance_parameter_value apollo_tx_jesd204 {DATA_PATH_WIDTH} $TX_DATAPATH_WIDTH +set_instance_parameter_value apollo_tx_jesd204 {TPL_DATA_PATH_WIDTH} $TX_DATAPATH_WIDTH + +add_instance apollo_tx_tpl ad_ip_jesd204_tpl_dac +set_instance_parameter_value apollo_tx_tpl {ID} {0} +set_instance_parameter_value apollo_tx_tpl {NUM_CHANNELS} [expr $TX_NUM_OF_CONVERTERS + $TX_B_NUM_OF_CONVERTERS] +set_instance_parameter_value apollo_tx_tpl {NUM_LANES} [expr $TX_NUM_OF_LANES + $TX_B_NUM_OF_LANES] +set_instance_parameter_value apollo_tx_tpl {BITS_PER_SAMPLE} $TX_SAMPLE_WIDTH +set_instance_parameter_value apollo_tx_tpl {CONVERTER_RESOLUTION} $TX_SAMPLE_WIDTH +set_instance_parameter_value apollo_tx_tpl {OCTETS_PER_BEAT} $TX_DATAPATH_WIDTH +set_instance_parameter_value apollo_tx_tpl {DMA_BITS_PER_SAMPLE} $TX_DMA_SAMPLE_WIDTH + +# pack(s) & unpack(s) + +add_instance apollo_tx_upack util_upack2 +set_instance_parameter_value apollo_tx_upack {NUM_OF_CHANNELS} $TX_NUM_OF_CONVERTERS +set_instance_parameter_value apollo_tx_upack {SAMPLES_PER_CHANNEL} $TX_SAMPLES_PER_CHANNEL +set_instance_parameter_value apollo_tx_upack {SAMPLE_DATA_WIDTH} $TX_DMA_SAMPLE_WIDTH +set_instance_parameter_value apollo_tx_upack {INTERFACE_TYPE} {1} +set_instance_parameter_value apollo_tx_upack {PARALLEL_OR_SERIAL_N} {1} + +add_instance apollo_rx_cpack util_cpack2 +set_instance_parameter_value apollo_rx_cpack {NUM_OF_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value apollo_rx_cpack {SAMPLES_PER_CHANNEL} $RX_SAMPLES_PER_CHANNEL +set_instance_parameter_value apollo_rx_cpack {SAMPLE_DATA_WIDTH} $RX_DMA_SAMPLE_WIDTH +set_instance_parameter_value apollo_rx_cpack {PARALLEL_OR_SERIAL_N} {1} + +if {$ASYMMETRIC_A_B_MODE} { + add_instance apollo_tx_b_upack util_upack2 + set_instance_parameter_value apollo_tx_b_upack {NUM_OF_CHANNELS} $TX_B_NUM_OF_CONVERTERS + set_instance_parameter_value apollo_tx_b_upack {SAMPLES_PER_CHANNEL} $TX_B_SAMPLES_PER_CHANNEL + set_instance_parameter_value apollo_tx_b_upack {SAMPLE_DATA_WIDTH} $TX_B_DMA_SAMPLE_WIDTH + set_instance_parameter_value apollo_tx_b_upack {INTERFACE_TYPE} {1} + + add_instance apollo_rx_b_cpack util_cpack2 + set_instance_parameter_value apollo_rx_b_cpack {NUM_OF_CHANNELS} $RX_B_NUM_OF_CONVERTERS + set_instance_parameter_value apollo_rx_b_cpack {SAMPLES_PER_CHANNEL} $RX_B_SAMPLES_PER_CHANNEL + set_instance_parameter_value apollo_rx_b_cpack {SAMPLE_DATA_WIDTH} $RX_B_DMA_SAMPLE_WIDTH +} +# RX and TX data offload buffers + +ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width +ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width true + +if {$ASYMMETRIC_A_B_MODE} { + ad_adcfifo_create $adc_b_fifo_name $adc_b_data_width $adc_b_dma_data_width $adc_b_fifo_address_width + ad_dacfifo_create $dac_b_fifo_name $dac_b_data_width $dac_b_dma_data_width $dac_b_fifo_address_width false +} + +# RX and TX DMA instance and connections + +add_instance apollo_tx_dma axi_dmac +set_instance_parameter_value apollo_tx_dma {ID} {0} +set_instance_parameter_value apollo_tx_dma {DMA_DATA_WIDTH_SRC} $dac_dma_data_width +set_instance_parameter_value apollo_tx_dma {DMA_DATA_WIDTH_DEST} $dac_dma_data_width +set_instance_parameter_value apollo_tx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value apollo_tx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value apollo_tx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value apollo_tx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value apollo_tx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value apollo_tx_dma {CYCLIC} {1} +set_instance_parameter_value apollo_tx_dma {DMA_TYPE_DEST} {1} +set_instance_parameter_value apollo_tx_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value apollo_tx_dma {FIFO_SIZE} {16} +set_instance_parameter_value apollo_tx_dma {HAS_AXIS_TLAST} {1} +set_instance_parameter_value apollo_tx_dma {DMA_AXI_PROTOCOL_SRC} {0} +set_instance_parameter_value apollo_tx_dma {MAX_BYTES_PER_BURST} {4096} + +add_instance apollo_rx_dma axi_dmac +set_instance_parameter_value apollo_rx_dma {ID} {0} +set_instance_parameter_value apollo_rx_dma {DMA_DATA_WIDTH_SRC} $adc_dma_data_width +set_instance_parameter_value apollo_rx_dma {DMA_DATA_WIDTH_DEST} $adc_dma_data_width +set_instance_parameter_value apollo_rx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value apollo_rx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value apollo_rx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value apollo_rx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value apollo_rx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value apollo_rx_dma {CYCLIC} {0} +set_instance_parameter_value apollo_rx_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value apollo_rx_dma {DMA_TYPE_SRC} {1} +set_instance_parameter_value apollo_rx_dma {FIFO_SIZE} {16} +set_instance_parameter_value apollo_rx_dma {DMA_AXI_PROTOCOL_DEST} {0} +set_instance_parameter_value apollo_rx_dma {MAX_BYTES_PER_BURST} {4096} + +if {$ASYMMETRIC_A_B_MODE} { + add_instance apollo_tx_b_dma axi_dmac + set_instance_parameter_value apollo_tx_b_dma {ID} {0} + set_instance_parameter_value apollo_tx_b_dma {DMA_DATA_WIDTH_SRC} $dac_b_dma_data_width + set_instance_parameter_value apollo_tx_b_dma {DMA_DATA_WIDTH_DEST} $dac_b_dma_data_width + set_instance_parameter_value apollo_tx_b_dma {DMA_LENGTH_WIDTH} {24} + set_instance_parameter_value apollo_tx_b_dma {DMA_2D_TRANSFER} {0} + set_instance_parameter_value apollo_tx_b_dma {AXI_SLICE_DEST} {0} + set_instance_parameter_value apollo_tx_b_dma {AXI_SLICE_SRC} {0} + set_instance_parameter_value apollo_tx_b_dma {SYNC_TRANSFER_START} {0} + set_instance_parameter_value apollo_tx_b_dma {CYCLIC} {1} + set_instance_parameter_value apollo_tx_b_dma {DMA_TYPE_DEST} {1} + set_instance_parameter_value apollo_tx_b_dma {DMA_TYPE_SRC} {0} + set_instance_parameter_value apollo_tx_b_dma {FIFO_SIZE} {16} + set_instance_parameter_value apollo_tx_b_dma {HAS_AXIS_TLAST} {1} + set_instance_parameter_value apollo_tx_b_dma {DMA_AXI_PROTOCOL_SRC} {0} + set_instance_parameter_value apollo_tx_b_dma {MAX_BYTES_PER_BURST} {2048} + + add_instance apollo_rx_b_dma axi_dmac + set_instance_parameter_value apollo_rx_b_dma {ID} {0} + set_instance_parameter_value apollo_rx_b_dma {DMA_DATA_WIDTH_SRC} $adc_b_dma_data_width + set_instance_parameter_value apollo_rx_b_dma {DMA_DATA_WIDTH_DEST} $adc_b_dma_data_width + set_instance_parameter_value apollo_rx_b_dma {DMA_LENGTH_WIDTH} {24} + set_instance_parameter_value apollo_rx_b_dma {DMA_2D_TRANSFER} {0} + set_instance_parameter_value apollo_rx_b_dma {AXI_SLICE_DEST} {0} + set_instance_parameter_value apollo_rx_b_dma {AXI_SLICE_SRC} {0} + set_instance_parameter_value apollo_rx_b_dma {SYNC_TRANSFER_START} {0} + set_instance_parameter_value apollo_rx_b_dma {CYCLIC} {0} + set_instance_parameter_value apollo_rx_b_dma {DMA_TYPE_DEST} {0} + set_instance_parameter_value apollo_rx_b_dma {DMA_TYPE_SRC} {1} + set_instance_parameter_value apollo_rx_b_dma {FIFO_SIZE} {16} + set_instance_parameter_value apollo_rx_b_dma {DMA_AXI_PROTOCOL_DEST} {0} + set_instance_parameter_value apollo_rx_b_dma {MAX_BYTES_PER_BURST} {2048} +} + +# Apollo GPIO + +add_instance apollo_gpio altera_avalon_pio +set_instance_parameter_value apollo_gpio {direction} {Input} +set_instance_parameter_value apollo_gpio {generateIRQ} {1} +set_instance_parameter_value apollo_gpio {width} {20} +add_connection sys_clk.clk apollo_gpio.clk +add_connection sys_clk.clk_reset apollo_gpio.reset +add_interface apollo_gpio conduit end +set_interface_property apollo_gpio EXPORT_OF apollo_gpio.external_connection + +# +## clocks and resets +# + +# system clock and reset + +add_connection sys_clk.clk apollo_rx_jesd204.sys_clk +add_connection sys_clk.clk apollo_rx_tpl.s_axi_clock +add_connection sys_clk.clk apollo_rx_dma.s_axi_clock +add_connection sys_clk.clk apollo_tx_jesd204.sys_clk +add_connection sys_clk.clk apollo_tx_tpl.s_axi_clock +add_connection sys_clk.clk apollo_tx_dma.s_axi_clock +if {$ASYMMETRIC_A_B_MODE} { + add_connection sys_clk.clk apollo_rx_b_dma.s_axi_clock + add_connection sys_clk.clk apollo_tx_b_dma.s_axi_clock +} + +add_connection sys_clk.clk_reset apollo_rx_jesd204.sys_resetn +add_connection sys_clk.clk_reset apollo_rx_tpl.s_axi_reset +add_connection sys_clk.clk_reset apollo_rx_dma.s_axi_reset +add_connection sys_clk.clk_reset apollo_tx_jesd204.sys_resetn +add_connection sys_clk.clk_reset apollo_tx_tpl.s_axi_reset +add_connection sys_clk.clk_reset apollo_tx_dma.s_axi_reset +if {$ASYMMETRIC_A_B_MODE} { + add_connection sys_clk.clk_reset apollo_rx_b_dma.s_axi_reset + add_connection sys_clk.clk_reset apollo_tx_b_dma.s_axi_reset +} + +# device clock and reset + +add_connection rx_device_clk.out_clk apollo_rx_jesd204.device_clk +add_connection rx_device_clk.out_clk apollo_rx_tpl.link_clk +add_connection rx_device_clk.out_clk apollo_rx_cpack.clk +add_connection rx_device_clk.out_clk $adc_fifo_name.if_adc_clk +if {$ASYMMETRIC_A_B_MODE} { + add_connection rx_device_clk.out_clk apollo_rx_b_cpack.clk + add_connection rx_device_clk.out_clk $adc_b_fifo_name.if_adc_clk +} + +add_connection tx_device_clk.out_clk apollo_tx_jesd204.device_clk +add_connection tx_device_clk.out_clk apollo_tx_tpl.link_clk +add_connection tx_device_clk.out_clk apollo_tx_upack.clk +add_connection tx_device_clk.out_clk $dac_fifo_name.if_dac_clk +if {$ASYMMETRIC_A_B_MODE} { + add_connection tx_device_clk.out_clk apollo_tx_b_upack.clk + add_connection tx_device_clk.out_clk $dac_b_fifo_name.if_dac_clk +} + +add_connection apollo_rx_jesd204.link_reset apollo_rx_cpack.reset +add_connection apollo_rx_jesd204.link_reset $adc_fifo_name.if_adc_rst +if {$ASYMMETRIC_A_B_MODE} { + add_connection apollo_rx_jesd204.link_reset apollo_rx_b_cpack.reset + add_connection apollo_rx_jesd204.link_reset $adc_b_fifo_name.if_adc_rst +} + +add_connection apollo_tx_jesd204.link_reset apollo_tx_upack.reset +add_connection apollo_tx_jesd204.link_reset $dac_fifo_name.if_dac_rst +if {$ASYMMETRIC_A_B_MODE} { + add_connection apollo_tx_jesd204.link_reset apollo_tx_b_upack.reset + add_connection apollo_tx_jesd204.link_reset $dac_b_fifo_name.if_dac_rst +} + +# dma clock and reset + +add_connection sys_dma_clk.clk $adc_fifo_name.if_dma_clk +add_connection sys_dma_clk.clk apollo_rx_dma.if_s_axis_aclk +add_connection sys_dma_clk.clk apollo_rx_dma.m_dest_axi_clock + +add_connection sys_dma_clk.clk_reset apollo_rx_dma.m_dest_axi_reset + +if {$ASYMMETRIC_A_B_MODE} { + add_connection sys_dma_clk.clk $adc_b_fifo_name.if_dma_clk + add_connection sys_dma_clk.clk apollo_rx_b_dma.if_s_axis_aclk + add_connection sys_dma_clk.clk apollo_rx_b_dma.m_dest_axi_clock + + add_connection sys_dma_clk.clk_reset apollo_rx_b_dma.m_dest_axi_reset +} + +add_connection sys_dma_clk.clk $dac_fifo_name.if_dma_clk +add_connection sys_dma_clk.clk apollo_tx_dma.if_m_axis_aclk +add_connection sys_dma_clk.clk apollo_tx_dma.m_src_axi_clock + +if {$ASYMMETRIC_A_B_MODE} { + add_connection sys_dma_clk.clk $dac_b_fifo_name.if_dma_clk + add_connection sys_dma_clk.clk apollo_tx_b_dma.if_m_axis_aclk + add_connection sys_dma_clk.clk apollo_tx_b_dma.m_src_axi_clock + + add_connection sys_dma_clk.clk_reset apollo_tx_b_dma.m_src_axi_reset + add_connection sys_dma_clk.clk_reset $dac_b_fifo_name.if_dma_rst +} + +add_connection sys_dma_clk.clk_reset apollo_tx_dma.m_src_axi_reset +add_connection sys_dma_clk.clk_reset $dac_fifo_name.if_dma_rst + +# +## Exported signals +# + +add_interface rx_ref_clk clock sink +add_interface rx_sysref conduit end +add_interface rx_sync conduit end +add_interface rx_serial_data conduit end +add_interface rx_serial_data_n conduit end + +add_interface tx_ref_clk clock sink +add_interface rx_device_clk clock sink +add_interface tx_serial_data conduit end +add_interface tx_serial_data_n conduit end +add_interface tx_sysref conduit end +add_interface tx_sync conduit end +add_interface tx_device_clk clock sink +add_interface tx_fifo_bypass conduit end +# add_interface tx_b_fifo_bypass conduit end + +set_interface_property rx_ref_clk EXPORT_OF apollo_rx_jesd204.ref_clk +set_interface_property rx_sysref EXPORT_OF apollo_rx_jesd204.sysref +set_interface_property rx_sync EXPORT_OF apollo_rx_jesd204.sync +set_interface_property rx_serial_data EXPORT_OF apollo_rx_jesd204.serial_data +set_interface_property rx_serial_data_n EXPORT_OF apollo_rx_jesd204.serial_data_n +set_interface_property rx_device_clk EXPORT_OF rx_device_clk.in_clk + +set_interface_property tx_ref_clk EXPORT_OF apollo_tx_jesd204.ref_clk +set_interface_property tx_sysref EXPORT_OF apollo_tx_jesd204.sysref +set_interface_property tx_sync EXPORT_OF apollo_tx_jesd204.sync +set_interface_property tx_serial_data EXPORT_OF apollo_tx_jesd204.serial_data +set_interface_property tx_serial_data_n EXPORT_OF apollo_tx_jesd204.serial_data_n +set_interface_property tx_device_clk EXPORT_OF tx_device_clk.in_clk +set_interface_property tx_fifo_bypass EXPORT_OF $dac_fifo_name.if_bypass +if {$ASYMMETRIC_A_B_MODE} { + set_interface_property tx_b_fifo_bypass EXPORT_OF $dac_b_fifo_name.if_bypass +} + +# +## Data interface / data path +# + +# RX link to tpl +add_connection apollo_rx_jesd204.link_sof apollo_rx_tpl.if_link_sof +add_connection apollo_rx_jesd204.link_data apollo_rx_tpl.link_data +# RX tpl to cpack (A side) +for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { + add_connection apollo_rx_tpl.adc_ch_$i apollo_rx_cpack.adc_ch_$i +} +add_connection apollo_rx_tpl.if_adc_dovf $adc_fifo_name.if_adc_wovf +if {$ASYMMETRIC_A_B_MODE} { + # RX tpl to cpack (B side) + for {set i 0} {$i < $RX_B_NUM_OF_CONVERTERS} {incr i} { + set idx [expr $RX_NUM_OF_CONVERTERS + $i] + add_connection apollo_rx_tpl.adc_ch_$idx apollo_rx_b_cpack.adc_ch_$i + } + add_connection apollo_rx_tpl.if_adc_dovf $adc_b_fifo_name.if_adc_wovf + + add_connection apollo_rx_b_cpack.if_packed_fifo_wr_en $adc_b_fifo_name.if_adc_wr + add_connection apollo_rx_b_cpack.if_packed_fifo_wr_data $adc_b_fifo_name.if_adc_wdata +} +# RX cpack to offload +add_connection apollo_rx_cpack.if_packed_fifo_wr_en $adc_fifo_name.if_adc_wr +add_connection apollo_rx_cpack.if_packed_fifo_wr_data $adc_fifo_name.if_adc_wdata + +# RX offload to dma +add_connection $adc_fifo_name.if_dma_xfer_req apollo_rx_dma.if_s_axis_xfer_req +add_connection $adc_fifo_name.m_axis apollo_rx_dma.s_axis +# RX dma to HPS +ad_dma_interconnect apollo_rx_dma.m_dest_axi + +if {$ASYMMETRIC_A_B_MODE} { + add_connection $adc_b_fifo_name.if_dma_xfer_req apollo_rx_b_dma.if_s_axis_xfer_req + add_connection $adc_b_fifo_name.m_axis apollo_rx_b_dma.s_axis + + ad_dma_interconnect apollo_rx_b_dma.m_dest_axi +} + +# TX link to tpl +add_connection apollo_tx_tpl.link_data apollo_tx_jesd204.link_data +# TX tpl to pack (A side) +for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { + add_connection apollo_tx_upack.dac_ch_$i apollo_tx_tpl.dac_ch_$i +} +if {$ASYMMETRIC_A_B_MODE} { + # TX tpl to pack (B side) + for {set i 0} {$i < $TX_B_NUM_OF_CONVERTERS} {incr i} { + set idx [expr $TX_NUM_OF_CONVERTERS + $i] + add_connection apollo_tx_b_upack.dac_ch_$i apollo_tx_tpl.dac_ch_$idx + } + add_connection apollo_tx_b_upack.if_packed_fifo_rd_en $dac_b_fifo_name.if_dac_valid + add_connection $dac_b_fifo_name.if_dac_data apollo_tx_b_upack.if_packed_fifo_rd_data + add_connection $dac_b_fifo_name.if_dac_dunf apollo_tx_tpl.if_dac_dunf +} +# TX pack to offload +add_connection apollo_tx_upack.if_packed_fifo_rd_en $dac_fifo_name.if_dac_valid +add_connection $dac_fifo_name.if_dac_data apollo_tx_upack.if_packed_fifo_rd_data +add_connection $dac_fifo_name.if_dac_dunf apollo_tx_tpl.if_dac_dunf + +# TX offload to dma +add_connection apollo_tx_dma.if_m_axis_xfer_req $dac_fifo_name.if_dma_xfer_req +add_connection apollo_tx_dma.m_axis $dac_fifo_name.s_axis + +# TX dma to HPS +ad_dma_interconnect apollo_tx_dma.m_src_axi + + +if {$ASYMMETRIC_A_B_MODE} { + add_connection apollo_tx_b_dma.if_m_axis_xfer_req $dac_b_fifo_name.if_dma_xfer_req + add_connection apollo_tx_b_dma.m_axis $dac_b_fifo_name.s_axis + + ad_dma_interconnect apollo_tx_b_dma.m_src_axi +} + +# +## address map +# + +## NOTE: if bridge is used, the address will be bridge_base_addr + peripheral_base_addr +# + +ad_cpu_interconnect 0x00000000 apollo_rx_jesd204.phy_reconfig "avl_mm_bridge_0" 0x10000000 25 +ad_cpu_interconnect 0x01000000 apollo_tx_jesd204.phy_reconfig "avl_mm_bridge_0" + +ad_cpu_interconnect 0x000C0000 apollo_rx_jesd204.link_reconfig +ad_cpu_interconnect 0x000C4000 apollo_rx_jesd204.link_management +ad_cpu_interconnect 0x000C8000 apollo_tx_jesd204.link_reconfig +ad_cpu_interconnect 0x000CC000 apollo_tx_jesd204.link_management +ad_cpu_interconnect 0x000D2000 apollo_rx_tpl.s_axi +ad_cpu_interconnect 0x000D4000 apollo_tx_tpl.s_axi +ad_cpu_interconnect 0x000D8000 apollo_rx_dma.s_axi +ad_cpu_interconnect 0x000DC000 apollo_tx_dma.s_axi +if {$ASYMMETRIC_A_B_MODE} { +ad_cpu_interconnect 0x000E0000 apollo_rx_b_dma.s_axi +ad_cpu_interconnect 0x000E4000 apollo_tx_b_dma.s_axi +} +ad_cpu_interconnect 0x000E8000 apollo_gpio.s1 + +# +## interrupts +# + +ad_cpu_interrupt 11 apollo_rx_dma.interrupt_sender +ad_cpu_interrupt 12 apollo_tx_dma.interrupt_sender +if {$ASYMMETRIC_A_B_MODE} { +ad_cpu_interrupt 13 apollo_rx_b_dma.interrupt_sender +ad_cpu_interrupt 14 apollo_tx_b_dma.interrupt_sender +} +ad_cpu_interrupt 15 apollo_rx_jesd204.interrupt +ad_cpu_interrupt 16 apollo_tx_jesd204.interrupt +ad_cpu_interrupt 17 apollo_gpio.irq diff --git a/projects/ad9084_ebz/common/ad9084_ebz_spi.v b/projects/ad9084_ebz/common/ad9084_ebz_spi.v new file mode 100644 index 00000000000..d50281113fd --- /dev/null +++ b/projects/ad9084_ebz/common/ad9084_ebz_spi.v @@ -0,0 +1,92 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad9084_ebz_spi #( + parameter NUM_OF_SLAVES = 8 +) ( + input [NUM_OF_SLAVES-1:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, + input spi_miso_in, + inout spi_sdio +); + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_s = & spi_csn; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io buffer + + assign spi_miso = (spi_csn[0] == 1'b0) ? spi_miso_in : spi_sdio; + assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; + +endmodule \ No newline at end of file diff --git a/projects/ad9084_ebz/common/hsci_phy_top.sv b/projects/ad9084_ebz/common/hsci_phy_top.sv new file mode 100644 index 00000000000..f33212ff13d --- /dev/null +++ b/projects/ad9084_ebz/common/hsci_phy_top.sv @@ -0,0 +1,131 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module hsci_phy_top ( + + input wire pll_inclk, + input wire hsci_pll_reset, + + output logic hsci_pclk, + output logic hsci_mosi_d_p, + output logic hsci_mosi_d_n, + + input wire hsci_miso_d_p, + input wire hsci_miso_d_n, + + output logic hsci_pll_locked, + + output logic hsci_mosi_clk_p, + output logic hsci_mosi_clk_n, + + input wire hsci_miso_clk_p, + input wire hsci_miso_clk_n, + + input wire [7:0] hsci_menc_clk, + input wire [7:0] hsci_mosi_data, + output logic [7:0] hsci_miso_data, + + // Status Signals + output logic vtc_rdy_bsc_tx, + output logic dly_rdy_bsc_tx, + output logic vtc_rdy_bsc_rx, + output logic dly_rdy_bsc_rx, + output logic rst_seq_done + +); + //TX + logic [7:0] hsci_mosi_data_br; + logic rst_seq_done_tx; + logic dly_rdy_bsc0; + logic vtc_rdy_bsc0; + logic dly_rdy_bsc1; + logic vtc_rdy_bsc1; + + // RX + logic [7:0] hsci_miso_data_br; + logic [7:0] hsci_miso_clk_d; + logic fifo_empty_rx; + logic fifo_empty_rx_strobe; + + // PLL + logic shared_pll0_clkoutphy_out; + logic pll0_clkout1; + + assign hsci_mosi_data_br = {hsci_mosi_data[0],hsci_mosi_data[1],hsci_mosi_data[2],hsci_mosi_data[3],hsci_mosi_data[4],hsci_mosi_data[5],hsci_mosi_data[6],hsci_mosi_data[7]}; + + assign hsci_miso_data = rst_seq_done ? {hsci_miso_data_br[0],hsci_miso_data_br[1],hsci_miso_data_br[2],hsci_miso_data_br[3],hsci_miso_data_br[4],hsci_miso_data_br[5],hsci_miso_data_br[6],hsci_miso_data_br[7]} + : 8'h0; + + assign dly_rdy_bsc_tx = dly_rdy_bsc0 & dly_rdy_bsc1; + assign vtc_rdy_bsc_tx = vtc_rdy_bsc0 & vtc_rdy_bsc1; + + high_speed_selectio_wiz_0 hssio_wiz_tx_rx ( + .fifo_rd_clk_32 (hsci_pclk), + .fifo_rd_clk_34 (hsci_pclk), + .fifo_rd_en_32 (1'b0), + .fifo_rd_en_34 (1'b1 & !fifo_empty_rx & rst_seq_done), + .fifo_empty_32 (fifo_empty_rx_strobe), + .fifo_empty_34 (fifo_empty_rx), + .dly_rdy_bsc0 (dly_rdy_bsc0), + .vtc_rdy_bsc0 (vtc_rdy_bsc0), + .en_vtc_bsc0 (1'b1), + .dly_rdy_bsc1 (dly_rdy_bsc1), + .vtc_rdy_bsc1 (vtc_rdy_bsc1), + .en_vtc_bsc1 (1'b1), + .dly_rdy_bsc5 (dly_rdy_bsc_rx), + .vtc_rdy_bsc5 (vtc_rdy_bsc_rx), + .en_vtc_bsc5 (1'b1), + .rst_seq_done (rst_seq_done), + .shared_pll0_clkoutphy_out (shared_pll0_clkoutphy_out), + .pll0_clkout0 (hsci_pclk), + .rst (hsci_pll_reset), + .clk (pll_inclk), + .pll0_locked (hsci_pll_locked), + .clk_out_p (hsci_mosi_clk_p), + .data_from_fabric_clk_out_p (hsci_menc_clk), + .clk_out_n (hsci_mosi_clk_n), + .data_out_p (hsci_mosi_d_p), + .data_from_fabric_data_out_p (hsci_mosi_data_br), + .data_out_n (hsci_mosi_d_n), + .clk_in_p (hsci_miso_clk_p), + .data_to_fabric_clk_in_p (hsci_miso_clk_d), + .clk_in_n (hsci_miso_clk_n), + .data_in_p (hsci_miso_d_p), + .data_to_fabric_data_in_p (hsci_miso_data_br), + .data_in_n (hsci_miso_d_n)); + +endmodule diff --git a/projects/ad9084_ebz/common/trigger_generator.v b/projects/ad9084_ebz/common/trigger_generator.v new file mode 100755 index 00000000000..8dc918e3833 --- /dev/null +++ b/projects/ad9084_ebz/common/trigger_generator.v @@ -0,0 +1,140 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module trigger_generator ( + input wire sysref, + input wire device_clk, + input wire gpio, + input wire rstn, + output reg trigger +); + + localparam STATE_WIDTH = 3; + localparam [STATE_WIDTH-1:0] CALIB_IDLE = 0; + localparam [STATE_WIDTH-1:0] CALIB_START = 1; + localparam [STATE_WIDTH-1:0] IDLE = 2; + localparam [STATE_WIDTH-1:0] SYSREF_SYNC = 3; + localparam [STATE_WIDTH-1:0] START = 4; + localparam [STATE_WIDTH-1:0] TRIGGER = 5; + + reg [STATE_WIDTH-1:0] curr_state = CALIB_IDLE; + reg [STATE_WIDTH-1:0] next_state; + reg [15:0] quarter_count = 'h0000; + reg [15:0] full_count = 'h0000; + reg [15:0] ratio_counter = 'h0000; + reg calib_done = 'b0; + reg sysref_edge = 'b0; + reg sysref_r = 'b0; + reg gpio_edge = 'b0; + reg gpio_r = 'b0; + + wire gpio_sync; + + ad_rst i_gpio_sync ( + .rst_async (gpio), + .clk (device_clk), + .rstn (), + .rst (gpio_sync)); + + always @* begin + case(curr_state) + CALIB_IDLE: next_state = (sysref_edge) ? CALIB_START : CALIB_IDLE; + CALIB_START: next_state = (calib_done == 1'b1) ? IDLE : CALIB_START; + IDLE: next_state = (gpio_edge == 1'b1) ? SYSREF_SYNC : IDLE; + SYSREF_SYNC: next_state = (sysref_edge) ? START : SYSREF_SYNC; + START: next_state = (quarter_count < (ratio_counter / 2) - 2) ? START : TRIGGER; + TRIGGER: next_state = (full_count <= (ratio_counter * 2) + 2) ? TRIGGER : IDLE; + default: next_state = CALIB_IDLE; + endcase + end + + always @(posedge device_clk) begin + if (rstn == 1'b0) begin + curr_state <= CALIB_IDLE; + calib_done <= 1'b0; + ratio_counter <= 'h0000; + end else begin + curr_state <= next_state; + if (curr_state == CALIB_START) begin + if (sysref) begin + ratio_counter <= ratio_counter + 'b1; + end else begin + calib_done <= 'b1; + end + end + end + end + + always @(posedge device_clk) begin + sysref_r <= sysref; + sysref_edge <= (sysref && !sysref_r); + end + + always @(posedge device_clk) begin + gpio_r <= gpio_sync; + gpio_edge <= (gpio_sync && !gpio_r); + end + + always @(posedge device_clk) begin + if (curr_state == START) begin + if (quarter_count < (ratio_counter / 2) - 2) begin + quarter_count <= quarter_count + 'b1; + end else begin + quarter_count <= 0; + end + end + end + + always @(posedge device_clk) begin + if (curr_state == TRIGGER) begin + if (full_count <= (ratio_counter * 2) + 2) begin + full_count <= full_count + 'b1; + end else begin + full_count <= 0; + end + end + end + + always @(posedge device_clk) begin + if (curr_state == TRIGGER) begin + trigger <= 1'b1; + end else begin + trigger <= 1'b0; + end + end + +endmodule diff --git a/projects/ad9084_ebz/common/versal_hsci_phy.tcl b/projects/ad9084_ebz/common/versal_hsci_phy.tcl new file mode 100755 index 00000000000..82d0876a0c7 --- /dev/null +++ b/projects/ad9084_ebz/common/versal_hsci_phy.tcl @@ -0,0 +1,43 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc create_hsci_phy { {ip_name advanced_io_wizard_0} {num_banks 1} } { + + ad_ip_instance advanced_io_wizard ${ip_name} + set_property -dict [list \ + CONFIG.DIFF_IO_T {DIFF_TERM_ADV} \ + CONFIG.DIFFERENTIAL_IO_TERMINATION {TERM_100} \ + CONFIG.BUS_DIR {3} \ + CONFIG.MAX_BANKS ${num_banks} \ + CONFIG.BIDIR_MODE {0} \ + CONFIG.CLK_TO_DATA_ALIGN {3} \ + CONFIG.DATA_SPEED {1600.00} \ + CONFIG.INPUT_CLK_FREQ {200.000} \ + CONFIG.ENABLE_PLLOUT1 {0} \ + CONFIG.PLL0_PLLOUTCLK1 {200.000} \ + CONFIG.SIMPLE_RIU {0} \ + CONFIG.REDUCE_CONTROL_SIG_EN {1} \ + CONFIG.BIT_PERIOD {625} \ + CONFIG.PLL_CLK {34.12539203348543} \ + CONFIG.TX_IOB {74} \ + CONFIG.TX_PHY {80} \ + CONFIG.TX_WINDOW_VAL {471} \ + CONFIG.RX_WINDOW_VAL {509} \ + CONFIG.BUS0_IO_TYPE {DIFF} \ + CONFIG.BUS0_STROBE_NAME {clk_in} \ + CONFIG.BUS0_STROBE_IO_TYPE {DIFF} \ + CONFIG.BUS0_SIG_NAME {data_in} \ + CONFIG.BUS1_DIR {TX} \ + CONFIG.BUS1_IO_TYPE {DIFF} \ + CONFIG.BUS1_SIG_NAME {data_out} \ + CONFIG.BUS2_DIR {TX} \ + CONFIG.BUS2_IO_TYPE {DIFF} \ + CONFIG.BUS2_SIG_TYPE {Clk Fwd} \ + CONFIG.BUS2_SIG_NAME {clk_out} \ + CONFIG.BUS12_WRCLK_EN {0} \ + CONFIG.DIFF_IO_STD {LVDS15} \ + CONFIG.ENABLE_BLI {0} \ + ] [get_bd_cells ${ip_name}] +} diff --git a/projects/ad9084_ebz/common/versal_transceiver.tcl b/projects/ad9084_ebz/common/versal_transceiver.tcl new file mode 100644 index 00000000000..37ee0754a2e --- /dev/null +++ b/projects/ad9084_ebz/common/versal_transceiver.tcl @@ -0,0 +1,1179 @@ +############################################################################### +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Parameter description: +# ip_name : The name of the versal phy ip +# rx_num_lanes : The number of used RX lanes for the JESD mode +# tx_num_lanes : The number of used TX lanes for the JESD mode +proc create_reset_logic { + {ip_name versal_phy} + {rx_num_lanes 4} + {tx_num_lanes 0} +} { + set rx_bridge gt_bridge_ip_0 + set asymmetric_mode [expr $rx_num_lanes != $tx_num_lanes] + set tx_bridge [expr {$asymmetric_mode == 0 ? "gt_bridge_ip_0" : "gt_bridge_ip_1"}] + + create_bd_pin -dir I ${ip_name}/gtreset_in + create_bd_pin -dir I ${ip_name}/gtreset_rx_pll_and_datapath + create_bd_pin -dir I ${ip_name}/gtreset_tx_pll_and_datapath + create_bd_pin -dir I ${ip_name}/gtreset_rx_datapath + create_bd_pin -dir I ${ip_name}/gtreset_tx_datapath + create_bd_pin -dir O ${ip_name}/gtpowergood + create_bd_pin -dir O ${ip_name}/rx_resetdone + create_bd_pin -dir O ${ip_name}/tx_resetdone + + # Sync resets to apb3clk + + create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_sync + ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_sync/out_clk + ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_sync/out_resetn + ad_connect ${ip_name}/gtreset_in ${ip_name}/gtreset_sync/in_bits + ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${rx_bridge}/gtreset_in + if {$asymmetric_mode} { + ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${tx_bridge}/gtreset_in + } + + foreach port {pll_and_datapath datapath} { + foreach rx_tx {rx tx} { + set bridge [expr {$rx_tx == "rx" ? $rx_bridge : $tx_bridge}] + create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_${rx_tx}_${port}_sync + ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_clk + ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_resetn + ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/gtreset_${rx_tx}_${port}_sync/in_bits + ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/${bridge}/reset_${rx_tx}_${port}_in + } + } + + set max_lanes [expr max($rx_num_lanes, $tx_num_lanes)] + set num_quads [expr int(ceil(1.0 * $max_lanes / 4))] + + ad_ip_instance xlconcat ${ip_name}/concat_powergood [list \ + NUM_PORTS $num_quads \ + ] + + ad_ip_instance util_reduced_logic ${ip_name}/and_powergood [list \ + C_SIZE $num_quads \ + ] + + for {set j 0} {$j < $num_quads} {incr j} { + ad_connect ${ip_name}/concat_powergood/In${j} ${ip_name}/gt_quad_base_${j}/gtpowergood + } + + ad_connect ${ip_name}/concat_powergood/dout ${ip_name}/and_powergood/Op1 + ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${rx_bridge}/gtpowergood + if {$asymmetric_mode} { + ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${tx_bridge}/gtpowergood + } + + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/${rx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset + } + if {$asymmetric_mode} { + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/${tx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset + } + } + ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone [list \ + NUM_PORTS ${rx_num_lanes} \ + ] + ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone [list \ + C_SIZE ${rx_num_lanes} \ + ] + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/xlconcat_iloresetdone/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone + } + ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/and_iloresetdone/Op1 + ad_connect ${ip_name}/and_iloresetdone/Res ${ip_name}/${rx_bridge}/ilo_resetdone + if {$asymmetric_mode} { + ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone_tx [list \ + NUM_PORTS ${tx_num_lanes} \ + ] + ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone_tx [list \ + C_SIZE ${tx_num_lanes} \ + ] + for {set j 0} {$j < ${tx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/xlconcat_iloresetdone_tx/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone + } + ad_connect ${ip_name}/xlconcat_iloresetdone_tx/dout ${ip_name}/and_iloresetdone_tx/Op1 + ad_connect ${ip_name}/and_iloresetdone_tx/Res ${ip_name}/${tx_bridge}/ilo_resetdone + } + + for {set j 0} {$j < ${num_quads}} {incr j} { + ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk0_lcpllreset + ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk1_lcpllreset + } + + set num_cplllocks [expr 2 * ${num_quads}] + ad_ip_instance xlconcat ${ip_name}/concat_cplllock [list \ + NUM_PORTS ${num_cplllocks} \ + ] + ad_ip_instance util_reduced_logic ${ip_name}/and_cplllock [list \ + C_SIZE ${num_cplllocks} \ + ] + + for {set j 0} {$j < ${num_quads}} {incr j} { + set in_index_0 [expr $j * 2 + 0] + set in_index_1 [expr $j * 2 + 1] + ad_connect ${ip_name}/concat_cplllock/In${in_index_0} ${ip_name}/gt_quad_base_${j}/hsclk0_lcplllock + ad_connect ${ip_name}/concat_cplllock/In${in_index_1} ${ip_name}/gt_quad_base_${j}/hsclk1_lcplllock + } + + ad_connect ${ip_name}/concat_cplllock/dout ${ip_name}/and_cplllock/Op1 + ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${rx_bridge}/gt_lcpll_lock + if {$asymmetric_mode} { + ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${tx_bridge}/gt_lcpll_lock + } + + ad_ip_instance xlconcat ${ip_name}/concat_phystatus [list \ + NUM_PORTS ${rx_num_lanes} \ + ] + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + + ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus/In${j} + } + ad_connect ${ip_name}/concat_phystatus/dout ${ip_name}/${rx_bridge}/ch_phystatus_in + if {$asymmetric_mode} { + ad_ip_instance xlconcat ${ip_name}/concat_phystatus_tx [list \ + NUM_PORTS ${rx_num_lanes} \ + ] + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + + ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus_tx/In${j} + } + ad_connect ${ip_name}/concat_phystatus_tx/dout ${ip_name}/${tx_bridge}/ch_phystatus_in + } + + # Outputs + ad_connect ${ip_name}/and_powergood/Res ${ip_name}/gtpowergood + ad_connect ${ip_name}/${rx_bridge}/rx_resetdone_out ${ip_name}/rx_resetdone + ad_connect ${ip_name}/${tx_bridge}/tx_resetdone_out ${ip_name}/tx_resetdone +} + +# Parameter description: +# ip_name : The name of the created ip +# jesd_mode : Used physical layer encoder mode +# rx_num_lanes : Number of RX lanes +# tx_num_lanes : Number of TX lanes +# ref_clock : Frequency of reference clock in MHz used in 64B66B mode (LANE_RATE/66) or 8B10B mode (LANE_RATE/40) +# rx_lane_rate : Line rate of the Rx link ( e.g. MxFE to FPGA ) in GHz +# tx_lane_rate : Line rate of the Tx link ( e.g. FPGA to MxFE ) in GHz +# intf_cfg : Direction of the transceivers +# RXTX : Duplex mode +# RX : Rx link only +# TX : Tx link only +proc create_versal_phy { + {ip_name versal_phy} + {jesd_mode 64B66B} + {rx_num_lanes 4} + {tx_num_lanes 4} + {rx_lane_rate 24.75} + {tx_lane_rate 24.75} + {ref_clock 375} + {transceiver GTY} + {intf_cfg RXTX} +} { + + set clk_divider [expr { $jesd_mode == "64B66B" ? 66 : 40} ] + set datapath_width [expr { $jesd_mode == "64B66B" ? 64 : 32} ] + set internal_datapath_width [expr { $jesd_mode == "64B66B" ? 64 : 40} ] + set data_encoding [expr { $jesd_mode == "64B66B" ? "64B66B_ASYNC" : "8B10B"} ] + set link_mode [expr { $jesd_mode == "64B66B" ? 2 : 1} ] + set comma_mask [expr { $jesd_mode == "64B66B" ? "0000000000" : "1111111111"} ] + set comma_p_enable [expr { $jesd_mode == "64B66B" ? false : false} ] + set comma_m_enable [expr { $jesd_mode == "64B66B" ? false : false} ] + set num_quads [expr int(ceil(1.0 * max($rx_num_lanes, $tx_num_lanes) / 4))] + set asymmetric_mode [expr { [expr $rx_num_lanes != $tx_num_lanes] ? true : false } ] + # When asymmetric_mode is true it means that the number of lanes on the Rx side is different from the number of lanes on the Tx side + # The 'gt_bridge_ip' can only be configured with the same number of lanes so we need to instantiate two ips, one for the Rx and one for the Tx + # Both 'gt_bridge_ip' will still share the same quad + + set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / ${clk_divider}]] + set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / ${clk_divider}]] + + if {$intf_cfg == "RX"} { + set gt_direction "SIMPLEX_RX" + set no_lanes_property "CONFIG.IP_NO_OF_RX_LANES" + } elseif {$intf_cfg == "TX"} { + set gt_direction "SIMPLEX_TX" + set no_lanes_property "CONFIG.IP_NO_OF_TX_LANES" + } else { + set gt_direction "DUPLEX" + set no_lanes_property "CONFIG.IP_NO_OF_LANES" + } + + create_bd_cell -type hier ${ip_name} + + # Common interface + create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk + create_bd_pin -dir I ${ip_name}/s_axi_clk + create_bd_pin -dir I ${ip_name}/s_axi_resetn + if {$intf_cfg != "TX"} { + create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk + create_bd_pin -dir I ${ip_name}/en_char_align + } + if {$intf_cfg != "RX"} { + create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk + } + + ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0 + set rx_bridge gt_bridge_ip_0 + set tx_bridge gt_bridge_ip_0 + if {$asymmetric_mode} { + ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_1 + set tx_bridge gt_bridge_ip_1 + } + if {!$asymmetric_mode} { + set num_lanes [expr max($rx_num_lanes, $tx_num_lanes)] + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.IP_PRESET ${transceiver}-JESD204_${jesd_mode} \ + CONFIG.IP_GT_DIRECTION ${gt_direction} \ + ${no_lanes_property} ${num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET ${transceiver}-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE ${transceiver} \ + GT_DIRECTION $gt_direction \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${rx_bridge}] + } else { + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.IP_PRESET ${transceiver}-JESD204_${jesd_mode} \ + CONFIG.IP_GT_DIRECTION {SIMPLEX_RX} \ + CONFIG.IP_NO_OF_RX_LANES ${rx_num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET ${transceiver}-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE ${transceiver} \ + GT_DIRECTION SIMPLEX_RX \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${rx_bridge}] + + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.IP_PRESET ${transceiver}-JESD204_${jesd_mode} \ + CONFIG.IP_GT_DIRECTION {SIMPLEX_TX} \ + CONFIG.IP_NO_OF_TX_LANES ${tx_num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET ${transceiver}-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE ${transceiver} \ + GT_DIRECTION SIMPLEX_TX \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${tx_bridge}] + } + + for {set j 0} {$j < $num_quads} {incr j} { + ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_${j} + set_property -dict [list \ + CONFIG.REG_CONF_INTF.VALUE_MODE {MANUAL} \ + CONFIG.REG_CONF_INTF {AXI_LITE} \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + if {!$asymmetric_mode} { + set_property -dict [list \ + CONFIG.REG_CONF_INTF.VALUE_MODE {MANUAL} \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + } else { + # When we have multiple protocols (different number of lanes on Rx and Tx) we have to manually set the protocols to pass design validation + set_property -dict [list \ + CONFIG.PROT1_LR0_SETTINGS.VALUE_MODE MANUAL \ + CONFIG.GT_TYPE.VALUE_MODE AUTO \ + CONFIG.PROT0_RX_MASTERCLK_SRC.VALUE_MODE MANUAL \ + CONFIG.PROT1_TX_MASTERCLK_SRC.VALUE_MODE MANUAL \ + CONFIG.PROT0_TX_MASTERCLK_SRC.VALUE_MODE MANUAL \ + CONFIG.PROT1_PRESET.VALUE_MODE MANUAL \ + CONFIG.PROT1_ENABLE.VALUE_MODE MANUAL \ + CONFIG.PROT0_PRESET.VALUE_MODE MANUAL \ + CONFIG.PROT0_GT_DIRECTION.VALUE_MODE MANUAL \ + CONFIG.TX0_LANE_SEL.VALUE_MODE AUTO \ + CONFIG.PROT0_NO_OF_LANES.VALUE_MODE MANUAL \ + CONFIG.PROT0_NO_OF_RX_LANES.VALUE_MODE MANUAL \ + CONFIG.PROT1_NO_OF_TX_LANES.VALUE_MODE MANUAL \ + CONFIG.PROT1_GT_DIRECTION.VALUE_MODE MANUAL \ + CONFIG.PROT0_LR0_SETTINGS.VALUE_MODE MANUAL \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + + set_property -dict [list \ + CONFIG.PROT0_GT_DIRECTION {SIMPLEX_RX} \ + CONFIG.PROT0_LR0_SETTINGS [list \ + PRESET ${transceiver}-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE ${transceiver} \ + GT_DIRECTION {SIMPLEX_RX} \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + CONFIG.PROT0_NO_OF_RX_LANES $rx_num_lanes \ + CONFIG.PROT0_PRESET ${transceiver}-JESD204_${jesd_mode} \ + CONFIG.PROT1_ENABLE {true} \ + CONFIG.PROT1_GT_DIRECTION {SIMPLEX_TX} \ + CONFIG.PROT1_LR0_SETTINGS [list \ + PRESET ${transceiver}-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE ${transceiver} \ + GT_DIRECTION {SIMPLEX_TX} \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + CONFIG.PROT1_NO_OF_TX_LANES $tx_num_lanes \ + CONFIG.PROT1_PRESET ${transceiver}-JESD204_${jesd_mode} \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + + for {set i 0} {$i < 4} {incr i} { + set_property -dict [list \ + CONFIG.TX${i}_LANE_SEL.VALUE_MODE MANUAL \ + CONFIG.RX${i}_LANE_SEL.VALUE_MODE MANUAL \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + } + } + + if {$intf_cfg != "TX"} { + # Share the link clock generated by the first quad + if {$j == 0} { + ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx + ad_connect ${ip_name}/gt_quad_base_0/ch0_rxoutclk ${ip_name}/bufg_gt_rx/outclk + ad_connect ${ip_name}/${rx_bridge}/rx_clr_out ${ip_name}/bufg_gt_rx/gt_bufgtclr + ad_connect ${ip_name}/${rx_bridge}/rxusrclk_out ${ip_name}/rxusrclk_out + ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/${rx_bridge}/gt_rxusrclk + } + create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_p + create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_n + ad_connect ${ip_name}/gt_quad_base_${j}/rxp ${ip_name}/rx_${j}_p + ad_connect ${ip_name}/gt_quad_base_${j}/rxn ${ip_name}/rx_${j}_n + } + if {$intf_cfg != "RX"} { + # Share the link clock generated by the first quad + if {$j == 0} { + ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx + ad_connect ${ip_name}/gt_quad_base_0/ch0_txoutclk ${ip_name}/bufg_gt_tx/outclk + ad_connect ${ip_name}/${tx_bridge}/tx_clr_out ${ip_name}/bufg_gt_tx/gt_bufgtclr + ad_connect ${ip_name}/${tx_bridge}/txusrclk_out ${ip_name}/txusrclk_out + ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/${tx_bridge}/gt_txusrclk + } + create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_p + create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_n + ad_connect ${ip_name}/gt_quad_base_${j}/txp ${ip_name}/tx_${j}_p + ad_connect ${ip_name}/gt_quad_base_${j}/txn ${ip_name}/tx_${j}_n + } + } + + if {$intf_cfg != "TX"} { + for {set j 0} {$j < $rx_num_lanes} {incr j} { + set quad_index [expr int($j / 4)] + set rx_index [expr $j % 4] + + ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_quad_base_${quad_index}/ch${rx_index}_rxusrclk + + ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} [list \ + LINK_MODE $link_mode \ + ] + ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/${rx_bridge}/GT_RX${j}_EXT + ad_connect ${ip_name}/${rx_bridge}/GT_RX${j} ${ip_name}/gt_quad_base_${quad_index}/RX${rx_index}_GT_IP_Interface + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j} + ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX + ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_rx/usrclk + ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align + + set_property CONFIG.RX${rx_index}_LANE_SEL {PROT0} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + } + if {$intf_cfg != "RX"} { + for {set j 0} {$j < $tx_num_lanes} {incr j} { + set quad_index [expr int($j / 4)] + set tx_index [expr $j % 4] + + ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_quad_base_${quad_index}/ch${tx_index}_txusrclk + + ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} [list \ + LINK_MODE $link_mode \ + ] + ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/${tx_bridge}/GT_TX${j}_EXT + ad_connect ${ip_name}/${tx_bridge}/GT_TX${j} ${ip_name}/gt_quad_base_${quad_index}/TX${tx_index}_GT_IP_Interface + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j} + ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX + ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_tx/usrclk + + if {!$asymmetric_mode} { + set_property CONFIG.TX${tx_index}_LANE_SEL {PROT0} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } else { + set_property CONFIG.TX${tx_index}_LANE_SEL {PROT1} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + } + } + + # Map unused quad lanes as unconnected + set max_num_of_lanes [expr $num_quads * 4] + for {set j $rx_num_lanes} {$j < $max_num_of_lanes} {incr j} { + set quad_index [expr $j / 4] + set lane_index [expr $j % 4] + set_property CONFIG.RX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + for {set j $tx_num_lanes} {$j < $max_num_of_lanes} {incr j} { + set quad_index [expr $j / 4] + set lane_index [expr $j % 4] + set_property CONFIG.TX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + + # Clocks + ad_connect ${ip_name}/s_axi_clk ${ip_name}/${rx_bridge}/apb3clk + if {$asymmetric_mode} { + ad_connect ${ip_name}/s_axi_clk ${ip_name}/${tx_bridge}/apb3clk + } + for {set j 0} {$j < $num_quads} {incr j} { + ad_connect ${ip_name}/GT_REFCLK ${ip_name}/gt_quad_base_${j}/GT_REFCLK0 + ad_connect ${ip_name}/s_axi_clk ${ip_name}/gt_quad_base_${j}/s_axi_lite_clk + ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gt_quad_base_${j}/s_axi_lite_resetn + } + + # Instantiate reset helper logic + create_reset_logic $ip_name $rx_num_lanes $tx_num_lanes +} diff --git a/projects/ad9084_ebz/fm87/Makefile b/projects/ad9084_ebz/fm87/Makefile new file mode 100755 index 00000000000..39053d8cdff --- /dev/null +++ b/projects/ad9084_ebz/fm87/Makefile @@ -0,0 +1,32 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9084_ebz_fm87 + +M_DEPS += ../common/ad9084_ebz_spi.v +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/intel/adcfifo_qsys.tcl +M_DEPS += ../../common/fm87/system_qsys.tcl +M_DEPS += ../../common/fm87/gpio_slave.v +M_DEPS += ../../common/fm87/fm87_system_qsys.tcl +M_DEPS += ../../common/fm87/fm87_system_assign.tcl +M_DEPS += ../../common/fm87/fm87_plddr_system_assign.tcl +M_DEPS += ../../common/fm87/fm87_plddr_dacfifo_qsys.tcl +M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_qsys.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v + + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += intel/adi_jesd204 +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../../scripts/project-intel.mk diff --git a/projects/ad9084_ebz/fm87/system_constr.sdc b/projects/ad9084_ebz/fm87/system_constr.sdc new file mode 100644 index 00000000000..c7a6d4e0725 --- /dev/null +++ b/projects/ad9084_ebz/fm87/system_constr.sdc @@ -0,0 +1,18 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "6.0000 ns" -name sys_ddr_ref_clk [get_ports {sys_ddr_ref_clk_clk}] +create_clock -period "6.0000 ns" -name emif_ref_clk [get_ports {emif_hps_pll_ref_clk}] + +create_clock -period "3.2000 ns" -name ref_clk [get_ports {fpga_refclk_in}] +create_clock -period "3.2000 ns" -name device_clk [get_ports {device_clk}] + +derive_clock_uncertainty + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] + +set_false_path -to [get_registers {*|i_sync_input_ctrl|cdc_sync_stage*[0]}] +set_false_path -to [get_registers {*|i_sync_reset_ack|cdc_sync_stage*[0]}] diff --git a/projects/ad9084_ebz/fm87/system_project.tcl b/projects/ad9084_ebz/fm87/system_project.tcl new file mode 100644 index 00000000000..884eb5b2670 --- /dev/null +++ b/projects/ad9084_ebz/fm87/system_project.tcl @@ -0,0 +1,271 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../../projects/scripts/adi_project_intel.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make JESD_MODE=64B66B RX_LANE_RATE=10.3125 TX_LANE_RATE=10.3125 RX_JESD_M=4 TX_JESD_M=4 RX_JESD_L=8 TX_JESD_L=8 RX_JESD_S=1 TX_JESD_S=1 RX_JESD_NP=16 TX_JESD_NP=16 +# + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C +# 8B10B - 8b10b link layer defined in JESD 204B +# +# REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B +# DEVICE_CLK_RATE : Device clock frequency in MHz, usually the same as REF_CLK_RATE but it can vary based on the JESD configuration +# ENABLE_HSCI : If set, adds and enables the HSCI core in the design +# RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample +# [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 +# [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) +# ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link +# RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side +# TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side +# [RX/TX]_B_JESD_M : Number of converters per link for B side +# [RX/TX]_B_JESD_L : Number of lanes per link for B side +# [RX/TX]_B_JESD_NP : Number of bits per sample for B side +# [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side +# +# !!! Requires the following hdl branch: https://github.com/analogdevicesinc/hdl/tree/dev_fm87_avlfifo +# + +adi_project ad9084_ebz_fm87 [list \ + JESD_MODE [get_env_param JESD_MODE 64B66B ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 312.5 ] \ + DEVICE_CLK_RATE [get_env_param DEVICE_CLK_RATE 312.5 ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 20.625 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 20.625 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 8 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 2 ] \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 8 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 2 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 16 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 16 ] \ +] + +# source common_assign.tcl + +source $ad_hdl_dir/projects/common/fm87/fm87_system_assign.tcl +source $ad_hdl_dir/projects/common/fm87/fm87_plddr_system_assign.tcl + +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_3w_spi.v +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/projects/common/fm87/gpio_slave.v +set_global_assignment -name VERILOG_FILE ../common/ad9084_ebz_spi.v + +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to fpga_refclk_in +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to syncinb_a0 +set_instance_assignment -name IO_STANDARD "Differential 1.2-V HSTL" -to syncoutb_a0 +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to sysref_in +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to device_clk + +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to syncinb_a0 +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref_in + +set_location_assignment PIN_CN56 -to "fpga_refclk_in" ; ## D4 GBTCLK0_M2C_P +set_location_assignment PIN_CP57 -to "fpga_refclk_in(n)" ; ## D5 GBTCLK0_M2C_N + +set_location_assignment PIN_DD47 -to "device_clk" ; ## G2 C_FMC_B_CLK1_P +set_location_assignment PIN_DE48 -to "device_clk(n)" ; ## G3 C_FMC_B_CLK1_N + +# For some reason the F-tile IP reverses the order... +set_location_assignment PIN_BK63 -to tx_data_p[0] ; ## M22 FGTL12A_TX_Q3_CH3P FMC_B_TX_P_15 SRXA_11P_FMC +set_location_assignment PIN_BL62 -to tx_data_n[0] ; ## M23 FGTL12A_TX_Q3_CH3N FMC_B_TX_N_15 SRXA_11N_FMC +set_location_assignment PIN_BN60 -to tx_data_p[1] ; ## M18 FGTL12A_TX_Q3_CH2P FMC_B_TX_P_14 SRXA_9P_FMC +set_location_assignment PIN_BM59 -to tx_data_n[1] ; ## M19 FGTL12A_TX_Q3_CH2N FMC_B_TX_N_14 SRXA_9N_FMC +set_location_assignment PIN_BP63 -to tx_data_p[2] ; ## Y30 FGTL12A_TX_Q3_CH1P FMC_B_TX_P_13 SRXA_8P_FMC +set_location_assignment PIN_BR62 -to tx_data_n[2] ; ## Y31 FGTL12A_TX_Q3_CH1N FMC_B_TX_N_13 SRXA_8N_FMC +set_location_assignment PIN_BU60 -to tx_data_p[3] ; ## Z28 FGTL12A_TX_Q3_CH0P FMC_B_TX_P_12 SRXA_10P_FMC +set_location_assignment PIN_BT59 -to tx_data_n[3] ; ## Z29 FGTL12A_TX_Q3_CH0N FMC_B_TX_N_12 SRXA_10N_FMC +set_location_assignment PIN_BV63 -to tx_data_p[4] ; ## Y26 FGTL12A_TX_Q2_CH3P FMC_B_TX_P_11 SRXB_11P_FMC +set_location_assignment PIN_BW62 -to tx_data_n[4] ; ## Y27 FGTL12A_TX_Q2_CH3N FMC_B_TX_N_11 SRXB_11N_FMC +set_location_assignment PIN_CA60 -to tx_data_p[5] ; ## Z24 FGTL12A_TX_Q2_CH2P FMC_B_TX_P_10 SRXB_9P_FMC +set_location_assignment PIN_BY59 -to tx_data_n[5] ; ## Z25 FGTL12A_TX_Q2_CH2N FMC_B_TX_N_10 SRXB_9N_FMC +set_location_assignment PIN_CB63 -to tx_data_p[6] ; ## B24 FGTL12A_TX_Q2_CH1P FMC_B_TX_P_9 SRXB_8P_FMC +set_location_assignment PIN_CC62 -to tx_data_n[6] ; ## B25 FGTL12A_TX_Q2_CH1N FMC_B_TX_N_9 SRXB_8N_FMC +set_location_assignment PIN_CE60 -to tx_data_p[7] ; ## B28 FGTL12A_TX_Q2_CH0P FMC_B_TX_P_8 SRXB_5P_FMC +set_location_assignment PIN_CD59 -to tx_data_n[7] ; ## B29 FGTL12A_TX_Q2_CH0N FMC_B_TX_N_8 SRXB_5N_FMC +set_location_assignment PIN_CF63 -to tx_data_p[8] ; ## B32 FGTL12A_TX_Q1_CH3P FMC_B_TX_P_7 SRXA_7P_FMC +set_location_assignment PIN_CG62 -to tx_data_n[8] ; ## B33 FGTL12A_TX_Q1_CH3N FMC_B_TX_N_7 SRXA_7N_FMC +set_location_assignment PIN_CJ60 -to tx_data_p[9] ; ## B36 FGTL12A_TX_Q1_CH2P FMC_B_TX_P_6 SRXA_3P_FMC +set_location_assignment PIN_CH59 -to tx_data_n[9] ; ## B37 FGTL12A_TX_Q1_CH2N FMC_B_TX_N_6 SRXA_3N_FMC +set_location_assignment PIN_CK63 -to tx_data_p[10] ; ## A38 FGTL12A_TX_Q1_CH1P FMC_B_TX_P_5 SRXA_1P_FMC +set_location_assignment PIN_CL62 -to tx_data_n[10] ; ## A39 FGTL12A_TX_Q1_CH1N FMC_B_TX_N_5 SRXA_1N_FMC +set_location_assignment PIN_CN60 -to tx_data_p[11] ; ## A34 FGTL12A_TX_Q1_CH0P FMC_B_TX_P_4 SRXA_5P_FMC +set_location_assignment PIN_CM59 -to tx_data_n[11] ; ## A35 FGTL12A_TX_Q1_CH0N FMC_B_TX_N_4 SRXA_5N_FMC +set_location_assignment PIN_CP63 -to tx_data_p[12] ; ## A30 FGTL12A_TX_Q0_CH3P FMC_B_TX_P_3 SRXB_3P_FMC +set_location_assignment PIN_CR62 -to tx_data_n[12] ; ## A31 FGTL12A_TX_Q0_CH3N FMC_B_TX_N_3 SRXB_3N_FMC +set_location_assignment PIN_CU60 -to tx_data_p[13] ; ## A26 FGTL12A_TX_Q0_CH2P FMC_B_TX_P_2 SRXB_10P_FMC +set_location_assignment PIN_CT59 -to tx_data_n[13] ; ## A27 FGTL12A_TX_Q0_CH2N FMC_B_TX_N_2 SRXB_10N_FMC +set_location_assignment PIN_CV63 -to tx_data_p[14] ; ## A22 FGTL12A_TX_Q0_CH1P FMC_B_TX_P_1 SRXB_7P_FMC +set_location_assignment PIN_CW62 -to tx_data_n[14] ; ## A23 FGTL12A_TX_Q0_CH1N FMC_B_TX_N_1 SRXB_7N_FMC +set_location_assignment PIN_DA60 -to tx_data_p[15] ; ## C2 FGTL12A_TX_Q0_CH0P FMC_B_TX_P_0 SRXB_1P_FMC +set_location_assignment PIN_CY59 -to tx_data_n[15] ; ## C3 FGTL12A_TX_Q0_CH0N FMC_B_TX_N_0 SRXB_1N_FMC + +set_location_assignment PIN_BK69 -to rx_data_p[0] ; ## Y22 FGTL12A_RX_Q3_CH3P FMC_B_RX_P_15 STXA_2P_FMC +set_location_assignment PIN_BL68 -to rx_data_n[0] ; ## Y23 FGTL12A_RX_Q3_CH3N FMC_B_RX_N_15 STXA_2N_FMC +set_location_assignment PIN_BN66 -to rx_data_p[1] ; ## Y18 FGTL12A_RX_Q3_CH2P FMC_B_RX_P_14 STXA_1P_FMC +set_location_assignment PIN_BM65 -to rx_data_n[1] ; ## Y19 FGTL12A_RX_Q3_CH2N FMC_B_RX_N_14 STXA_1N_FMC +set_location_assignment PIN_BP69 -to rx_data_p[2] ; ## Z16 FGTL12A_RX_Q3_CH1P FMC_B_RX_P_13 STXA_5P_FMC +set_location_assignment PIN_BR68 -to rx_data_n[2] ; ## Z17 FGTL12A_RX_Q3_CH1N FMC_B_RX_N_13 STXA_5N_FMC +set_location_assignment PIN_BU66 -to rx_data_p[3] ; ## Y14 FGTL12A_RX_Q3_CH0P FMC_B_RX_P_12 STXA_7P_FMC +set_location_assignment PIN_BT65 -to rx_data_n[3] ; ## Y15 FGTL12A_RX_Q3_CH0N FMC_B_RX_N_12 STXA_7N_FMC +set_location_assignment PIN_BV69 -to rx_data_p[4] ; ## Z12 FGTL12A_RX_Q2_CH3P FMC_B_RX_P_11 STXB_9P_FMC +set_location_assignment PIN_BW68 -to rx_data_n[4] ; ## Z13 FGTL12A_RX_Q2_CH3N FMC_B_RX_N_11 STXB_9N_FMC +set_location_assignment PIN_CA66 -to rx_data_p[5] ; ## Y10 FGTL12A_RX_Q2_CH2P FMC_B_RX_P_10 STXB_11P_FMC +set_location_assignment PIN_BY65 -to rx_data_n[5] ; ## Y11 FGTL12A_RX_Q2_CH2N FMC_B_RX_N_10 STXB_11N_FMC +set_location_assignment PIN_CB69 -to rx_data_p[6] ; ## B4 FGTL12A_RX_Q2_CH1P FMC_B_RX_P_9 STXB_1P_FMC +set_location_assignment PIN_CC68 -to rx_data_n[6] ; ## B5 FGTL12A_RX_Q2_CH1N FMC_B_RX_N_9 STXB_1N_FMC +set_location_assignment PIN_CE66 -to rx_data_p[7] ; ## B8 FGTL12A_RX_Q2_CH0P FMC_B_RX_P_8 STXB_8P_FMC +set_location_assignment PIN_CD65 -to rx_data_n[7] ; ## B9 FGTL12A_RX_Q2_CH0N FMC_B_RX_N_8 STXB_8N_FMC +set_location_assignment PIN_CF69 -to rx_data_p[8] ; ## B12 FGTL12A_RX_Q1_CH3P FMC_B_RX_P_7 STXA_9P_FMC +set_location_assignment PIN_CG68 -to rx_data_n[8] ; ## B13 FGTL12A_RX_Q1_CH3N FMC_B_RX_N_7 STXA_9N_FMC +set_location_assignment PIN_CJ66 -to rx_data_p[9] ; ## B16 FGTL12A_RX_Q1_CH2P FMC_B_RX_P_6 STXA_8P_FMC +set_location_assignment PIN_CH65 -to rx_data_n[9] ; ## B17 FGTL12A_RX_Q1_CH2N FMC_B_RX_N_6 STXA_8N_FMC +set_location_assignment PIN_CK69 -to rx_data_p[10] ; ## A18 FGTL12A_RX_Q1_CH1P FMC_B_RX_P_5 STXA_3P_FMC +set_location_assignment PIN_CL68 -to rx_data_n[10] ; ## A19 FGTL12A_RX_Q1_CH1N FMC_B_RX_N_5 STXA_3N_FMC +set_location_assignment PIN_CN66 -to rx_data_p[11] ; ## A14 FGTL12A_RX_Q1_CH0P FMC_B_RX_P_4 STXA_11P_FMC +set_location_assignment PIN_CM65 -to rx_data_n[11] ; ## A15 FGTL12A_RX_Q1_CH0N FMC_B_RX_N_4 STXA_11N_FMC +set_location_assignment PIN_CP69 -to rx_data_p[12] ; ## A10 FGTL12A_RX_Q0_CH3P FMC_B_RX_P_3 STXB_7P_FMC +set_location_assignment PIN_CR68 -to rx_data_n[12] ; ## A11 FGTL12A_RX_Q0_CH3N FMC_B_RX_N_3 STXB_7N_FMC +set_location_assignment PIN_CU66 -to rx_data_p[13] ; ## A6 FGTL12A_RX_Q0_CH2P FMC_B_RX_P_2 STXB_5P_FMC +set_location_assignment PIN_CT65 -to rx_data_n[13] ; ## A7 FGTL12A_RX_Q0_CH2N FMC_B_RX_N_2 STXB_5N_FMC +set_location_assignment PIN_CV69 -to rx_data_p[14] ; ## A2 FGTL12A_RX_Q0_CH1P FMC_B_RX_P_1 STXB_2P_FMC +set_location_assignment PIN_CW68 -to rx_data_n[14] ; ## A3 FGTL12A_RX_Q0_CH1N FMC_B_RX_N_1 STXB_2N_FMC +set_location_assignment PIN_DA66 -to rx_data_p[15] ; ## C6 FGTL12A_RX_Q0_CH0P FMC_B_RX_P_0 STXB_3P_FMC +set_location_assignment PIN_CY65 -to rx_data_n[15] ; ## C7 FGTL12A_RX_Q0_CH0N FMC_B_RX_N_0 STXB_3N_FMC + +set_location_assignment PIN_DB37 -to "gpio[15]" ; ## C10 FMC_B_LA_P6 +set_location_assignment PIN_DA38 -to "gpio[16]" ; ## C11 FMC_B_LA_N6 +set_location_assignment PIN_DM45 -to "gpio[23]" ; ## C18 FMC_B_LA_P14 +set_location_assignment PIN_DL46 -to "gpio[24]" ; ## C19 FMC_B_LA_N14 +set_location_assignment PIN_CL42 -to "gpio[27]" ; ## C22 FMC_B_LA_P18 +set_location_assignment PIN_CM41 -to "gpio[28]" ; ## C23 FMC_B_LA_N18 +set_location_assignment PIN_DF37 -to "gpio[21]" ; ## G15 FMC_B_LA_P12 +set_location_assignment PIN_DG38 -to "gpio[22]" ; ## G16 FMC_B_LA_N12 +set_location_assignment PIN_DK37 -to "gpio[17]" ; ## H13 FMC_B_LA_P7 +set_location_assignment PIN_DJ38 -to "gpio[18]" ; ## H14 FMC_B_LA_N7 +set_location_assignment PIN_DF39 -to "gpio[19]" ; ## H16 FMC_B_LA_P11 +set_location_assignment PIN_DG40 -to "gpio[20]" ; ## H17 FMC_B_LA_N11 +set_location_assignment PIN_DB39 -to "gpio[25]" ; ## H19 FMC_B_LA_P15 +set_location_assignment PIN_DA40 -to "gpio[26]" ; ## H20 FMC_B_LA_N15 +set_location_assignment PIN_CT43 -to "gpio[29]" ; ## H22 FMC_B_LA_P19 +set_location_assignment PIN_CU44 -to "gpio[30]" ; ## H23 FMC_B_LA_N19 +set_location_assignment PIN_DL42 -to "aux_gpio" ; ## D24 FMC_B_LA_N23 + +set_location_assignment PIN_DB41 -to "syncinb_a1_p_gpio" ; ## G21 FMC_B_LA_P20 +set_location_assignment PIN_DA42 -to "syncinb_a1_n_gpio" ; ## G22 FMC_B_LA_N20 +set_location_assignment PIN_DD41 -to "syncoutb_a1_p_gpio" ; ## H25 FMC_B_LA_P21 +set_location_assignment PIN_DE42 -to "syncoutb_a1_n_gpio" ; ## H26 FMC_B_LA_N21 + +set_location_assignment PIN_DD39 -to "syncinb_a0" ; ## H10 FMC_B_LA_P4 +set_location_assignment PIN_DE40 -to "syncinb_a0(n)" ; ## H11 FMC_B_LA_N4 +set_location_assignment PIN_DF41 -to "syncoutb_a0" ; ## D11 FMC_B_LA_P5 +set_location_assignment PIN_DG42 -to "syncoutb_a0(n)" ; ## D12 FMC_B_LA_N5 + +set_location_assignment PIN_CW42 -to "sysref_in" ; ## G36 FMC_B_LA_P33 +set_location_assignment PIN_CY41 -to "sysref_in(n)" ; ## G37 FMC_B_LA_N33 + +set_location_assignment PIN_DB45 -to "spi2_sclk" ; ## H28 FMC_B_LA_P24 +set_location_assignment PIN_DA46 -to "spi2_sdio" ; ## H29 FMC_B_LA_N24 +set_location_assignment PIN_DD43 -to "spi2_sdo" ; ## D26 FMC_B_LA_P26 +set_location_assignment PIN_DE44 -to "spi2_cs[0]" ; ## D27 FMC_B_LA_N26 +set_location_assignment PIN_CW46 -to "spi2_cs[1]" ; ## G30 FMC_B_LA_P29 +set_location_assignment PIN_CY45 -to "spi2_cs[2]" ; ## G31 FMC_B_LA_N29 +set_location_assignment PIN_CL46 -to "spi2_cs[3]" ; ## H34 FMC_B_LA_P30 +set_location_assignment PIN_CM45 -to "spi2_cs[4]" ; ## H35 FMC_B_LA_N30 +set_location_assignment PIN_DB43 -to "spi2_cs[5]" ; ## H37 FMC_B_LA_P32 + +set_location_assignment PIN_DB47 -to "dut_sdio" ; ## G9 FMC_B_LA_P3 +set_location_assignment PIN_DA48 -to "dut_sdo" ; ## G10 FMC_B_LA_N3 +set_location_assignment PIN_DD37 -to "dut_sclk" ; ## H7 FMC_B_LA_P2 +set_location_assignment PIN_DE38 -to "dut_csb" ; ## H8 FMC_B_LA_N2 + +set_location_assignment PIN_DM43 -to "trig_a[0]" ; ## C14 FMC_B_LA_P10 +set_location_assignment PIN_DL44 -to "trig_a[1]" ; ## C15 FMC_B_LA_N10 +set_location_assignment PIN_DP41 -to "trig_b[0]" ; ## D17 FMC_B_LA_P13 +set_location_assignment PIN_DR42 -to "trig_b[1]" ; ## D18 FMC_B_LA_N13 +set_location_assignment PIN_CU46 -to "trig_in" ; ## D9 FMC_B_LA_N1 +set_location_assignment PIN_CT45 -to "resetb" ; ## D8 FMC_B_LA_P1 + +# Merge RX and TX into single transceiver +for {set i 0} {$i < 16} {incr i} { + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_data_p[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_data_p[${i}] +} + +# Apply default main-tap and pre-tap values +set tx_num_lanes [expr [get_env_param TX_JESD_L 8] * [get_env_param TX_NUM_LINKS 2]] +for {set j 0} {$j < $tx_num_lanes} {incr j} { + set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to tx_data_p[$j] + set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to tx_data_n[$j] + + set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=35" -to tx_data_p[$j] + set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to tx_data_p[$j] + set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to tx_data_p[$j] + set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to tx_data_p[$j] + set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=35" -to tx_data_n[$j] + set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to tx_data_n[$j] + set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to tx_data_n[$j] + set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to tx_data_n[$j] +} + +# Enable AC coupling, set termination to 100 ohms and enable VSR mode at high lane rates +set rx_num_lanes [expr [get_env_param RX_JESD_L 8] * [get_env_param RX_NUM_LINKS 2]] +set lane_rate [expr [get_env_param RX_LANE_RATE 20.625] * 1000] +for {set j 0} {$j < $rx_num_lanes} {incr j} { + set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to rx_data_p[$j] + set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to rx_data_n[$j] + + set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to rx_data_p[$j] + set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to rx_data_p[$j] + set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to rx_data_n[$j] + set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to rx_data_n[$j] + + if {$lane_rate > 23000} { + set_instance_assignment -name HSSI_PARAMETER "vsr_mode=VSR_MODE_LOW_LOSS" -to rx_data_p[$j] + set_instance_assignment -name HSSI_PARAMETER "vsr_mode=VSR_MODE_LOW_LOSS" -to rx_data_n[$j] + } else { + set_instance_assignment -name HSSI_PARAMETER "vsr_mode=VSR_MODE_DISABLE" -to rx_data_p[$j] + set_instance_assignment -name HSSI_PARAMETER "vsr_mode=VSR_MODE_DISABLE" -to rx_data_n[$j] + } +} + +for {set i 15} {$i < 31} {incr i} { + set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[$i] +} + +foreach port {aux_gpio trig_a[0] trig_a[1] trig_b[0] trig_b[1] trig_in resetb} { + set_instance_assignment -name IO_STANDARD "1.2V" -to $port +} + +foreach port {spi2_sclk spi2_sdio spi2_sdo spi2_cs[0] spi2_cs[1] spi2_cs[2] spi2_cs[3] spi2_cs[4] spi2_cs[5] dut_sdio dut_sdo dut_sclk dut_csb} { + set_instance_assignment -name IO_STANDARD "1.2V" -to $port +} + +foreach port {syncinb_a1_p_gpio syncinb_a1_n_gpio syncoutb_a1_p_gpio syncoutb_a1_n_gpio} { + set_instance_assignment -name IO_STANDARD "1.2V" -to $port +} + +set_global_assignment -name OPTIMIZATION_MODE "Superior Performance" + +execute_flow -compile diff --git a/projects/ad9084_ebz/fm87/system_qsys.tcl b/projects/ad9084_ebz/fm87/system_qsys.tcl new file mode 100644 index 00000000000..4db028c6d71 --- /dev/null +++ b/projects/ad9084_ebz/fm87/system_qsys.tcl @@ -0,0 +1,66 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/fm87/system_qsys.tcl +source $ad_hdl_dir/projects/common/fm87/fm87_plddr_dacfifo_qsys.tcl +source $ad_hdl_dir/projects/common/intel/adcfifo_qsys.tcl + +set jesd_mode $ad_project_params(JESD_MODE) + +set jesd204_ref_clock [format {%.6f} $ad_project_params(REF_CLK_RATE)] +if {$jesd_mode == "64B66B"} { + set syspll_freq [format {%.6f} [expr $ad_project_params(RX_LANE_RATE)*1000 / 32]] +} else { + set syspll_freq [format {%.6f} [expr $ad_project_params(RX_LANE_RATE)*1000 / 20]] +} +# DUT F-Tile Ref clock +add_instance systemclk systemclk_f +set_instance_parameter_value systemclk syspll_mod_0 {User Configuration} +set_instance_parameter_value systemclk syspll_refclk_src_0 {RefClk #2} +set_instance_parameter_value systemclk syspll_freq_mhz_0 $syspll_freq +set_instance_parameter_value systemclk refclk_fgt_output_enable_2 1 +set_instance_parameter_value systemclk refclk_fgt_freq_mhz_2 $jesd204_ref_clock + +add_interface ref_clk_fgt_2 clock sink +set_interface_property ref_clk_fgt_2 EXPORT_OF systemclk.out_refclk_fgt_2 + +add_interface ref_clk_in clock sink +set_interface_property ref_clk_in EXPORT_OF systemclk.refclk_fgt + +set HSCI_ENABLE 0 +set ASYMMETRIC_A_B_MODE 0 +source $ad_hdl_dir/projects/ad9084_ebz/common/ad9084_ebz_qsys.tcl + +# Apollo spi +add_instance apollo_spi altera_avalon_spi +set_instance_parameter_value apollo_spi {clockPhase} {0} +set_instance_parameter_value apollo_spi {clockPolarity} {0} +set_instance_parameter_value apollo_spi {dataWidth} {8} +set_instance_parameter_value apollo_spi {masterSPI} {1} +set_instance_parameter_value apollo_spi {numberOfSlaves} {8} +set_instance_parameter_value apollo_spi {targetClockRate} {10000000.0} + +add_connection sys_clk.clk_reset apollo_spi.reset +add_connection sys_clk.clk apollo_spi.clk +add_interface apollo_spi conduit end +set_interface_property apollo_spi EXPORT_OF apollo_spi.external + +ad_cpu_interconnect 0x000EA000 apollo_spi.spi_control_port + +ad_cpu_interrupt 18 apollo_spi.irq + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +sysid_gen_sys_init_file; \ No newline at end of file diff --git a/projects/ad9084_ebz/fm87/system_top.v b/projects/ad9084_ebz/fm87/system_top.v new file mode 100644 index 00000000000..0baed7d092c --- /dev/null +++ b/projects/ad9084_ebz/fm87/system_top.v @@ -0,0 +1,427 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter JESD_MODE = "8B10B", + parameter HSCI_ENABLE = 0, + parameter REF_CLK_RATE = 312.5, + parameter DEVICE_CLK_RATE = 312.5, + parameter RX_LANE_RATE = 10, + parameter TX_LANE_RATE = 10, + parameter RX_JESD_M = 4, + parameter RX_JESD_L = 8, + parameter RX_JESD_S = 1, + parameter RX_JESD_NP = 16, + parameter RX_NUM_LINKS = 1, + parameter TX_JESD_M = 4, + parameter TX_JESD_L = 8, + parameter TX_JESD_S = 1, + parameter TX_JESD_NP = 16, + parameter TX_NUM_LINKS = 1, + parameter RX_KS_PER_CHANNEL = 32, + parameter TX_KS_PER_CHANNEL = 32, + + parameter RX_NO_LANES = RX_JESD_L * RX_NUM_LINKS, + parameter TX_NO_LANES = TX_JESD_L * TX_NUM_LINKS +) ( + // clock and resets + input sys_clk, + input hps_io_ref_clk, + input sys_resetn, + + // board gpio + input [12:0] fpga_gpio, + input fpga_sgpio_sync, + input fpga_sgpio_clk, + input fpga_sgpi, + output fpga_sgpo, + + // hps-emif + input emif_hps_pll_ref_clk, + output emif_hps_mem_clk_p, + output emif_hps_mem_clk_n, + output [16:0] emif_hps_mem_a, + output [ 1:0] emif_hps_mem_ba, + output emif_hps_mem_bg, + output emif_hps_mem_cke, + output emif_hps_mem_cs_n, + output emif_hps_mem_odt, + output emif_hps_mem_reset_n, + output emif_hps_mem_act_n, + output emif_hps_mem_par, + input emif_hps_mem_alert_n, + inout [ 8:0] emif_hps_mem_dqs_p, + inout [ 8:0] emif_hps_mem_dqs_n, + inout [ 8:0] emif_hps_mem_dbi_n, + inout [71:0] emif_hps_mem_dq, + input emif_hps_oct_rzq, + + // sys-ddr + input sys_ddr_ref_clk_clk, + output sys_ddr_mem_mem_clk_p, + output sys_ddr_mem_mem_clk_n, + output [16:0] sys_ddr_mem_mem_a, + output sys_ddr_mem_mem_act_n, + output [ 1:0] sys_ddr_mem_mem_ba, + output [ 1:0] sys_ddr_mem_mem_bg, + output sys_ddr_mem_mem_cke, + output sys_ddr_mem_mem_cs_n, + output sys_ddr_mem_mem_odt, + output sys_ddr_mem_mem_reset_n, + output sys_ddr_mem_mem_par, + input sys_ddr_mem_mem_alert_n, + inout [17:0] sys_ddr_mem_mem_dqs_p, + inout [17:0] sys_ddr_mem_mem_dqs_n, + inout [71:0] sys_ddr_mem_mem_dq, + input sys_ddr_oct_oct_rzq, + + // hps-emac + input hps_emac_rxclk, + input hps_emac_rxctl, + input [ 3:0] hps_emac_rxd, + output hps_emac_txclk, + output hps_emac_txctl, + output [ 3:0] hps_emac_txd, + output hps_emac_mdc, + inout hps_emac_mdio, + + // hps-sdio + output hps_sdio_clk, + inout hps_sdio_cmd, + inout [ 3:0] hps_sdio_d, + + // hps-usb + input hps_usb_clk, + input hps_usb_dir, + input hps_usb_nxt, + output hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + input hps_uart_rx, + output hps_uart_tx, + + // hps-i2c + inout hps_i2c_sda, + inout hps_i2c_scl, + + // hps-jtag + input hps_jtag_tck, + input hps_jtag_tms, + output hps_jtag_tdo, + input hps_jtag_tdi, + + // hps-OOBE daughter card peripherals + inout hps_gpio_eth_irq, + inout hps_gpio_usb_oci, + inout [ 1:0] hps_gpio_btn, + inout [ 2:0] hps_gpio_led, + + // FMC HPC+ IOs + input [RX_NO_LANES-1:0] rx_data_p, + input [RX_NO_LANES-1:0] rx_data_n, + output [TX_NO_LANES-1:0] tx_data_p, + output [TX_NO_LANES-1:0] tx_data_n, + + inout [30:15] gpio, + inout aux_gpio, + + input syncinb_a0, + inout syncinb_a1_p_gpio, + inout syncinb_a1_n_gpio, + + output syncoutb_a0, + inout syncoutb_a1_p_gpio, + inout syncoutb_a1_n_gpio, + + input fpga_refclk_in, + input sysref_in, + + output spi2_sclk, + inout spi2_sdio, + input spi2_sdo, + output [ 5:0] spi2_cs, + + output dut_sdio, + input dut_sdo, + output dut_sclk, + output dut_csb, + + input device_clk, + + output [ 1:0] trig_a, + output [ 1:0] trig_b, + + input trig_in, + output resetb +); + + // internal signals + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [ 7:0] fpga_dipsw; + wire [ 7:0] fpga_led; + + wire ninit_done; + wire sys_reset_n; + wire h2f_reset; + wire [43:0] stm_hw_events; + + wire spi_clk; + wire [ 7:0] spi_csn; + wire spi_sdo; + wire spi_sdio; + wire hmc7044_sdo; + + wire apollo_spi_clk; + wire [ 7:0] apollo_spi_csn; + wire apollo_spi_sdo; + wire apollo_spi_sdio; + + wire sys_ddr_status_local_cal_success; + wire sys_ddr_status_local_cal_fail; + wire sys_ddr4_local_reset_status_local_reset_done; + wire sys_ddr4_pll_locked_pll_locked; + wire tx_fifo_bypass; + + wire refclk_fgt_2; + + assign spi2_cs[5:0] = spi_csn[5:0]; + assign spi2_sclk = spi_clk; + + ad9084_ebz_spi #( + .NUM_OF_SLAVES(2) + ) i_spi ( + .spi_csn (spi_csn[1:0]), + .spi_clk (spi_clk), + .spi_mosi (spi_sdio), + .spi_miso (spi_sdo), + .spi_miso_in (spi2_sdo), + .spi_sdio (spi2_sdio)); + + assign dut_csb = apollo_spi_csn[0]; + assign dut_sclk = apollo_spi_clk; + assign dut_sdio = apollo_spi_sdio; + + assign apollo_spi_sdo = ~apollo_spi_csn[0] ? dut_sdo : 1'b0; + + // Board GPIOs + assign fpga_led = gpio_o[7:0]; + assign gpio_i[ 7: 0] = gpio_o[7:0]; + assign gpio_i[15: 8] = fpga_dipsw; + assign gpio_i[17:16] = fpga_gpio[ 1:0]; // push buttons + assign gpio_i[28:18] = fpga_gpio[12:2]; + + // FMC GPIOs + assign gpio_i[ 48] = aux_gpio; + assign gpio_i[47:32] = gpio[30:15]; + assign gpio_i[ 53] = trig_in; + + assign trig_a[0] = gpio_o[58]; + assign trig_a[1] = gpio_o[59]; + assign trig_b[0] = gpio_o[60]; + assign trig_b[1] = gpio_o[61]; + assign resetb = gpio_o[62]; + + assign tx_fifo_bypass = gpio_o[63]; + + // Unused GPIOs + assign gpio_i[63:54] = gpio_o[63:54]; + assign gpio_i[52:49] = gpio_o[52:49]; + assign gpio_i[31:29] = gpio_o[31:29]; + + assign sys_reset_n = sys_resetn & ~h2f_reset & ~ninit_done; + assign stm_hw_events = {14'b0, fpga_led, fpga_dipsw, fpga_gpio[1:0]}; + + gpio_slave i_gpio_slave ( + .reset_n (sys_reset_n), + .clk (fpga_sgpio_clk), + .sync (fpga_sgpio_sync), + .miso (fpga_sgpo), + .mosi (fpga_sgpi), + .leds (fpga_led), + .dipsw (fpga_dipsw)); + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_hps_io_hps_osc_clk (hps_io_ref_clk), + + .sys_rst_reset_n (sys_reset_n), + .rst_ninit_done (ninit_done), + .sys_gpio_bd_in_port (gpio_i[31: 0]), + .sys_gpio_bd_out_port (gpio_o[31: 0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .emif_hps_ddr_mem_ck (emif_hps_mem_clk_p), + .emif_hps_ddr_mem_ck_n (emif_hps_mem_clk_n), + .emif_hps_ddr_mem_a (emif_hps_mem_a), + .emif_hps_ddr_mem_act_n (emif_hps_mem_act_n), + .emif_hps_ddr_mem_ba (emif_hps_mem_ba), + .emif_hps_ddr_mem_bg (emif_hps_mem_bg), + .emif_hps_ddr_mem_cke (emif_hps_mem_cke), + .emif_hps_ddr_mem_cs_n (emif_hps_mem_cs_n), + .emif_hps_ddr_mem_odt (emif_hps_mem_odt), + .emif_hps_ddr_mem_reset_n (emif_hps_mem_reset_n), + .emif_hps_ddr_mem_par (emif_hps_mem_par), + .emif_hps_ddr_mem_alert_n (emif_hps_mem_alert_n), + .emif_hps_ddr_mem_dqs (emif_hps_mem_dqs_p), + .emif_hps_ddr_mem_dqs_n (emif_hps_mem_dqs_n), + .emif_hps_ddr_mem_dq (emif_hps_mem_dq), + .emif_hps_ddr_mem_dbi_n (emif_hps_mem_dbi_n), + .emif_hps_oct_rzqin (emif_hps_oct_rzq), + .emif_hps_pll_ref_clk (emif_hps_pll_ref_clk), + + .sys_ddr_ref_clk_clk (sys_ddr_ref_clk_clk), + .sys_ddr_mem_mem_ck (sys_ddr_mem_mem_clk_p), + .sys_ddr_mem_mem_ck_n (sys_ddr_mem_mem_clk_n), + .sys_ddr_mem_mem_a (sys_ddr_mem_mem_a), + .sys_ddr_mem_mem_act_n (sys_ddr_mem_mem_act_n), + .sys_ddr_mem_mem_ba (sys_ddr_mem_mem_ba), + .sys_ddr_mem_mem_bg (sys_ddr_mem_mem_bg), + .sys_ddr_mem_mem_cke (sys_ddr_mem_mem_cke), + .sys_ddr_mem_mem_cs_n (sys_ddr_mem_mem_cs_n), + .sys_ddr_mem_mem_odt (sys_ddr_mem_mem_odt), + .sys_ddr_mem_mem_reset_n (sys_ddr_mem_mem_reset_n), + .sys_ddr_mem_mem_par (sys_ddr_mem_mem_par), + .sys_ddr_mem_mem_alert_n (sys_ddr_mem_mem_alert_n), + .sys_ddr_mem_mem_dqs (sys_ddr_mem_mem_dqs_p), + .sys_ddr_mem_mem_dqs_n (sys_ddr_mem_mem_dqs_n), + .sys_ddr_mem_mem_dq (sys_ddr_mem_mem_dq), + .sys_ddr_oct_oct_rzqin (sys_ddr_oct_oct_rzq), + .sys_ddr_status_local_cal_success (sys_ddr_status_local_cal_success), + .sys_ddr_status_local_cal_fail (sys_ddr_status_local_cal_fail), + .sys_ddr4_pll_locked_pll_locked (sys_ddr4_pll_locked_pll_locked), + .sys_ddr4_local_reset_local_reset_req (sys_ddr4_pll_locked_pll_locked), + .sys_ddr4_local_reset_status_local_reset_done (sys_ddr4_local_reset_status_local_reset_done), + + .sys_hps_io_EMAC0_TX_CLK (hps_emac_txclk), + .sys_hps_io_EMAC0_TX_CTL (hps_emac_txctl), + .sys_hps_io_EMAC0_TXD0 (hps_emac_txd[0]), + .sys_hps_io_EMAC0_TXD1 (hps_emac_txd[1]), + .sys_hps_io_EMAC0_TXD2 (hps_emac_txd[2]), + .sys_hps_io_EMAC0_TXD3 (hps_emac_txd[3]), + .sys_hps_io_EMAC0_RX_CLK (hps_emac_rxclk), + .sys_hps_io_EMAC0_RX_CTL (hps_emac_rxctl), + .sys_hps_io_EMAC0_RXD0 (hps_emac_rxd[0]), + .sys_hps_io_EMAC0_RXD1 (hps_emac_rxd[1]), + .sys_hps_io_EMAC0_RXD2 (hps_emac_rxd[2]), + .sys_hps_io_EMAC0_RXD3 (hps_emac_rxd[3]), + .sys_hps_io_EMAC0_MDIO (hps_emac_mdio), + .sys_hps_io_EMAC0_MDC (hps_emac_mdc), + + .sys_hps_io_SDMMC_CCLK (hps_sdio_clk), + .sys_hps_io_SDMMC_CMD (hps_sdio_cmd), + .sys_hps_io_SDMMC_D0 (hps_sdio_d[0]), + .sys_hps_io_SDMMC_D1 (hps_sdio_d[1]), + .sys_hps_io_SDMMC_D2 (hps_sdio_d[2]), + .sys_hps_io_SDMMC_D3 (hps_sdio_d[3]), + + .sys_hps_io_USB0_CLK (hps_usb_clk), + .sys_hps_io_USB0_STP (hps_usb_stp), + .sys_hps_io_USB0_DIR (hps_usb_dir), + .sys_hps_io_USB0_NXT (hps_usb_nxt), + .sys_hps_io_USB0_DATA0 (hps_usb_d[0]), + .sys_hps_io_USB0_DATA1 (hps_usb_d[1]), + .sys_hps_io_USB0_DATA2 (hps_usb_d[2]), + .sys_hps_io_USB0_DATA3 (hps_usb_d[3]), + .sys_hps_io_USB0_DATA4 (hps_usb_d[4]), + .sys_hps_io_USB0_DATA5 (hps_usb_d[5]), + .sys_hps_io_USB0_DATA6 (hps_usb_d[6]), + .sys_hps_io_USB0_DATA7 (hps_usb_d[7]), + + .sys_hps_io_UART0_RX (hps_uart_rx), + .sys_hps_io_UART0_TX (hps_uart_tx), + + .sys_hps_io_I2C1_SDA (hps_i2c_sda), + .sys_hps_io_I2C1_SCL (hps_i2c_scl), + + .sys_hps_io_jtag_tck (hps_jtag_tck), + .sys_hps_io_jtag_tms (hps_jtag_tms), + .sys_hps_io_jtag_tdo (hps_jtag_tdo), + .sys_hps_io_jtag_tdi (hps_jtag_tdi), + //Terminate the CS_JTAG. + .sys_hps_h2f_cs_ntrst (1'b1), + .sys_hps_h2f_cs_tck (1'b1), + .sys_hps_h2f_cs_tdi (1'b1), + .sys_hps_h2f_cs_tdo (), + .sys_hps_h2f_cs_tdoen (), + .sys_hps_h2f_cs_tms (1'b1), + + .sys_hps_io_gpio1_io0 (hps_gpio_eth_irq), + .sys_hps_io_gpio1_io1 (hps_gpio_usb_oci), + .sys_hps_io_gpio1_io4 (hps_gpio_btn[0]), + .sys_hps_io_gpio1_io5 (hps_gpio_btn[1]), + .sys_hps_io_gpio1_io19 (hps_gpio_led[1]), + .sys_hps_io_gpio1_io20 (hps_gpio_led[0]), + .sys_hps_io_gpio1_io21 (hps_gpio_led[2]), + + .h2f_reset_reset (h2f_reset), + + .sys_hps_f2h_stm_hwevents (stm_hw_events), + + .sys_spi_MISO (spi_sdo), + .sys_spi_MOSI (spi_sdio), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn), + // FMC HPC + .apollo_spi_MISO (apollo_spi_sdo), + .apollo_spi_MOSI (apollo_spi_sdio), + .apollo_spi_SCLK (apollo_spi_clk), + .apollo_spi_SS_n (apollo_spi_csn), + .tx_serial_data_tx_serial_data (tx_data_p), + .tx_serial_data_n_tx_serial_data_n (tx_data_n), + .tx_ref_clk_clk (refclk_fgt_2), + .tx_sync_export (syncinb_a0), + .tx_sysref_export (sysref_in), + .tx_device_clk_clk (device_clk), + .tx_fifo_bypass_bypass (tx_fifo_bypass), + .rx_serial_data_rx_serial_data (rx_data_p), + .rx_serial_data_n_rx_serial_data_n (rx_data_n), + .rx_ref_clk_clk (refclk_fgt_2), + .rx_sync_export (syncoutb_a0), + .rx_sysref_export (sysref_in), + .rx_device_clk_clk (device_clk), + .ref_clk_in_in_refclk_fgt_2 (fpga_refclk_in), + .ref_clk_fgt_2_clk (refclk_fgt_2), + .apollo_gpio_export ({syncinb_a1_n_gpio, // 19 + syncinb_a1_p_gpio, // 18 + syncoutb_a1_n_gpio, // 17 + syncoutb_a1_p_gpio, // 16 + gpio})); // 15:0 + +endmodule diff --git a/projects/ad9084_ebz/vck190/Makefile b/projects/ad9084_ebz/vck190/Makefile new file mode 100755 index 00000000000..9c8951c93fe --- /dev/null +++ b/projects/ad9084_ebz/vck190/Makefile @@ -0,0 +1,50 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9084_ebz_vck190 + +M_DEPS += ../common/versal_transceiver.tcl +M_DEPS += ../common/versal_hsci_phy.tcl +M_DEPS += ../common/ad9084_ebz_spi.v +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../common/vmk180/vmk180_system_bd.tcl +M_DEPS += ../../common/vck190/vck190_system_constr.xdc +M_DEPS += ../../common/vck190/vck190_system_bd.tcl +M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../projects/common/xilinx/data_offload_bd.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hsci +LIB_DEPS += axi_sysid +LIB_DEPS += axi_tdd +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_tdd_sync +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9084_ebz/vck190/system_bd.tcl b/projects/ad9084_ebz/vck190/system_bd.tcl new file mode 100755 index 00000000000..f7c52d5aed7 --- /dev/null +++ b/projects/ad9084_ebz/vck190/system_bd.tcl @@ -0,0 +1,86 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +set ASYMMETRIC_A_B_MODE [ expr { [info exists ad_project_params(ASYMMETRIC_A_B_MODE)] \ + ? $ad_project_params(ASYMMETRIC_A_B_MODE) : 0 } ] + +if {$ASYMMETRIC_A_B_MODE == 1} { + ## ADC B Side FIFO depth in samples per converter + set adc_b_fifo_samples_per_converter [expr $ad_project_params(RX_B_KS_PER_CHANNEL)*1024] + ## DAC B Side FIFO depth in samples per converter + set dac_b_fifo_samples_per_converter [expr $ad_project_params(TX_B_KS_PER_CHANNEL)*1024] +} + +source $ad_hdl_dir/projects/common/vck190/vck190_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl + +set ADI_PHY_SEL 0 +set MAX_NUMBER_OF_QUADS 3 +set TRANSCEIVER_TYPE GTY +set HSCI_BANKS 2 +set HSCI_ENABLE [ expr { [info exists ad_project_params(HSCI_ENABLE)] \ + ? $ad_project_params(HSCI_ENABLE) : 1 } ] + +adi_project_files ad9084_ebz_vck190 [list \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ +] + + +source $ad_hdl_dir/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2 +ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 + +if {$ASYMMETRIC_A_B_MODE == 1} { + ad_ip_parameter axi_apollo_rx_b_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2 + ad_ip_parameter axi_apollo_tx_b_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 +} + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +# Second SPI controller +create_bd_port -dir O -from 7 -to 0 apollo_spi_csn_o +create_bd_port -dir I -from 7 -to 0 apollo_spi_csn_i +create_bd_port -dir I apollo_spi_clk_i +create_bd_port -dir O apollo_spi_clk_o +create_bd_port -dir I apollo_spi_sdo_i +create_bd_port -dir O apollo_spi_sdo_o +create_bd_port -dir I apollo_spi_sdi_i + +ad_ip_instance axi_quad_spi axi_spi_2 +ad_ip_parameter axi_spi_2 CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_2 CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi_2 CONFIG.C_SCK_RATIO 16 +ad_ip_parameter axi_spi_2 CONFIG.Multiples16 1 + +ad_connect apollo_spi_csn_i axi_spi_2/ss_i +ad_connect apollo_spi_csn_o axi_spi_2/ss_o +ad_connect apollo_spi_clk_i axi_spi_2/sck_i +ad_connect apollo_spi_clk_o axi_spi_2/sck_o +ad_connect apollo_spi_sdo_i axi_spi_2/io0_i +ad_connect apollo_spi_sdo_o axi_spi_2/io0_o +ad_connect apollo_spi_sdi_i axi_spi_2/io1_i + +ad_connect $sys_cpu_clk axi_spi_2/ext_spi_clk + +ad_cpu_interrupt ps-9 mb-16 axi_spi_2/ip2intc_irpt + +ad_cpu_interconnect 0x44A80000 axi_spi_2 + +if {$HSCI_ENABLE} { + set_property range 256K [get_bd_addr_segs {sys_cips/M_AXI_FPD/SEG_data_axi_hsci_0}] +} diff --git a/projects/ad9084_ebz/vck190/system_constr.xdc b/projects/ad9084_ebz/vck190/system_constr.xdc new file mode 100644 index 00000000000..0b19999cbca --- /dev/null +++ b/projects/ad9084_ebz/vck190/system_constr.xdc @@ -0,0 +1,144 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# +## Apollo +# + +set_property -dict {PACKAGE_PIN K1 } [get_ports stxb_n[0] ] ; ## FMC2_DP0_M2C_N GTY_204 +set_property -dict {PACKAGE_PIN K2 } [get_ports stxb_p[0] ] ; ## FMC2_DP0_M2C_P GTY_204 +set_property -dict {PACKAGE_PIN J3 } [get_ports stxb_n[1] ] ; ## FMC2_DP1_M2C_N GTY_204 +set_property -dict {PACKAGE_PIN J4 } [get_ports stxb_p[1] ] ; ## FMC2_DP1_M2C_P GTY_204 +set_property -dict {PACKAGE_PIN H1 } [get_ports stxb_n[2] ] ; ## FMC2_DP2_M2C_N GTY_204 +set_property -dict {PACKAGE_PIN H2 } [get_ports stxb_p[2] ] ; ## FMC2_DP2_M2C_P GTY_204 +set_property -dict {PACKAGE_PIN H5 } [get_ports stxb_n[3] ] ; ## FMC2_DP3_M2C_N GTY_204 +set_property -dict {PACKAGE_PIN H6 } [get_ports stxb_p[3] ] ; ## FMC2_DP3_M2C_P GTY_204 +set_property -dict {PACKAGE_PIN G3 } [get_ports stxa_n[0] ] ; ## FMC2_DP4_M2C_N GTY_205 +set_property -dict {PACKAGE_PIN G4 } [get_ports stxa_p[0] ] ; ## FMC2_DP4_M2C_P GTY_205 +set_property -dict {PACKAGE_PIN F1 } [get_ports stxa_n[1] ] ; ## FMC2_DP5_M2C_N GTY_205 +set_property -dict {PACKAGE_PIN F2 } [get_ports stxa_p[1] ] ; ## FMC2_DP5_M2C_P GTY_205 +set_property -dict {PACKAGE_PIN F5 } [get_ports stxa_n[2] ] ; ## FMC2_DP6_M2C_N GTY_205 +set_property -dict {PACKAGE_PIN F6 } [get_ports stxa_p[2] ] ; ## FMC2_DP6_M2C_P GTY_205 +set_property -dict {PACKAGE_PIN E3 } [get_ports stxa_n[3] ] ; ## FMC2_DP7_M2C_N GTY_205 +set_property -dict {PACKAGE_PIN E4 } [get_ports stxa_p[3] ] ; ## FMC2_DP7_M2C_P GTY_205 +set_property -dict {PACKAGE_PIN D1 } [get_ports stxb_n[4] ] ; ## FMC2_DP8_M2C_N GTY_206 +set_property -dict {PACKAGE_PIN D2 } [get_ports stxb_p[4] ] ; ## FMC2_DP8_M2C_P GTY_206 +set_property -dict {PACKAGE_PIN D5 } [get_ports stxb_n[5] ] ; ## FMC2_DP9_M2C_N GTY_206 +set_property -dict {PACKAGE_PIN D6 } [get_ports stxb_p[5] ] ; ## FMC2_DP9_M2C_P GTY_206 +set_property -dict {PACKAGE_PIN C3 } [get_ports stxb_n[6] ] ; ## FMC2_DP10_M2C_N GTY_206 +set_property -dict {PACKAGE_PIN C4 } [get_ports stxb_p[6] ] ; ## FMC2_DP10_M2C_P GTY_206 +set_property -dict {PACKAGE_PIN B5 } [get_ports stxb_n[7] ] ; ## FMC2_DP11_M2C_N GTY_206 +set_property -dict {PACKAGE_PIN B6 } [get_ports stxb_p[7] ] ; ## FMC2_DP11_M2C_P GTY_206 + +set_property -dict {PACKAGE_PIN K6 } [get_ports srxb_n[0] ] ; ## FMC2_DP0_C2M_N GTY_204 +set_property -dict {PACKAGE_PIN K7 } [get_ports srxb_p[0] ] ; ## FMC2_DP0_C2M_P GTY_204 +set_property -dict {PACKAGE_PIN K10 } [get_ports srxb_n[1] ] ; ## FMC2_DP1_C2M_N GTY_204 +set_property -dict {PACKAGE_PIN K11 } [get_ports srxb_p[1] ] ; ## FMC2_DP1_C2M_P GTY_204 +set_property -dict {PACKAGE_PIN J8 } [get_ports srxb_n[2] ] ; ## FMC2_DP2_C2M_N GTY_204 +set_property -dict {PACKAGE_PIN J9 } [get_ports srxb_p[2] ] ; ## FMC2_DP2_C2M_P GTY_204 +set_property -dict {PACKAGE_PIN H10 } [get_ports srxb_n[3] ] ; ## FMC2_DP3_C2M_N GTY_204 +set_property -dict {PACKAGE_PIN H11 } [get_ports srxb_p[3] ] ; ## FMC2_DP3_C2M_P GTY_204 +set_property -dict {PACKAGE_PIN G8 } [get_ports srxa_n[0] ] ; ## FMC2_DP4_C2M_N GTY_205 +set_property -dict {PACKAGE_PIN G9 } [get_ports srxa_p[0] ] ; ## FMC2_DP4_C2M_P GTY_205 +set_property -dict {PACKAGE_PIN F10 } [get_ports srxa_n[1] ] ; ## FMC2_DP5_C2M_N GTY_205 +set_property -dict {PACKAGE_PIN F11 } [get_ports srxa_p[1] ] ; ## FMC2_DP5_C2M_P GTY_205 +set_property -dict {PACKAGE_PIN E8 } [get_ports srxa_n[2] ] ; ## FMC2_DP6_C2M_N GTY_205 +set_property -dict {PACKAGE_PIN E9 } [get_ports srxa_p[2] ] ; ## FMC2_DP6_C2M_P GTY_205 +set_property -dict {PACKAGE_PIN D10 } [get_ports srxa_n[3] ] ; ## FMC2_DP7_C2M_N GTY_205 +set_property -dict {PACKAGE_PIN D11 } [get_ports srxa_p[3] ] ; ## FMC2_DP7_C2M_P GTY_205 +set_property -dict {PACKAGE_PIN C8 } [get_ports srxb_n[4] ] ; ## FMC2_DP8_C2M_N GTY_206 +set_property -dict {PACKAGE_PIN C9 } [get_ports srxb_p[4] ] ; ## FMC2_DP8_C2M_P GTY_206 +set_property -dict {PACKAGE_PIN B10 } [get_ports srxb_n[5] ] ; ## FMC2_DP9_C2M_N GTY_206 +set_property -dict {PACKAGE_PIN B11 } [get_ports srxb_p[5] ] ; ## FMC2_DP9_C2M_P GTY_206 +set_property -dict {PACKAGE_PIN A8 } [get_ports srxb_n[6] ] ; ## FMC2_DP10_C2M_N GTY_206 +set_property -dict {PACKAGE_PIN A9 } [get_ports srxb_p[6] ] ; ## FMC2_DP10_C2M_P GTY_206 +set_property -dict {PACKAGE_PIN A12 } [get_ports srxb_n[7] ] ; ## FMC2_DP11_C2M_N GTY_206 +set_property -dict {PACKAGE_PIN A13 } [get_ports srxb_p[7] ] ; ## FMC2_DP11_C2M_P GTY_206 + +set_property -dict {PACKAGE_PIN AU12 IOSTANDARD LVCMOS15 } [get_ports gpio[15] ] ; ## FMC2_LA06_P +set_property -dict {PACKAGE_PIN AU11 IOSTANDARD LVCMOS15 } [get_ports gpio[16] ] ; ## FMC2_LA06_N +set_property -dict {PACKAGE_PIN BE15 IOSTANDARD LVCMOS15 } [get_ports gpio[23] ] ; ## FMC2_LA14_P +set_property -dict {PACKAGE_PIN BE14 IOSTANDARD LVCMOS15 } [get_ports gpio[24] ] ; ## FMC2_LA14_N +set_property -dict {PACKAGE_PIN AU13 IOSTANDARD LVCMOS15 } [get_ports gpio[27] ] ; ## FMC2_LA18_CC_P +set_property -dict {PACKAGE_PIN AV13 IOSTANDARD LVCMOS15 } [get_ports gpio[28] ] ; ## FMC2_LA18_CC_N +set_property -dict {PACKAGE_PIN BB11 IOSTANDARD LVCMOS15 } [get_ports gpio[21] ] ; ## FMC2_LA12_P +set_property -dict {PACKAGE_PIN BC11 IOSTANDARD LVCMOS15 } [get_ports gpio[22] ] ; ## FMC2_LA12_N +set_property -dict {PACKAGE_PIN BG15 IOSTANDARD LVCMOS15 } [get_ports gpio[17] ] ; ## FMC2_LA07_P +set_property -dict {PACKAGE_PIN BG14 IOSTANDARD LVCMOS15 } [get_ports gpio[18] ] ; ## FMC2_LA07_N +set_property -dict {PACKAGE_PIN BC12 IOSTANDARD LVCMOS15 } [get_ports gpio[19] ] ; ## FMC2_LA11_P +set_property -dict {PACKAGE_PIN BD12 IOSTANDARD LVCMOS15 } [get_ports gpio[20] ] ; ## FMC2_LA11_N +set_property -dict {PACKAGE_PIN BE12 IOSTANDARD LVCMOS15 } [get_ports gpio[25] ] ; ## FMC2_LA15_P +set_property -dict {PACKAGE_PIN BF13 IOSTANDARD LVCMOS15 } [get_ports gpio[26] ] ; ## FMC2_LA15_N +set_property -dict {PACKAGE_PIN AR14 IOSTANDARD LVCMOS15 } [get_ports gpio[29] ] ; ## FMC2_LA19_P +set_property -dict {PACKAGE_PIN AT13 IOSTANDARD LVCMOS15 } [get_ports gpio[30] ] ; ## FMC2_LA19_N +set_property -dict {PACKAGE_PIN AM17 IOSTANDARD LVCMOS15 } [get_ports aux_gpio ] ; ## FMC2_LA32_N + +set_property -dict {PACKAGE_PIN AP15 IOSTANDARD LVCMOS15 } [get_ports syncinb_a1_p_gpio ] ; ## FMC2_LA20_P +set_property -dict {PACKAGE_PIN AR15 IOSTANDARD LVCMOS15 } [get_ports syncinb_a1_n_gpio ] ; ## FMC2_LA20_N +set_property -dict {PACKAGE_PIN AP11 IOSTANDARD LVCMOS15 } [get_ports syncinb_b1_p_gpio ] ; ## FMC2_LA22_P +set_property -dict {PACKAGE_PIN AR12 IOSTANDARD LVCMOS15 } [get_ports syncinb_b1_n_gpio ] ; ## FMC2_LA22_N +set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS15 } [get_ports syncoutb_a1_p_gpio ] ; ## FMC2_LA21_P +set_property -dict {PACKAGE_PIN AP13 IOSTANDARD LVCMOS15 } [get_ports syncoutb_a1_n_gpio ] ; ## FMC2_LA21_N +set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS15 } [get_ports syncoutb_b1_p_gpio ] ; ## FMC2_LA23_P +set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS15 } [get_ports syncoutb_b1_n_gpio ] ; ## FMC2_LA23_N + +set_property -dict {PACKAGE_PIN BF11 IOSTANDARD LVDS15 } [get_ports syncinb_a0_p ] ; ## FMC2_LA04_P +set_property -dict {PACKAGE_PIN BG11 IOSTANDARD LVDS15 } [get_ports syncinb_a0_n ] ; ## FMC2_LA04_N +set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVDS15 } [get_ports syncinb_b0_p ] ; ## FMC2_LA08_P +set_property -dict {PACKAGE_PIN AV14 IOSTANDARD LVDS15 } [get_ports syncinb_b0_n ] ; ## FMC2_LA08_N +set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_a0_p ] ; ## FMC2_LA05_P +set_property -dict {PACKAGE_PIN BA13 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_a0_n ] ; ## FMC2_LA05_N +set_property -dict {PACKAGE_PIN BD15 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_b0_p ] ; ## FMC2_LA09_P +set_property -dict {PACKAGE_PIN BD14 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_b0_n ] ; ## FMC2_LA09_N + +set_property -dict {PACKAGE_PIN D15 } [get_ports ref_clk_p[0] ] ; ## FMC2_GBTCLK1_M2C_C_P GTY_205 +set_property -dict {PACKAGE_PIN D14 } [get_ports ref_clk_n[0] ] ; ## FMC2_GBTCLK1_M2C_C_N GTY_205 + +set_property -dict {PACKAGE_PIN AV11 IOSTANDARD LVDS15 } [get_ports sysref_a_p ] ; ## FMC2_LA16_P +set_property -dict {PACKAGE_PIN AW11 IOSTANDARD LVDS15 } [get_ports sysref_a_n ] ; ## FMC2_LA16_N +set_property -dict {PACKAGE_PIN AY13 IOSTANDARD LVDS15 } [get_ports sysref_b_p ] ; ## FMC2_LA17_CC_P +set_property -dict {PACKAGE_PIN BA12 IOSTANDARD LVDS15 } [get_ports sysref_b_n ] ; ## FMC2_LA17_CC_N +set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref_p ] ; ## FMC2_LA00_CC_P +set_property -dict {PACKAGE_PIN BD13 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref_n ] ; ## FMC2_LA00_CC_N +set_property -dict {PACKAGE_PIN AT17 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref_in_p ] ; ## FMC2_LA33_P +set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref_in_n ] ; ## FMC2_LA33_N + +set_property -dict {PACKAGE_PIN AR11 IOSTANDARD LVCMOS15 } [get_ports spi2_sclk ] ; ## FMC2_LA24_P +set_property -dict {PACKAGE_PIN AT11 IOSTANDARD LVCMOS15 } [get_ports spi2_sdio ] ; ## FMC2_LA24_N +set_property -dict {PACKAGE_PIN AV19 IOSTANDARD LVCMOS15 } [get_ports spi2_sdo ] ; ## FMC2_LA26_P +set_property -dict {PACKAGE_PIN AV18 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[0] ] ; ## FMC2_LA26_N +set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[1] ] ; ## FMC2_LA29_P +set_property -dict {PACKAGE_PIN AN17 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[2] ] ; ## FMC2_LA29_N +set_property -dict {PACKAGE_PIN AN16 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[3] ] ; ## FMC2_LA30_P +set_property -dict {PACKAGE_PIN AP16 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[4] ] ; ## FMC2_LA30_N +set_property -dict {PACKAGE_PIN AL16 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[5] ] ; ## FMC2_LA32_P + +set_property -dict {PACKAGE_PIN BE11 IOSTANDARD LVCMOS15 } [get_ports dut_sdio ] ; ## FMC2_LA03_P +set_property -dict {PACKAGE_PIN BF12 IOSTANDARD LVCMOS15 } [get_ports dut_sdo ] ; ## FMC2_LA03_N +set_property -dict {PACKAGE_PIN BF14 IOSTANDARD LVCMOS15 } [get_ports dut_sclk ] ; ## FMC2_LA02_P +set_property -dict {PACKAGE_PIN BG13 IOSTANDARD LVCMOS15 } [get_ports dut_csb ] ; ## FMC2_LA02_N + +set_property -dict {PACKAGE_PIN BB14 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_p[0] ] ; ## FMC2_CLK0_M2C_P +set_property -dict {PACKAGE_PIN BB13 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_n[0] ] ; ## FMC2_CLK0_M2C_N +set_property -dict {PACKAGE_PIN AW19 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_p[1] ] ; ## FMC2_CLK1_M2C_P +set_property -dict {PACKAGE_PIN AY18 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_n[1] ] ; ## FMC2_CLK1_M2C_N + +set_property -dict {PACKAGE_PIN AT14 IOSTANDARD LVCMOS15 } [get_ports trig_a[0] ] ; ## FMC2_LA10_P +set_property -dict {PACKAGE_PIN AU15 IOSTANDARD LVCMOS15 } [get_ports trig_a[1] ] ; ## FMC2_LA10_N +set_property -dict {PACKAGE_PIN BB15 IOSTANDARD LVCMOS15 } [get_ports trig_b[0] ] ; ## FMC2_LA13_P +set_property -dict {PACKAGE_PIN BC15 IOSTANDARD LVCMOS15 } [get_ports trig_b[1] ] ; ## FMC2_LA13_N +set_property -dict {PACKAGE_PIN AW13 IOSTANDARD LVCMOS15 } [get_ports trig_in ] ; ## FMC2_LA01_CC_N +set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS15 } [get_ports resetb ] ; ## FMC2_LA01_CC_P + +set_property -dict {PACKAGE_PIN AW20 IOSTANDARD LVDS15 } [get_ports hsci_ckin_p ] ; ## FMC2_LA27_P # Bank 707 +set_property -dict {PACKAGE_PIN AY19 IOSTANDARD LVDS15 } [get_ports hsci_ckin_n ] ; ## FMC2_LA27_N # Bank 707 +set_property -dict {PACKAGE_PIN AY11 IOSTANDARD LVDS15 } [get_ports hsci_din_p ] ; ## FMC2_LA25_P # Bank 708 +set_property -dict {PACKAGE_PIN BA11 IOSTANDARD LVDS15 } [get_ports hsci_din_n ] ; ## FMC2_LA25_N # Bank 708 +set_property -dict {PACKAGE_PIN AT16 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_p ] ; ## FMC2_LA31_P # Bank 707 +set_property -dict {PACKAGE_PIN AR17 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_n ] ; ## FMC2_LA31_N # Bank 707 +set_property -dict {PACKAGE_PIN AU17 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_p ] ; ## FMC2_LA28_P # Bank 708 +set_property -dict {PACKAGE_PIN AV17 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_n ] ; ## FMC2_LA28_N # Bank 708 + +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_REGION [get_nets i_system_wrapper/system_i/axi_hsci_clkgen/inst/i_mmcm_drp/clk_0] diff --git a/projects/ad9084_ebz/vck190/system_project.tcl b/projects/ad9084_ebz/vck190/system_project.tcl new file mode 100755 index 00000000000..34de1e17efc --- /dev/null +++ b/projects/ad9084_ebz/vck190/system_project.tcl @@ -0,0 +1,94 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../../projects/scripts/adi_project_xilinx.tcl +source ../../../projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make JESD_MODE=64B66B RX_LANE_RATE=10.3125 TX_LANE_RATE=10.3125 RX_JESD_M=4 TX_JESD_M=4 RX_JESD_L=8 TX_JESD_L=8 RX_JESD_S=1 TX_JESD_S=1 RX_JESD_NP=16 TX_JESD_NP=16 +# + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C +# 8B10B - 8b10b link layer defined in JESD 204B +# +# REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B +# HSCI_ENABLE : If set, adds and enables the HSCI core in the design +# RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample +# [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 +# [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) +# ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link +# RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side +# TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side +# [RX/TX]_B_JESD_M : Number of converters per link for B side +# [RX/TX]_B_JESD_L : Number of lanes per link for B side +# [RX/TX]_B_JESD_NP : Number of bits per sample for B side +# [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side +# + +adi_project ad9084_ebz_vck190 0 [list \ + JESD_MODE [get_env_param JESD_MODE 64B66B ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 312.5 ] \ + ENABLE_HSCI [get_env_param HSCI_ENABLE 1 ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 20.625 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 20.625 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 2 ] \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 2 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ + ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0 ] \ + RX_B_LANE_RATE [get_env_param RX_B_LANE_RATE 20.625 ] \ + TX_B_LANE_RATE [get_env_param TX_B_LANE_RATE 20.625 ] \ + RX_B_JESD_M [get_env_param RX_B_JESD_M 4 ] \ + RX_B_JESD_L [get_env_param RX_B_JESD_L 4 ] \ + RX_B_JESD_S [get_env_param RX_B_JESD_S 1 ] \ + RX_B_JESD_NP [get_env_param RX_B_JESD_NP 16 ] \ + TX_B_JESD_M [get_env_param TX_B_JESD_M 4 ] \ + TX_B_JESD_L [get_env_param TX_B_JESD_L 4 ] \ + TX_B_JESD_S [get_env_param TX_B_JESD_S 1 ] \ + TX_B_JESD_NP [get_env_param TX_B_JESD_NP 16 ] \ + RX_B_KS_PER_CHANNEL [get_env_param RX_B_KS_PER_CHANNEL 64 ] \ + TX_B_KS_PER_CHANNEL [get_env_param TX_B_KS_PER_CHANNEL 64 ] \ +] + +adi_project_files ad9084_ebz_vck190 [list \ + "system_top.v" \ + "system_constr.xdc" \ + "timing_constr.tcl" \ + "../common/versal_hsci_phy.tcl" \ + "../common/ad9084_ebz_spi.v" \ + "../common/versal_transceiver.tcl" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc" ] + +# Avoid critical warning in OOC mode from the clock definitions +# since at that stage the submodules are not stiched together yet +if {$ADI_USE_OOC_SYNTHESIS == 1} { + set_property used_in_synthesis false [get_files timing_constr.tcl] +} + +set_property strategy Performance_RefinePlacement [get_runs impl_1] + +adi_project_run ad9084_ebz_vck190 diff --git a/projects/ad9084_ebz/vck190/system_top.v b/projects/ad9084_ebz/vck190/system_top.v new file mode 100755 index 00000000000..3bb4e25a935 --- /dev/null +++ b/projects/ad9084_ebz/vck190/system_top.v @@ -0,0 +1,459 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_NUM_LINKS = 1, + parameter RX_NUM_LINKS = 1, + parameter ASYMMETRIC_A_B_MODE = 0 +) ( + input sys_clk_n, + input sys_clk_p, + output ddr4_act_n, + output [16:0] ddr4_adr, + output [ 1:0] ddr4_ba, + output [ 1:0] ddr4_bg, + output ddr4_ck_c, + output ddr4_ck_t, + output ddr4_cke, + output ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_c, + inout [ 7:0] ddr4_dqs_t, + output ddr4_odt, + output ddr4_reset_n, + // GPIOs + output [ 3:0] gpio_led, + input [ 3:0] gpio_dip_sw, + input [ 1:0] gpio_pb, + + // // FMC HPC+ IOs + output [ 7:0] srxb_p, + output [ 7:0] srxb_n, + output [ 3:0] srxa_p, + output [ 3:0] srxa_n, + + input [ 7:0] stxb_p, + input [ 7:0] stxb_n, + input [ 3:0] stxa_p, + input [ 3:0] stxa_n, + + inout [30:15] gpio, + inout aux_gpio, + + output syncinb_a0_p, + output syncinb_a0_n, + output syncinb_b0_p, + output syncinb_b0_n, + inout syncinb_a1_p_gpio, + inout syncinb_a1_n_gpio, + inout syncinb_b1_p_gpio, + inout syncinb_b1_n_gpio, + + input syncoutb_a0_p, + input syncoutb_a0_n, + input syncoutb_b0_p, + input syncoutb_b0_n, + inout syncoutb_a1_p_gpio, + inout syncoutb_a1_n_gpio, + inout syncoutb_b1_p_gpio, + inout syncoutb_b1_n_gpio, + + input [ 0:0] ref_clk_p, + input [ 0:0] ref_clk_n, + + output sysref_a_p, + output sysref_a_n, + output sysref_b_p, + output sysref_b_n, + input sysref_p, + input sysref_n, + input sysref_in_p, + input sysref_in_n, + + output spi2_sclk, + inout spi2_sdio, + input spi2_sdo, + output [ 5:0] spi2_cs, + + output dut_sdio, + input dut_sdo, + output dut_sclk, + output dut_csb, + + input [ 1:0] clk_m2c_p, + input [ 1:0] clk_m2c_n, + + output hsci_ckin_p, + output hsci_ckin_n, + output hsci_din_p, + output hsci_din_n, + input hsci_cko_p, + input hsci_cko_n, + input hsci_do_p, + input hsci_do_n, + + output [ 1:0] trig_a, + output [ 1:0] trig_b, + + input trig_in, + output resetb +); + + localparam SYNC_W = (ASYMMETRIC_A_B_MODE == 1)? 2 : RX_NUM_LINKS; + + // internal signals + + wire [95:0] gpio_i; + wire [95:0] gpio_o; + wire [95:0] gpio_t; + + wire spi_clk; + wire [ 7:0] spi_csn; + wire spi_sdo; + wire spi_sdio; + wire hmc7044_sdo; + + wire apollo_spi_clk; + wire [ 7:0] apollo_spi_csn; + wire apollo_spi_sdo; + wire apollo_spi_sdio; + + wire ref_clk; + wire ref_clk_replica; + wire sysref; + wire [SYNC_W-1:0] tx_syncin; + wire [SYNC_W-1:0] rx_syncout; + + wire clkin0; + wire clkin1; + wire tx_device_clk; + wire rx_device_clk; + + wire intf_rdy; + wire fifo_empty; + wire fifo_rd_en; + wire [ 7:0] hsci_data_out; + wire [ 7:0] data_from_fabric; + wire [ 7:0] data_to_fabric; + wire [ 7:0] hsci_data_in; + + assign iic_rstn = 1'b1; + wire gt_reset; + wire rx_reset_pll_and_datapath; + wire tx_reset_pll_and_datapath; + wire rx_reset_datapath; + wire tx_reset_datapath; + wire rx_resetdone; + wire tx_resetdone; + wire gt_b_reset; + wire rx_b_reset_pll_and_datapath; + wire tx_b_reset_pll_and_datapath; + wire rx_b_reset_datapath; + wire tx_b_reset_datapath; + wire rx_b_resetdone; + wire tx_b_resetdone; + wire gt_powergood; + + wire [11:0] rx_data_p_loc; + wire [11:0] rx_data_n_loc; + wire [11:0] tx_data_p_loc; + wire [11:0] tx_data_n_loc; + + // instantiations + + IBUFDS_GTE5 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (ref_clk_p[0]), + .IB (ref_clk_n[0]), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref_in ( + .I (sysref_in_p), + .IB (sysref_in_n), + .O (sysref)); + + OBUFDS i_obufds_sysref_a ( + .I (1'b0), + .O (sysref_a_p), + .OB (sysref_a_n)); + + OBUFDS i_obufds_sysref_b ( + .I (1'b0), + .O (sysref_b_p), + .OB (sysref_b_n)); + + IBUFDS i_ibufds_sysref_ext ( + .I (sysref_p), + .IB (sysref_n), + .O ()); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clk_m2c_p[0]), + .IB (clk_m2c_n[0]), + .O (clkin0)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clk_m2c_p[1]), + .IB (clk_m2c_n[1]), + .O (clkin1)); + + IBUFDS i_ibufds_syncin0 ( + .I (syncoutb_a0_p), + .IB (syncoutb_a0_n), + .O (tx_syncin[0])); + + OBUFDS i_obufds_syncout0 ( + .I (rx_syncout[0]), + .O (syncinb_a0_p), + .OB (syncinb_a0_n)); + + IBUFDS i_ibufds_syncin1 ( + .I (syncoutb_b0_p), + .IB (syncoutb_b0_n), + .O (tx_syncin[1])); + + OBUFDS i_obufds_syncout1 ( + .I (rx_syncout[1]), + .O (syncinb_b0_p), + .OB (syncinb_b0_n)); + + BUFG i_rx_device_clk ( + .I (clkin0), + .O (rx_device_clk)); + + BUFG i_tx_device_clk ( + .I (clkin1), + .O (tx_device_clk)); + + // spi + assign spi2_cs[5:0] = spi_csn[5:0]; + assign spi2_sclk = spi_clk; + + ad9084_ebz_spi #( + .NUM_OF_SLAVES(2) + ) i_spi ( + .spi_csn (spi_csn[1:0]), + .spi_clk (spi_clk), + .spi_mosi (spi_sdio), + .spi_miso (spi_sdo), + .spi_miso_in (spi2_sdo), + .spi_sdio (spi2_sdio)); + + assign dut_csb = apollo_spi_csn[0]; + assign dut_sclk = apollo_spi_clk; + assign dut_sdio = apollo_spi_sdio; + + assign apollo_spi_sdo = ~apollo_spi_csn[0] ? dut_sdo : 1'b0; + + // gpios + /* Board GPIOS. Buttons, LEDs, etc... */ + assign gpio_led = gpio_o[3:0]; + assign gpio_i[3:0] = gpio_o[3:0]; + assign gpio_i[7:4] = gpio_dip_sw; + assign gpio_i[9:8] = gpio_pb; + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf ( + .dio_t (gpio_t[48:32]), + .dio_i (gpio_o[48:32]), + .dio_o (gpio_i[48:32]), + .dio_p ({aux_gpio, // 48 + gpio[30:15]})); // 47-32 + + assign gpio_i[53] = trig_in; + + assign trig_a[0] = gpio_o[58]; + assign trig_a[1] = gpio_o[59]; + assign trig_b[0] = gpio_o[60]; + assign trig_b[1] = gpio_o[61]; + assign resetb = gpio_o[62]; + + assign gpio_i[64] = rx_resetdone; + assign gpio_i[65] = tx_resetdone; + assign gpio_i[66] = rx_resetdone & tx_resetdone; + assign gt_reset = gpio_o[67]; + assign rx_reset_pll_and_datapath = gpio_o[68]; + assign tx_reset_pll_and_datapath = gpio_o[69]; + assign rx_reset_datapath = gpio_o[70]; + assign tx_reset_datapath = gpio_o[71]; + + assign gpio_i[72] = rx_b_resetdone; + assign gpio_i[73] = tx_b_resetdone; + assign gpio_i[74] = rx_b_resetdone & tx_b_resetdone; + assign gt_b_reset = gpio_o[75]; + assign rx_b_reset_pll_and_datapath = gpio_o[76]; + assign tx_b_reset_pll_and_datapath = gpio_o[77]; + assign rx_b_reset_datapath = gpio_o[78]; + assign tx_b_reset_datapath = gpio_o[79]; + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf_bd ( + .dio_t (gpio_t[26:10]), + .dio_i (gpio_o[26:10]), + .dio_o (gpio_i[26:10]), + .dio_p (gpio_bd)); + + assign gpio_i[95:80] = gpio_o[95:80]; + assign gpio_i[63:55] = gpio_o[63:55]; + assign gpio_i[31:27] = gpio_o[31:27]; + + assign fifo_rd_en = ~fifo_empty & intf_rdy; + assign data_from_fabric = {hsci_data_out[0], hsci_data_out[1], hsci_data_out[2], hsci_data_out[3], hsci_data_out[4], hsci_data_out[5], hsci_data_out[6], hsci_data_out[7]}; + assign hsci_data_in = (intf_rdy) ? {data_to_fabric[0], data_to_fabric[1], data_to_fabric[2], data_to_fabric[3], data_to_fabric[4], data_to_fabric[5], data_to_fabric[6], data_to_fabric[7]} : 8'h0; + + system_wrapper i_system_wrapper ( + .ddr4_dimm1_sma_clk_clk_n (sys_clk_n), + .ddr4_dimm1_sma_clk_clk_p (sys_clk_p), + .ddr4_dimm1_act_n (ddr4_act_n), + .ddr4_dimm1_adr (ddr4_adr), + .ddr4_dimm1_ba (ddr4_ba), + .ddr4_dimm1_bg (ddr4_bg), + .ddr4_dimm1_ck_c (ddr4_ck_c), + .ddr4_dimm1_ck_t (ddr4_ck_t), + .ddr4_dimm1_cke (ddr4_cke), + .ddr4_dimm1_cs_n (ddr4_cs_n), + .ddr4_dimm1_dm_n (ddr4_dm_n), + .ddr4_dimm1_dq (ddr4_dq), + .ddr4_dimm1_dqs_c (ddr4_dqs_c), + .ddr4_dimm1_dqs_t (ddr4_dqs_t), + .ddr4_dimm1_odt (ddr4_odt), + .ddr4_dimm1_reset_n (ddr4_reset_n), + .spi0_csn (spi_csn), + .spi0_miso (spi_sdo), + .spi0_mosi (spi_sdio), + .spi0_sclk (spi_clk), + + .apollo_spi_clk_i (apollo_spi_clk), + .apollo_spi_clk_o (apollo_spi_clk), + .apollo_spi_csn_i (apollo_spi_csn), + .apollo_spi_csn_o (apollo_spi_csn), + .apollo_spi_sdi_i (apollo_spi_sdo), + .apollo_spi_sdo_i (apollo_spi_sdio), + .apollo_spi_sdo_o (apollo_spi_sdio), + + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .gpio2_i (gpio_i[95:64]), + .gpio2_o (gpio_o[95:64]), + .gpio2_t (gpio_t[95:64]), + + // FMC HPC + .tx_0_p (tx_data_p_loc[ 3:0]), + .tx_0_n (tx_data_n_loc[ 3:0]), + .rx_0_p (rx_data_p_loc[ 3:0]), + .rx_0_n (rx_data_n_loc[ 3:0]), + .tx_1_p (tx_data_p_loc[ 7:4]), + .tx_1_n (tx_data_n_loc[ 7:4]), + .rx_1_p (rx_data_p_loc[ 7:4]), + .rx_1_n (rx_data_n_loc[ 7:4]), + .tx_2_p (tx_data_p_loc[11:8]), + .tx_2_n (tx_data_n_loc[11:8]), + .rx_2_p (rx_data_p_loc[11:8]), + .rx_2_n (rx_data_n_loc[11:8]), + + .gt_powergood (gt_powergood), + .gt_reset (gt_reset & gt_powergood), + .gt_reset_rx_datapath (rx_reset_datapath), + .gt_reset_tx_datapath (tx_reset_datapath), + .gt_reset_rx_pll_and_datapath (rx_reset_pll_and_datapath), + .gt_reset_tx_pll_and_datapath (tx_reset_pll_and_datapath), + .rx_resetdone (rx_resetdone), + .tx_resetdone (tx_resetdone), + + .gt_b_reset (gt_b_reset & gt_powergood), + .gt_b_reset_rx_datapath (rx_b_reset_datapath), + .gt_b_reset_tx_datapath (tx_b_reset_datapath), + .gt_b_reset_rx_pll_and_datapath (rx_b_reset_pll_and_datapath), + .gt_b_reset_tx_pll_and_datapath (tx_b_reset_pll_and_datapath), + .rx_b_resetdone (rx_b_resetdone), + .tx_b_resetdone (tx_b_resetdone), + + .ref_clk_a (ref_clk), + .ref_clk_b (ref_clk), + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), + .rx_b_device_clk (rx_device_clk), + .tx_b_device_clk (tx_device_clk), + + .data_in_p (hsci_do_p), + .data_in_n (hsci_do_n), + .clk_in_p (hsci_cko_p), + .clk_in_n (hsci_cko_n), + .data_out_p (hsci_din_p), + .data_out_n (hsci_din_n), + .clk_out_p (hsci_ckin_p), + .clk_out_n (hsci_ckin_n), + .intf_rdy (intf_rdy), + .fifo_empty (fifo_empty), + .fifo_rd_en (fifo_rd_en), + .hsci_data_out (hsci_data_out), + .hsci_data_in (hsci_data_in), + .data_from_fabric (data_from_fabric), + .data_to_fabric (data_to_fabric), + + .rx_sync_0 (rx_syncout[0]), + .tx_sync_0 (tx_syncin[0]), + .rx_sync_12 (rx_syncout[1]), + .tx_sync_12 (tx_syncin[1]), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref), + .rx_sysref_12 (sysref), + .tx_sysref_12 (sysref)); + + assign rx_data_p_loc[11:8] = stxb_p[7:4]; + assign rx_data_p_loc[ 7:4] = stxa_p[3:0]; + assign rx_data_p_loc[ 3:0] = stxb_p[3:0]; + assign rx_data_n_loc[11:8] = stxb_n[7:4]; + assign rx_data_n_loc[ 7:4] = stxa_n[3:0]; + assign rx_data_n_loc[ 3:0] = stxb_n[3:0]; + + assign srxb_p[7:4] = tx_data_p_loc[11:8]; + assign srxa_p[3:0] = tx_data_p_loc[ 7:4]; + assign srxb_p[3:0] = tx_data_p_loc[ 3:0]; + assign srxb_n[7:4] = tx_data_n_loc[11:8]; + assign srxa_n[3:0] = tx_data_n_loc[ 7:4]; + assign srxb_n[3:0] = tx_data_n_loc[ 3:0]; + +endmodule diff --git a/projects/ad9084_ebz/vck190/timing_constr.tcl b/projects/ad9084_ebz/vck190/timing_constr.tcl new file mode 100755 index 00000000000..e7a80589472 --- /dev/null +++ b/projects/ad9084_ebz/vck190/timing_constr.tcl @@ -0,0 +1,78 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +# Primary clock definitions + +# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block +# Maximum values for Link clock: +# 204B - 15.5 Gbps /40 = 387.5MHz +# 204C - 24.75 Gbps /66 = 375MHz +set jesd_mode [get_env_param JESD_MODE 64B66B] +set link_mode [expr {$jesd_mode=="64B66B"?2:1}] + +set rx_lane_rate [get_env_param RX_LANE_RATE 20.625] +set tx_lane_rate [get_env_param TX_LANE_RATE 20.625] + +set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] +set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] + +set rx_link_clk_period [expr 1000/$rx_link_clk] +set tx_link_clk_period [expr 1000/$tx_link_clk] + +set rx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_jesd/rx/inst]] +set tx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_jesd/tx/inst]] +set rx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_jesd/rx/inst]] +set tx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_jesd/tx/inst]] + +set rx_device_clk [expr $rx_link_clk*$rx_ll_width/$rx_tpl_width] +set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width] +set rx_device_clk_period [expr 1000/$rx_device_clk] +set tx_device_clk_period [expr 1000/$tx_device_clk] + +set ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0] + +if {$ASYMMETRIC_A_B_MODE} { + set rx_b_lane_rate [get_env_param RX_B_LANE_RATE 20.625] + set tx_b_lane_rate [get_env_param TX_B_LANE_RATE 20.625] + + set rx_b_link_clk [expr $rx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]] + set tx_b_link_clk [expr $tx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]] + + set rx_b_link_clk_period [expr 1000/$rx_b_link_clk] + set tx_b_link_clk_period [expr 1000/$tx_b_link_clk] + + set rx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]] + set tx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]] + set rx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]] + set tx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]] + + set rx_b_device_clk [expr $rx_b_link_clk*$rx_b_ll_width/$rx_b_tpl_width] + set tx_b_device_clk [expr $tx_b_link_clk*$tx_b_ll_width/$tx_b_tpl_width] + set rx_b_device_clk_period [expr 1000/$rx_b_device_clk] + set tx_b_device_clk_period [expr 1000/$tx_b_device_clk] +} + +# refclk and refclk_replica are connect to the same source on the PCB +# Set reference clock to same frequency as the link clock, +# this will ease the XCVR out clocks propagation calculation. +# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE +create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p[0]] + +# device clock +create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clk_m2c_p[0]] +create_clock -name tx_device_clk -period $tx_device_clk_period [get_ports clk_m2c_p[1]] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay -clock [get_clocks rx_device_clk] \ + [get_property PERIOD [get_clocks rx_device_clk]] \ + [get_ports {sysref_in*}] +set_input_delay -clock [get_clocks tx_device_clk] -add_delay\ + [get_property PERIOD [get_clocks tx_device_clk]] \ + [get_ports {sysref_in*}] + +set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous diff --git a/projects/ad9084_ebz/vcu118/Makefile b/projects/ad9084_ebz/vcu118/Makefile new file mode 100755 index 00000000000..16d78ecab6e --- /dev/null +++ b/projects/ad9084_ebz/vcu118/Makefile @@ -0,0 +1,50 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9084_ebz_vcu118 + +M_DEPS += timing_constr.xdc +M_DEPS += ../common/versal_hsci_phy.tcl +M_DEPS += ../common/ad9084_ebz_spi.v +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc +M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl +M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_rst_constr.xdc +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../projects/common/xilinx/data_offload_bd.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hsci +LIB_DEPS += axi_sysid +LIB_DEPS += axi_tdd +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_tdd_sync +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9084_ebz/vcu118/system_bd.tcl b/projects/ad9084_ebz/vcu118/system_bd.tcl new file mode 100755 index 00000000000..962cd219898 --- /dev/null +++ b/projects/ad9084_ebz/vcu118/system_bd.tcl @@ -0,0 +1,177 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +set ASYMMETRIC_A_B_MODE [ expr { [info exists ad_project_params(ASYMMETRIC_A_B_MODE)] \ + ? $ad_project_params(ASYMMETRIC_A_B_MODE) : 0 } ] + +if {$ASYMMETRIC_A_B_MODE == 1} { + ## ADC B Side FIFO depth in samples per converter + set adc_b_fifo_samples_per_converter [expr $ad_project_params(RX_B_KS_PER_CHANNEL)*1024] + ## DAC B Side FIFO depth in samples per converter + set dac_b_fifo_samples_per_converter [expr $ad_project_params(TX_B_KS_PER_CHANNEL)*1024] +} + +source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl + +source $ad_hdl_dir/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2 +ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 + +# Set SPI clock to 100/16 = 6.25 MHz +ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 16 + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +# Parameters for 15.5Gpbs lane rate + +ad_ip_parameter util_apollo_xcvr CONFIG.RX_CLK25_DIV 31 +ad_ip_parameter util_apollo_xcvr CONFIG.TX_CLK25_DIV 31 +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_CFG0 0x1fa +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_CFG1 0x2b +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_CFG2 0x2 +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_apollo_xcvr CONFIG.CH_HSPMUX 0x4040 +ad_ip_parameter util_apollo_xcvr CONFIG.PREIQ_FREQ_BST 1 +ad_ip_parameter util_apollo_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 +ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG0 0x3002 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG2 0x1E9 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3 0x23 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN2 0x23 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN3 0x23 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN4 0x23 +ad_ip_parameter util_apollo_xcvr CONFIG.RX_WIDEMODE_CDR 0x1 +ad_ip_parameter util_apollo_xcvr CONFIG.RX_XMODE_SEL 0x0 +ad_ip_parameter util_apollo_xcvr CONFIG.TXDRV_FREQBAND 1 +ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG1 0xAA00 +ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG2 0xAA00 +ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG3 0xAA00 +ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG0 0x3100 +ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG1 0x0 +ad_ip_parameter util_apollo_xcvr CONFIG.TX_PI_BIASSET 1 +ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG1 0x54 + +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG0 0x333c +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG4 0x2 +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_apollo_xcvr CONFIG.PPF0_CFG 0xB00 +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_LPF 0x2ff + +# 204C params 16.5Gbps..24.75Gpbs +if {$ad_project_params(JESD_MODE) == "64B66B"} { + + # Set higher swing for the diff driver, other case 16.5Gbps won't work + ad_ip_parameter axi_apollo_tx_xcvr CONFIG.TX_DIFFCTRL 0xC + + # Lane rate indepentent parameters + ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12 + ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12 + ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 + ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG1 0x0 + ad_ip_parameter util_apollo_xcvr CONFIG.RX_WIDEMODE_CDR 0x2 + ad_ip_parameter util_apollo_xcvr CONFIG.CH_HSPMUX 0x6060 + ad_ip_parameter util_apollo_xcvr CONFIG.PREIQ_FREQ_BST 2 + ad_ip_parameter util_apollo_xcvr CONFIG.TX_PI_BIASSET 2 + ad_ip_parameter util_apollo_xcvr CONFIG.RXDFE_KH_CFG2 0x281C + ad_ip_parameter util_apollo_xcvr CONFIG.RXDFE_KH_CFG3 0x4120 + + # Lane rate indepentent QPLL parameters + ad_ip_parameter util_apollo_xcvr CONFIG.PPF0_CFG 0x600 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG0 0x331c + + # Lane rate dependent QPLL params (these match for 16.5 Gbps and 24.75 Gpbs) + ad_ip_parameter util_apollo_xcvr CONFIG.PPF1_CFG 0x400 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_LPF 0x33f + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG2 0x0FC1 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG2_G3 0x0FC1 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG4 0x03 + + # set dividers for 24.75Gbps, are overwritten by software + ad_ip_parameter util_apollo_xcvr CONFIG.RX_CLK25_DIV 10 + ad_ip_parameter util_apollo_xcvr CONFIG.TX_CLK25_DIV 10 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_FBDIV 66 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_REFCLK_DIV 2 + + set RX_LANE_RATE $ad_project_params(RX_LANE_RATE) + set TX_LANE_RATE $ad_project_params(TX_LANE_RATE) + + if {$ASYMMETRIC_A_B_MODE} { + set RX_LANE_RATE [expr max($ad_project_params(RX_B_LANE_RATE), $RX_LANE_RATE)] + set TX_LANE_RATE [expr max($ad_project_params(TX_B_LANE_RATE), $TX_LANE_RATE)] + } + + if {$RX_LANE_RATE < 20} { + ad_ip_parameter util_apollo_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 + ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG0 0x0104 + } else { + ad_ip_parameter util_apollo_xcvr CONFIG.RTX_BUF_CML_CTRL 0x6 + ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG0 0x3004 + } + + if {$TX_LANE_RATE < 20} { + ad_ip_parameter util_apollo_xcvr CONFIG.TXDRV_FREQBAND 1 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG0 0x3C2 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG1 0xAA00 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG2 0xAA00 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG3 0xAA00 + ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG0 0x0100 + ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG1 0x1000 + ad_ip_parameter util_apollo_xcvr CONFIG.TXSWBST_EN 0 + } else { + ad_ip_parameter util_apollo_xcvr CONFIG.TXDRV_FREQBAND 3 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG0 0x3C6 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG1 0xF800 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG2 0xF800 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG3 0xF800 + ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG0 0x3000 + ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG1 0x0 + ad_ip_parameter util_apollo_xcvr CONFIG.TXSWBST_EN 1 + } + +} + +# Second SPI controller +create_bd_port -dir O -from 7 -to 0 apollo_spi_csn_o +create_bd_port -dir I -from 7 -to 0 apollo_spi_csn_i +create_bd_port -dir I apollo_spi_clk_i +create_bd_port -dir O apollo_spi_clk_o +create_bd_port -dir I apollo_spi_sdo_i +create_bd_port -dir O apollo_spi_sdo_o +create_bd_port -dir I apollo_spi_sdi_i + +ad_ip_instance axi_quad_spi axi_spi_2 +ad_ip_parameter axi_spi_2 CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_2 CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi_2 CONFIG.C_SCK_RATIO 16 + +ad_connect apollo_spi_csn_i axi_spi_2/ss_i +ad_connect apollo_spi_csn_o axi_spi_2/ss_o +ad_connect apollo_spi_clk_i axi_spi_2/sck_i +ad_connect apollo_spi_clk_o axi_spi_2/sck_o +ad_connect apollo_spi_sdo_i axi_spi_2/io0_i +ad_connect apollo_spi_sdo_o axi_spi_2/io0_o +ad_connect apollo_spi_sdi_i axi_spi_2/io1_i + +ad_connect sys_cpu_clk axi_spi_2/ext_spi_clk + +ad_cpu_interrupt ps-0 mb-16 axi_spi_2/ip2intc_irpt + +ad_cpu_interconnect 0x44A80000 axi_spi_2 + +set_property range 256K [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_hsci_0}] diff --git a/projects/ad9084_ebz/vcu118/system_constr.xdc b/projects/ad9084_ebz/vcu118/system_constr.xdc new file mode 100755 index 00000000000..5c328ffde21 --- /dev/null +++ b/projects/ad9084_ebz/vcu118/system_constr.xdc @@ -0,0 +1,198 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# +## Apollo +# + +set_property -dict {PACKAGE_PIN T42 } [get_ports srxa_p[5] ] ; ## MGTYTXP0_126 +set_property -dict {PACKAGE_PIN T43 } [get_ports srxa_n[5] ] ; ## MGTYTXN0_126 +set_property -dict {PACKAGE_PIN P42 } [get_ports srxa_p[1] ] ; ## MGTYTXP1_126 +set_property -dict {PACKAGE_PIN P43 } [get_ports srxa_n[1] ] ; ## MGTYTXN1_126 +set_property -dict {PACKAGE_PIN K42 } [get_ports srxa_p[7] ] ; ## MGTYTXP3_126 +set_property -dict {PACKAGE_PIN K43 } [get_ports srxa_n[7] ] ; ## MGTYTXN3_126 +set_property -dict {PACKAGE_PIN M42 } [get_ports srxa_p[3] ] ; ## MGTYTXP2_126 +set_property -dict {PACKAGE_PIN M43 } [get_ports srxa_n[3] ] ; ## MGTYTXN2_126 +set_property -dict {PACKAGE_PIN W40 } [get_ports srxa_p[9] ] ; ## MGTYTXP2_125 +set_property -dict {PACKAGE_PIN W41 } [get_ports srxa_n[9] ] ; ## MGTYTXN2_125 +set_property -dict {PACKAGE_PIN U40 } [get_ports srxa_p[11] ] ; ## MGTYTXP3_125 +set_property -dict {PACKAGE_PIN U41 } [get_ports srxa_n[11] ] ; ## MGTYTXN3_125 +set_property -dict {PACKAGE_PIN H42 } [get_ports srxa_p[4] ] ; ## MGTYTXP0_127 +set_property -dict {PACKAGE_PIN H43 } [get_ports srxa_n[4] ] ; ## MGTYTXN0_127 +set_property -dict {PACKAGE_PIN F42 } [get_ports srxa_p[6] ] ; ## MGTYTXP1_127 +set_property -dict {PACKAGE_PIN F43 } [get_ports srxa_n[6] ] ; ## MGTYTXN1_127 +set_property -dict {PACKAGE_PIN D42 } [get_ports srxa_p[2] ] ; ## MGTYTXP2_127 +set_property -dict {PACKAGE_PIN D43 } [get_ports srxa_n[2] ] ; ## MGTYTXN2_127 +set_property -dict {PACKAGE_PIN B42 } [get_ports srxa_p[0] ] ; ## MGTYTXP3_127 +set_property -dict {PACKAGE_PIN B43 } [get_ports srxa_n[0] ] ; ## MGTYTXN3_127 +set_property -dict {PACKAGE_PIN AA40 } [get_ports srxa_p[8] ] ; ## MGTYTXP1_125 +set_property -dict {PACKAGE_PIN AA41 } [get_ports srxa_n[8] ] ; ## MGTYTXN1_125 +set_property -dict {PACKAGE_PIN AC40 } [get_ports srxa_p[10] ] ; ## MGTYTXP0_125 +set_property -dict {PACKAGE_PIN AC41 } [get_ports srxa_n[10] ] ; ## MGTYTXN0_125 + +set_property -dict {PACKAGE_PIN AP42 } [get_ports srxb_p[7] ] ; ## MGTYTXP1_121 +set_property -dict {PACKAGE_PIN AP43 } [get_ports srxb_n[7] ] ; ## MGTYTXN1_121 +set_property -dict {PACKAGE_PIN AM42 } [get_ports srxb_p[10] ] ; ## MGTYTXP2_121 +set_property -dict {PACKAGE_PIN AM43 } [get_ports srxb_n[10] ] ; ## MGTYTXN2_121 +set_property -dict {PACKAGE_PIN AL40 } [get_ports srxb_p[3] ] ; ## MGTYTXP3_121 +set_property -dict {PACKAGE_PIN AL41 } [get_ports srxb_n[3] ] ; ## MGTYTXN3_121 +set_property -dict {PACKAGE_PIN AJ40 } [get_ports srxb_p[8] ] ; ## MGTYTXP1_122 +set_property -dict {PACKAGE_PIN AJ41 } [get_ports srxb_n[8] ] ; ## MGTYTXN1_122 +set_property -dict {PACKAGE_PIN AK42 } [get_ports srxb_p[5] ] ; ## MGTYTXP0_122 +set_property -dict {PACKAGE_PIN AK43 } [get_ports srxb_n[5] ] ; ## MGTYTXN0_122 +set_property -dict {PACKAGE_PIN AT42 } [get_ports srxb_p[1] ] ; ## MGTYTXP0_121 +set_property -dict {PACKAGE_PIN AT43 } [get_ports srxb_n[1] ] ; ## MGTYTXN0_121 +set_property -dict {PACKAGE_PIN AV42 } [get_ports srxb_p[0] ] ; ## MGTYTXP3_120 +set_property -dict {PACKAGE_PIN AV43 } [get_ports srxb_n[0] ] ; ## MGTYTXN3_120 +set_property -dict {PACKAGE_PIN BB42 } [get_ports srxb_p[6] ] ; ## MGTYTXP1_120 +set_property -dict {PACKAGE_PIN BB43 } [get_ports srxb_n[6] ] ; ## MGTYTXN1_120 +set_property -dict {PACKAGE_PIN AE40 } [get_ports srxb_p[11] ] ; ## MGTYTXP3_122 +set_property -dict {PACKAGE_PIN AE41 } [get_ports srxb_n[11] ] ; ## MGTYTXN3_122 +set_property -dict {PACKAGE_PIN AY42 } [get_ports srxb_p[2] ] ; ## MGTYTXP2_120 +set_property -dict {PACKAGE_PIN AY43 } [get_ports srxb_n[2] ] ; ## MGTYTXN2_120 +set_property -dict {PACKAGE_PIN BD42 } [get_ports srxb_p[4] ] ; ## MGTYTXP0_120 +set_property -dict {PACKAGE_PIN BD43 } [get_ports srxb_n[4] ] ; ## MGTYTXN0_120 +set_property -dict {PACKAGE_PIN AG40 } [get_ports srxb_p[9] ] ; ## MGTYTXP2_122 +set_property -dict {PACKAGE_PIN AG41 } [get_ports srxb_n[9] ] ; ## MGTYTXN2_122 + +set_property -dict {PACKAGE_PIN W45 } [get_ports stxa_p[11] ] ; ## MGTYRXP0_126 +set_property -dict {PACKAGE_PIN W46 } [get_ports stxa_n[11] ] ; ## MGTYRXN0_126 +set_property -dict {PACKAGE_PIN U45 } [get_ports stxa_p[3] ] ; ## MGTYRXP1_126 +set_property -dict {PACKAGE_PIN U46 } [get_ports stxa_n[3] ] ; ## MGTYRXN1_126 +set_property -dict {PACKAGE_PIN N45 } [get_ports stxa_p[9] ] ; ## MGTYRXP3_126 +set_property -dict {PACKAGE_PIN N46 } [get_ports stxa_n[9] ] ; ## MGTYRXN3_126 +set_property -dict {PACKAGE_PIN R45 } [get_ports stxa_p[8] ] ; ## MGTYRXP2_126 +set_property -dict {PACKAGE_PIN R46 } [get_ports stxa_n[8] ] ; ## MGTYRXN2_126 +set_property -dict {PACKAGE_PIN AC45 } [get_ports stxa_p[7] ] ; ## MGTYRXP0_125 +set_property -dict {PACKAGE_PIN AC46 } [get_ports stxa_n[7] ] ; ## MGTYRXN0_125 +set_property -dict {PACKAGE_PIN AA45 } [get_ports stxa_p[1] ] ; ## MGTYRXP2_125 +set_property -dict {PACKAGE_PIN AA46 } [get_ports stxa_n[1] ] ; ## MGTYRXN2_125 +set_property -dict {PACKAGE_PIN Y43 } [get_ports stxa_p[2] ] ; ## MGTYRXP3_125 +set_property -dict {PACKAGE_PIN Y44 } [get_ports stxa_n[2] ] ; ## MGTYRXN3_125 +set_property -dict {PACKAGE_PIN J45 } [get_ports stxa_p[6] ] ; ## MGTYRXP1_127 +set_property -dict {PACKAGE_PIN J46 } [get_ports stxa_n[6] ] ; ## MGTYRXN1_127 +set_property -dict {PACKAGE_PIN E45 } [get_ports stxa_p[0] ] ; ## MGTYRXP3_127 +set_property -dict {PACKAGE_PIN E46 } [get_ports stxa_n[0] ] ; ## MGTYRXN3_127 +set_property -dict {PACKAGE_PIN AB43 } [get_ports stxa_p[5] ] ; ## MGTYRXP1_125 +set_property -dict {PACKAGE_PIN AB44 } [get_ports stxa_n[5] ] ; ## MGTYRXN1_125 +set_property -dict {PACKAGE_PIN L45 } [get_ports stxa_p[10] ] ; ## MGTYRXP0_127 +set_property -dict {PACKAGE_PIN L46 } [get_ports stxa_n[10] ] ; ## MGTYRXN0_127 +set_property -dict {PACKAGE_PIN G45 } [get_ports stxa_p[4] ] ; ## MGTYRXP2_127 +set_property -dict {PACKAGE_PIN G46 } [get_ports stxa_n[4] ] ; ## MGTYRXN2_127 + +set_property -dict {PACKAGE_PIN AN45 } [get_ports stxb_p[2] ] ; ## MGTYRXP1_121 +set_property -dict {PACKAGE_PIN AN46 } [get_ports stxb_n[2] ] ; ## MGTYRXN1_121 +set_property -dict {PACKAGE_PIN AL45 } [get_ports stxb_p[5] ] ; ## MGTYRXP2_121 +set_property -dict {PACKAGE_PIN AL46 } [get_ports stxb_n[5] ] ; ## MGTYRXN2_121 +set_property -dict {PACKAGE_PIN AJ45 } [get_ports stxb_p[7] ] ; ## MGTYRXP3_121 +set_property -dict {PACKAGE_PIN AJ46 } [get_ports stxb_n[7] ] ; ## MGTYRXN3_121 +set_property -dict {PACKAGE_PIN AF43 } [get_ports stxb_p[1] ] ; ## MGTYRXP1_122 +set_property -dict {PACKAGE_PIN AF44 } [get_ports stxb_n[1] ] ; ## MGTYRXN1_122 +set_property -dict {PACKAGE_PIN AG45 } [get_ports stxb_p[8] ] ; ## MGTYRXP0_122 +set_property -dict {PACKAGE_PIN AG46 } [get_ports stxb_n[8] ] ; ## MGTYRXN0_122 +set_property -dict {PACKAGE_PIN AR45 } [get_ports stxb_p[3] ] ; ## MGTYRXP0_121 +set_property -dict {PACKAGE_PIN AR46 } [get_ports stxb_n[3] ] ; ## MGTYRXN0_121 +set_property -dict {PACKAGE_PIN AU45 } [get_ports stxb_p[0] ] ; ## MGTYRXP3_120 +set_property -dict {PACKAGE_PIN AU46 } [get_ports stxb_n[0] ] ; ## MGTYRXN3_120 +set_property -dict {PACKAGE_PIN AW45 } [get_ports stxb_p[4] ] ; ## MGTYRXP2_120 +set_property -dict {PACKAGE_PIN AW46 } [get_ports stxb_n[4] ] ; ## MGTYRXN2_120 +set_property -dict {PACKAGE_PIN BA45 } [get_ports stxb_p[6] ] ; ## MGTYRXP1_120 +set_property -dict {PACKAGE_PIN BA46 } [get_ports stxb_n[6] ] ; ## MGTYRXN1_120 +set_property -dict {PACKAGE_PIN BC45 } [get_ports stxb_p[10] ] ; ## MGTYRXP0_120 +set_property -dict {PACKAGE_PIN BC46 } [get_ports stxb_n[10] ] ; ## MGTYRXN0_120 +set_property -dict {PACKAGE_PIN AE45 } [get_ports stxb_p[11] ] ; ## MGTYRXP2_122 +set_property -dict {PACKAGE_PIN AE46 } [get_ports stxb_n[11] ] ; ## MGTYRXN2_122 +set_property -dict {PACKAGE_PIN AD43 } [get_ports stxb_p[9] ] ; ## MGTYRXP3_122 +set_property -dict {PACKAGE_PIN AD44 } [get_ports stxb_n[9] ] ; ## MGTYRXN3_122 + +set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 } [get_ports gpio[15] ] ; ## IO_L2P_T0L_N2_43 +set_property -dict {PACKAGE_PIN AT36 IOSTANDARD LVCMOS18 } [get_ports gpio[16] ] ; ## IO_L2N_T0L_N3_43 +set_property -dict {PACKAGE_PIN AG31 IOSTANDARD LVCMOS18 } [get_ports gpio[23] ] ; ## IO_L23P_T3U_N8_43 +set_property -dict {PACKAGE_PIN AH31 IOSTANDARD LVCMOS18 } [get_ports gpio[24] ] ; ## IO_L23N_T3U_N9_43 +set_property -dict {PACKAGE_PIN R31 IOSTANDARD LVCMOS18 } [get_ports gpio[27] ] ; ## IO_L10P_T1U_N6_QBC_AD4P_45 +set_property -dict {PACKAGE_PIN P31 IOSTANDARD LVCMOS18 } [get_ports gpio[28] ] ; ## IO_L10N_T1U_N7_QBC_AD4N_45 +set_property -dict {PACKAGE_PIN AH33 IOSTANDARD LVCMOS18 } [get_ports gpio[21] ] ; ## IO_L21P_T3L_N4_AD8P_43 +set_property -dict {PACKAGE_PIN AH34 IOSTANDARD LVCMOS18 } [get_ports gpio[22] ] ; ## IO_L21N_T3L_N5_AD8N_43 +set_property -dict {PACKAGE_PIN AP36 IOSTANDARD LVCMOS18 } [get_ports gpio[17] ] ; ## IO_L5P_T0U_N8_AD14P_43 +set_property -dict {PACKAGE_PIN AP37 IOSTANDARD LVCMOS18 } [get_ports gpio[18] ] ; ## IO_L5N_T0U_N9_AD14N_43 +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports gpio[19] ] ; ## IO_L17P_T2U_N8_AD10P_43 +set_property -dict {PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports gpio[20] ] ; ## IO_L17N_T2U_N9_AD10N_43 +set_property -dict {PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports gpio[25] ] ; ## IO_L24P_T3U_N10_43 +set_property -dict {PACKAGE_PIN AG33 IOSTANDARD LVCMOS18 } [get_ports gpio[26] ] ; ## IO_L24N_T3U_N11_43 +set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVCMOS18 } [get_ports gpio[29] ] ; ## IO_L22P_T3U_N6_DBC_AD0P_45 +set_property -dict {PACKAGE_PIN M33 IOSTANDARD LVCMOS18 } [get_ports gpio[30] ] ; ## IO_L22N_T3U_N7_DBC_AD0N_45 +set_property -dict {PACKAGE_PIN K33 IOSTANDARD LVCMOS18 } [get_ports aux_gpio ] ; ## IO_L21N_T3L_N5_AD8N_45 + +set_property -dict {PACKAGE_PIN N32 IOSTANDARD LVCMOS18 } [get_ports syncinb_a1_p_gpio ] ; ## IO_L23P_T3U_N8_45 +set_property -dict {PACKAGE_PIN M32 IOSTANDARD LVCMOS18 } [get_ports syncinb_a1_n_gpio ] ; ## IO_L23N_T3U_N9_45 +set_property -dict {PACKAGE_PIN N34 IOSTANDARD LVCMOS18 } [get_ports syncinb_b1_p_gpio ] ; ## IO_L20P_T3L_N2_AD1P_45 +set_property -dict {PACKAGE_PIN N35 IOSTANDARD LVCMOS18 } [get_ports syncinb_b1_n_gpio ] ; ## IO_L20N_T3L_N3_AD1N_45 +set_property -dict {PACKAGE_PIN M35 IOSTANDARD LVCMOS18 } [get_ports syncoutb_a1_p_gpio ] ; ## IO_L24P_T3U_N10_45 +set_property -dict {PACKAGE_PIN L35 IOSTANDARD LVCMOS18 } [get_ports syncoutb_a1_n_gpio ] ; ## IO_L24N_T3U_N11_45 +set_property -dict {PACKAGE_PIN Y32 IOSTANDARD LVCMOS18 } [get_ports syncoutb_b1_p_gpio ] ; ## IO_L1P_T0L_N0_DBC_45 +set_property -dict {PACKAGE_PIN W32 IOSTANDARD LVCMOS18 } [get_ports syncoutb_b1_n_gpio ] ; ## IO_L1N_T0L_N1_DBC_45 + +set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVDS } [get_ports syncinb_a0_p ] ; ## IO_L6P_T0U_N10_AD6P_43 +set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVDS } [get_ports syncinb_a0_n ] ; ## IO_L6N_T0U_N11_AD6N_43 +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVDS } [get_ports syncinb_b0_p ] ; ## IO_L18P_T2U_N10_AD2P_43 +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS } [get_ports syncinb_b0_n ] ; ## IO_L18N_T2U_N11_AD2N_43 +set_property -dict {PACKAGE_PIN AP38 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_a0_p ] ; ## IO_L1P_T0L_N0_DBC_43 +set_property -dict {PACKAGE_PIN AR38 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_a0_n ] ; ## IO_L1N_T0L_N1_DBC_43 +set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_b0_p ] ; ## IO_L19P_T3L_N0_DBC_AD9P_43 +set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_b0_n ] ; ## IO_L19N_T3L_N1_DBC_AD9N_43 + +set_property -dict {PACKAGE_PIN AK38 } [get_ports ref_clk_p[0] ] ; ## MGTREFCLK0P_121 +set_property -dict {PACKAGE_PIN AK39 } [get_ports ref_clk_n[0] ] ; ## MGTREFCLK0N_121 +set_property -dict {PACKAGE_PIN AM38 } [get_ports ref_clk_p[1] ] ; ## MGTREFCLK1P_120,121,122,125,126,127 +set_property -dict {PACKAGE_PIN AM39 } [get_ports ref_clk_n[1] ] ; ## MGTREFCLK1N_120,121,122,125,126,127 +set_property -dict {PACKAGE_PIN AF38 } [get_ports ref_clk_p[2] ] ; ## MGTREFCLK0P_122 +set_property -dict {PACKAGE_PIN AF39 } [get_ports ref_clk_n[2] ] ; ## MGTREFCLK0N_122 +set_property -dict {PACKAGE_PIN V38 } [get_ports ref_clk_replica_p ] ; ## MGTREFCLK0P_126 +set_property -dict {PACKAGE_PIN V39 } [get_ports ref_clk_replica_n ] ; ## MGTREFCLK0N_126 + +set_property -dict {PACKAGE_PIN AG34 IOSTANDARD LVDS } [get_ports sysref_a_p ] ; ## IO_L22P_T3U_N6_DBC_AD0P_43 +set_property -dict {PACKAGE_PIN AH35 IOSTANDARD LVDS } [get_ports sysref_a_n ] ; ## IO_L22N_T3U_N7_DBC_AD0N_43 +set_property -dict {PACKAGE_PIN R34 IOSTANDARD LVDS } [get_ports sysref_b_p ] ; ## IO_L13P_T2L_N0_GC_QBC_45 +set_property -dict {PACKAGE_PIN P34 IOSTANDARD LVDS } [get_ports sysref_b_n ] ; ## IO_L13N_T2L_N1_GC_QBC_45 +set_property -dict {PACKAGE_PIN AL35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports sysref_p ] ; ## IO_L7P_T1L_N0_QBC_AD13P_43 +set_property -dict {PACKAGE_PIN AL36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports sysref_n ] ; ## IO_L7N_T1L_N1_QBC_AD13N_43 +set_property -dict {PACKAGE_PIN L34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports sysref_in_p ] ; ## IO_L19P_T3L_N0_DBC_AD9P_45 +set_property -dict {PACKAGE_PIN K34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports sysref_in_n ] ; ## IO_L19N_T3L_N1_DBC_AD9N_45 + +set_property -dict {PACKAGE_PIN T34 IOSTANDARD LVCMOS18 } [get_ports spi2_sclk ] ; ## IO_L6P_T0U_N10_AD6P_45 +set_property -dict {PACKAGE_PIN T35 IOSTANDARD LVCMOS18 } [get_ports spi2_sdio ] ; ## IO_L6N_T0U_N11_AD6N_45 +set_property -dict {PACKAGE_PIN V32 IOSTANDARD LVCMOS18 } [get_ports spi2_sdo ] ; ## IO_L2P_T0L_N2_45 +set_property -dict {PACKAGE_PIN U33 IOSTANDARD LVCMOS18 } [get_ports spi2_cs[0] ] ; ## IO_L2N_T0L_N3_45 +set_property -dict {PACKAGE_PIN U35 IOSTANDARD LVCMOS18 } [get_ports spi2_cs[1] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_45 +set_property -dict {PACKAGE_PIN T36 IOSTANDARD LVCMOS18 } [get_ports spi2_cs[2] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_45 +set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18 } [get_ports spi2_cs[3] ] ; ## IO_L18P_T2U_N10_AD2P_45 +set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18 } [get_ports spi2_cs[4] ] ; ## IO_L18N_T2U_N11_AD2N_45 +set_property -dict {PACKAGE_PIN L33 IOSTANDARD LVCMOS18 } [get_ports spi2_cs[5] ] ; ## IO_L21P_T3L_N4_AD8P_45 + +set_property -dict {PACKAGE_PIN AT39 IOSTANDARD LVCMOS18 } [get_ports dut_sdio ] ; ## IO_L4P_T0U_N6_DBC_AD7P_43 +set_property -dict {PACKAGE_PIN AT40 IOSTANDARD LVCMOS18 } [get_ports dut_sdo ] ; ## IO_L4N_T0U_N7_DBC_AD7N_43 +set_property -dict {PACKAGE_PIN AJ32 IOSTANDARD LVCMOS18 } [get_ports dut_sclk ] ; ## IO_L14P_T2L_N2_GC_43 +set_property -dict {PACKAGE_PIN AK32 IOSTANDARD LVCMOS18 } [get_ports dut_csb ] ; ## IO_L14N_T2L_N3_GC_43 + +set_property -dict {PACKAGE_PIN AL32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_p[0] ] ; ## IO_L13P_T2L_N0_GC_QBC_43 +set_property -dict {PACKAGE_PIN AM32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_n[0] ] ; ## IO_L13N_T2L_N1_GC_QBC_43 +set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_p[1] ] ; ## IO_L14P_T2L_N2_GC_45 +set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_n[1] ] ; ## IO_L14N_T2L_N3_GC_45 + +set_property -dict {PACKAGE_PIN V33 IOSTANDARD LVDS } [get_ports hsci_ckin_p ] ; ## IO_L5P_T0U_N8_AD14P_45 +set_property -dict {PACKAGE_PIN V34 IOSTANDARD LVDS } [get_ports hsci_ckin_n ] ; ## IO_L5N_T0U_N9_AD14N_45 +set_property -dict {PACKAGE_PIN Y34 IOSTANDARD LVDS } [get_ports hsci_din_p ] ; ## IO_L3P_T0L_N4_AD15P_45 +set_property -dict {PACKAGE_PIN W34 IOSTANDARD LVDS } [get_ports hsci_din_n ] ; ## IO_L3N_T0L_N5_AD15N_45 +set_property -dict {PACKAGE_PIN P37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_p ] ; ## IO_L16P_T2U_N6_QBC_AD3P_45 +set_property -dict {PACKAGE_PIN N37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_n ] ; ## IO_L16N_T2U_N7_QBC_AD3N_45 +set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_p ] ; ## IO_L17P_T2U_N8_AD10P_45 +set_property -dict {PACKAGE_PIN L36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_n ] ; ## IO_L17N_T2U_N9_AD10N_45 + +set_property -dict {PACKAGE_PIN AP35 IOSTANDARD LVCMOS18 } [get_ports trig_a[0] ] ; ## IO_L3P_T0L_N4_AD15P_43 +set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18 } [get_ports trig_a[1] ] ; ## IO_L3N_T0L_N5_AD15N_43 +set_property -dict {PACKAGE_PIN AJ35 IOSTANDARD LVCMOS18 } [get_ports trig_b[0] ] ; ## IO_L20P_T3L_N2_AD1P_43 +set_property -dict {PACKAGE_PIN AJ36 IOSTANDARD LVCMOS18 } [get_ports trig_b[1] ] ; ## IO_L20N_T3L_N3_AD1N_43 +set_property -dict {PACKAGE_PIN AL31 IOSTANDARD LVCMOS18 } [get_ports trig_in ] ; ## IO_L16N_T2U_N7_QBC_AD3N_43 +set_property -dict {PACKAGE_PIN AL30 IOSTANDARD LVCMOS18 } [get_ports resetb ] ; ## IO_L16P_T2U_N6_QBC_AD3P_43 diff --git a/projects/ad9084_ebz/vcu118/system_project.tcl b/projects/ad9084_ebz/vcu118/system_project.tcl new file mode 100755 index 00000000000..0ca801cecc6 --- /dev/null +++ b/projects/ad9084_ebz/vcu118/system_project.tcl @@ -0,0 +1,99 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../../projects/scripts/adi_project_xilinx.tcl +source ../../../projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# ID=11+ make JESD_MODE=64B66B RX_LANE_RATE=26.4 TX_LANE_RATE=26.4 RX_B_LANE_RATE=26.4 TX_B_LANE_RATE=26.4 +# ID=47 make JESD_MODE=64B66B RX_LANE_RATE=10.3125 TX_LANE_RATE=10.3125 RX_JESD_M=4 TX_JESD_M=4 RX_JESD_L=8 TX_JESD_L=8 RX_JESD_S=1 TX_JESD_S=1 RX_JESD_NP=16 TX_JESD_NP=16 RX_B_LANE_RATE=10.3125 TX_B_LANE_RATE=10.3125 RX_B_JESD_M=4 TX_B_JESD_M=4 RX_B_JESD_L=8 TX_B_JESD_L=8 RX_B_JESD_S=1 TX_B_JESD_S=1 RX_B_JESD_NP=16 TX_B_JESD_NP=16 +# ID=47+ make JESD_MODE=64B66B RX_LANE_RATE=20.6250 TX_LANE_RATE=20.6250 RX_JESD_M=4 TX_JESD_M=4 RX_JESD_L=8 TX_JESD_L=8 RX_JESD_S=1 TX_JESD_S=1 RX_JESD_NP=16 TX_JESD_NP=16 RX_B_LANE_RATE=20.6250 TX_B_LANE_RATE=20.625 RX_B_JESD_M=4 TX_B_JESD_M=4 RX_B_JESD_L=8 TX_B_JESD_L=8 RX_B_JESD_S=1 TX_B_JESD_S=1 RX_B_JESD_NP=16 TX_B_JESD_NP=16 +# ID=68 make JESD_MODE=64B66B RX_LANE_RATE=20.6250 TX_LANE_RATE=20.6250 RX_JESD_M=1 TX_JESD_M=1 RX_JESD_L=12 TX_JESD_L=12 RX_JESD_S=8 TX_JESD_S=8 RX_JESD_NP=12 TX_JESD_NP=12 RX_B_LANE_RATE=20.6250 TX_B_LANE_RATE=20.625 RX_B_JESD_M=1 TX_B_JESD_M=1 RX_B_JESD_L=12 TX_B_JESD_L=12 RX_B_JESD_S=8 TX_B_JESD_S=8 RX_B_JESD_NP=12 TX_B_JESD_NP=12 + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C +# 8B10B - 8b10b link layer defined in JESD 204B +# +# RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample +# [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 +# [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) +# ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link +# RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side +# TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side +# [RX/TX]_B_JESD_M : Number of converters per link for B side +# [RX/TX]_B_JESD_L : Number of lanes per link for B side +# [RX/TX]_B_JESD_NP : Number of bits per sample for B side +# [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side +# + +adi_project ad9084_ebz_vcu118 0 [list \ + JESD_MODE [get_env_param JESD_MODE 64B66B ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 20.625 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 20.625 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 8 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 8 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 32 ] \ + ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 1 ] \ + RX_B_LANE_RATE [get_env_param RX_B_LANE_RATE 20.625 ] \ + TX_B_LANE_RATE [get_env_param TX_B_LANE_RATE 20.625 ] \ + RX_B_JESD_M [get_env_param RX_B_JESD_M 4 ] \ + RX_B_JESD_L [get_env_param RX_B_JESD_L 8 ] \ + RX_B_JESD_S [get_env_param RX_B_JESD_S 1 ] \ + RX_B_JESD_NP [get_env_param RX_B_JESD_NP 16 ] \ + TX_B_JESD_M [get_env_param TX_B_JESD_M 4 ] \ + TX_B_JESD_L [get_env_param TX_B_JESD_L 8 ] \ + TX_B_JESD_S [get_env_param TX_B_JESD_S 1 ] \ + TX_B_JESD_NP [get_env_param TX_B_JESD_NP 16 ] \ + RX_B_KS_PER_CHANNEL [get_env_param RX_B_KS_PER_CHANNEL 32 ] \ + TX_B_KS_PER_CHANNEL [get_env_param TX_B_KS_PER_CHANNEL 32 ] \ +] + +adi_project_files ad9084_ebz_vcu118 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "timing_constr.xdc"\ + "../common/hsci_phy_top.sv"\ + "../common/ad9084_ebz_spi.v"\ + "$ad_hdl_dir/library/common/ad_rst.v"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc"\ + "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ] +create_ip -name high_speed_selectio_wiz -vendor xilinx.com -library ip -version 3.6 -module_name high_speed_selectio_wiz_0 +set_property -dict [list CONFIG.PLL_LOCS {PLL_X0Y12 PLL_X0Y13} CONFIG.BUS_DIR {3} CONFIG.FIFO_RD_EN_CONTROL {1} CONFIG.PLL0_DATA_SPEED {1600} CONFIG.PLL0_INPUT_CLK_FREQ {200.000} CONFIG.PLL0_RX_EXTERNAL_CLK_TO_DATA {3} CONFIG.PLL0_PLLOUT0 {200.000} CONFIG.RIU_FROM_PLL {1} CONFIG.PLL0_CLK_SOURCE {BUFG_TO_PLL} CONFIG.BANK {45_(HP)} CONFIG.DIFFERENTIAL_IO_STD {LVDS} CONFIG.TX_PRE_EMPHASIS_D {FALSE} CONFIG.ENABLE_PLL_DRP_PORTS {0} CONFIG.ENABLE_N_PINS {0} CONFIG.BYTE0_PIN4_SIGNAL_NAME {data_out_p} CONFIG.BYTE0_PIN5_SIGNAL_NAME {data_out_n} CONFIG.BYTE0_PIN8_SIGNAL_NAME {clk_out_p} CONFIG.BYTE0_PIN9_SIGNAL_NAME {clk_out_n} CONFIG.BYTE0_PIN0_LOC {Y32} CONFIG.BYTE0_PIN1_LOC {W32} CONFIG.BYTE0_PIN2_LOC {V32} CONFIG.BYTE0_PIN3_LOC {U33} CONFIG.BYTE0_PIN4_LOC {Y34} CONFIG.BYTE0_PIN5_LOC {W34} CONFIG.BYTE0_PIN6_LOC {U35} CONFIG.BYTE0_PIN7_LOC {T36} CONFIG.BYTE0_PIN8_LOC {V33} CONFIG.BYTE0_PIN9_LOC {V34} CONFIG.BYTE0_PIN10_LOC {T34} CONFIG.BYTE0_PIN11_LOC {T35} CONFIG.BYTE0_PIN12_LOC {Y33} CONFIG.BYTE0_PIN0_NAME {IO_L1P_T0L_N0_DBC_45} CONFIG.BYTE0_PIN1_NAME {IO_L1N_T0L_N1_DBC_45} CONFIG.BYTE0_PIN2_NAME {IO_L2P_T0L_N2_45} CONFIG.BYTE0_PIN3_NAME {IO_L2N_T0L_N3_45} CONFIG.BYTE0_PIN4_NAME {IO_L3P_T0L_N4_AD15P_45} CONFIG.BYTE0_PIN5_NAME {IO_L3N_T0L_N5_AD15N_45} CONFIG.BYTE0_PIN6_NAME {IO_L4P_T0U_N6_DBC_AD7P_45} CONFIG.BYTE0_PIN7_NAME {IO_L4N_T0U_N7_DBC_AD7N_45} CONFIG.BYTE0_PIN8_NAME {IO_L5P_T0U_N8_AD14P_45} CONFIG.BYTE0_PIN9_NAME {IO_L5N_T0U_N9_AD14N_45} CONFIG.BYTE0_PIN10_NAME {IO_L6P_T0U_N10_AD6P_45} CONFIG.BYTE0_PIN11_NAME {IO_L6N_T0U_N11_AD6N_45} CONFIG.BYTE0_PIN12_NAME {IO_T0U_N12_VRP_45} CONFIG.BYTE0_PIN4_BUS_DIR {TX} CONFIG.BYTE0_PIN5_BUS_DIR {TX} CONFIG.BYTE0_PIN8_BUS_DIR {TX} CONFIG.BYTE0_PIN9_BUS_DIR {TX} CONFIG.BYTE0_PIN8_DATA_STROBE {Clk Fwd} CONFIG.BYTE0_PIN9_DATA_STROBE {Clk Fwd} CONFIG.BYTE0_PIN4_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN5_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN8_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN9_SIG_TYPE {DIFF} CONFIG.ENABLE_BYTE0_PIN4 {true} CONFIG.ENABLE_BYTE0_PIN5 {true} CONFIG.ENABLE_BYTE0_PIN8 {true} CONFIG.ENABLE_BYTE0_PIN9 {true} CONFIG.BYTE1_PIN0_LOC {T30} CONFIG.BYTE1_PIN1_LOC {T31} CONFIG.BYTE1_PIN2_LOC {U31} CONFIG.BYTE1_PIN3_LOC {U32} CONFIG.BYTE1_PIN4_LOC {Y31} CONFIG.BYTE1_PIN5_LOC {W31} CONFIG.BYTE1_PIN6_LOC {R31} CONFIG.BYTE1_PIN7_LOC {P31} CONFIG.BYTE1_PIN8_LOC {R32} CONFIG.BYTE1_PIN9_LOC {P32} CONFIG.BYTE1_PIN10_LOC {T33} CONFIG.BYTE1_PIN11_LOC {R33} CONFIG.BYTE1_PIN12_LOC {V30} CONFIG.BYTE1_PIN0_NAME {IO_L7P_T1L_N0_QBC_AD13P_45} CONFIG.BYTE1_PIN1_NAME {IO_L7N_T1L_N1_QBC_AD13N_45} CONFIG.BYTE1_PIN2_NAME {IO_L8P_T1L_N2_AD5P_45} CONFIG.BYTE1_PIN3_NAME {IO_L8N_T1L_N3_AD5N_45} CONFIG.BYTE1_PIN4_NAME {IO_L9P_T1L_N4_AD12P_45} CONFIG.BYTE1_PIN5_NAME {IO_L9N_T1L_N5_AD12N_45} CONFIG.BYTE1_PIN6_NAME {IO_L10P_T1U_N6_QBC_AD4P_45} CONFIG.BYTE1_PIN7_NAME {IO_L10N_T1U_N7_QBC_AD4N_45} CONFIG.BYTE1_PIN8_NAME {IO_L11P_T1U_N8_GC_45} CONFIG.BYTE1_PIN9_NAME {IO_L11N_T1U_N9_GC_45} CONFIG.BYTE1_PIN10_NAME {IO_L12P_T1U_N10_GC_45} CONFIG.BYTE1_PIN11_NAME {IO_L12N_T1U_N11_GC_45} CONFIG.BYTE1_PIN12_NAME {IO_T1U_N12_45} CONFIG.ENABLE_BYTE2_PIN0 {false} CONFIG.ENABLE_BYTE2_PIN6 {true} CONFIG.ENABLE_BYTE2_PIN7 {true} CONFIG.ENABLE_BYTE2_PIN8 {true} CONFIG.ENABLE_BYTE2_PIN9 {true} CONFIG.BYTE2_PIN6_SIG_TYPE {DIFF} CONFIG.BYTE2_PIN7_SIG_TYPE {DIFF} CONFIG.BYTE2_PIN8_SIG_TYPE {DIFF} CONFIG.BYTE2_PIN9_SIG_TYPE {DIFF} CONFIG.BYTE2_PIN0_DATA_STROBE {Data} CONFIG.BYTE2_PIN6_DATA_STROBE {Strobe} CONFIG.BYTE2_PIN7_DATA_STROBE {Strobe} CONFIG.BYTE2_PIN6_SIGNAL_NAME {clk_in_p} CONFIG.BYTE2_PIN7_SIGNAL_NAME {clk_in_n} CONFIG.BYTE2_PIN8_SIGNAL_NAME {data_in_p} CONFIG.BYTE2_PIN9_SIGNAL_NAME {data_in_n} CONFIG.BYTE2_PIN0_LOC {R34} CONFIG.BYTE2_PIN1_LOC {P34} CONFIG.BYTE2_PIN2_LOC {P35} CONFIG.BYTE2_PIN3_LOC {P36} CONFIG.BYTE2_PIN4_LOC {M37} CONFIG.BYTE2_PIN5_LOC {L38} CONFIG.BYTE2_PIN6_LOC {P37} CONFIG.BYTE2_PIN7_LOC {N37} CONFIG.BYTE2_PIN8_LOC {M36} CONFIG.BYTE2_PIN9_LOC {L36} CONFIG.BYTE2_PIN10_LOC {N38} CONFIG.BYTE2_PIN11_LOC {M38} CONFIG.BYTE2_PIN12_LOC {R36} CONFIG.BYTE2_PIN0_NAME {IO_L13P_T2L_N0_GC_QBC_45} CONFIG.BYTE2_PIN1_NAME {IO_L13N_T2L_N1_GC_QBC_45} CONFIG.BYTE2_PIN2_NAME {IO_L14P_T2L_N2_GC_45} CONFIG.BYTE2_PIN3_NAME {IO_L14N_T2L_N3_GC_45} CONFIG.BYTE2_PIN4_NAME {IO_L15P_T2L_N4_AD11P_45} CONFIG.BYTE2_PIN5_NAME {IO_L15N_T2L_N5_AD11N_45} CONFIG.BYTE2_PIN6_NAME {IO_L16P_T2U_N6_QBC_AD3P_45} CONFIG.BYTE2_PIN7_NAME {IO_L16N_T2U_N7_QBC_AD3N_45} CONFIG.BYTE2_PIN8_NAME {IO_L17P_T2U_N8_AD10P_45} CONFIG.BYTE2_PIN9_NAME {IO_L17N_T2U_N9_AD10N_45} CONFIG.BYTE2_PIN10_NAME {IO_L18P_T2U_N10_AD2P_45} CONFIG.BYTE2_PIN11_NAME {IO_L18N_T2U_N11_AD2N_45} CONFIG.BYTE2_PIN12_NAME {IO_T2U_N12_45} CONFIG.ENABLE_BYTE3_PIN12 {false} CONFIG.BYTE3_PIN0_LOC {L34} CONFIG.BYTE3_PIN1_LOC {K34} CONFIG.BYTE3_PIN2_LOC {N34} CONFIG.BYTE3_PIN3_LOC {N35} CONFIG.BYTE3_PIN4_LOC {L33} CONFIG.BYTE3_PIN5_LOC {K33} CONFIG.BYTE3_PIN6_LOC {N33} CONFIG.BYTE3_PIN7_LOC {M33} CONFIG.BYTE3_PIN8_LOC {N32} CONFIG.BYTE3_PIN9_LOC {M32} CONFIG.BYTE3_PIN10_LOC {M35} CONFIG.BYTE3_PIN11_LOC {L35} CONFIG.BYTE3_PIN12_LOC {K36} CONFIG.BYTE3_PIN0_NAME {IO_L19P_T3L_N0_DBC_AD9P_45} CONFIG.BYTE3_PIN1_NAME {IO_L19N_T3L_N1_DBC_AD9N_45} CONFIG.BYTE3_PIN2_NAME {IO_L20P_T3L_N2_AD1P_45} CONFIG.BYTE3_PIN3_NAME {IO_L20N_T3L_N3_AD1N_45} CONFIG.BYTE3_PIN4_NAME {IO_L21P_T3L_N4_AD8P_45} CONFIG.BYTE3_PIN5_NAME {IO_L21N_T3L_N5_AD8N_45} CONFIG.BYTE3_PIN6_NAME {IO_L22P_T3U_N6_DBC_AD0P_45} CONFIG.BYTE3_PIN7_NAME {IO_L22N_T3U_N7_DBC_AD0N_45} CONFIG.BYTE3_PIN8_NAME {IO_L23P_T3U_N8_45} CONFIG.BYTE3_PIN9_NAME {IO_L23N_T3U_N9_45} CONFIG.BYTE3_PIN10_NAME {IO_L24P_T3U_N10_45} CONFIG.BYTE3_PIN11_NAME {IO_L24N_T3U_N11_45} CONFIG.BYTE3_PIN12_NAME {IO_T3U_N12_45} CONFIG.BYTE0_PIN5_INIT {1} CONFIG.BYTE0_PIN9_INIT {1} CONFIG.APPEND_PIN_NO {0}] [get_ips high_speed_selectio_wiz_0] + +generate_target {instantiation_template} [get_files ./ad9084_ebz_vcu118.srcs/sources_1/ip/high_speed_selectio_wiz_0/high_speed_selectio_wiz_0.xci] +generate_target all [get_files ./ad9084_ebz_vcu118.srcs/sources_1/ip/high_speed_selectio_wiz_0/high_speed_selectio_wiz_0.xci] + + +# Avoid critical warning in OOC mode from the clock definitions +# since at that stage the submodules are not stiched together yet +if {$ADI_USE_OOC_SYNTHESIS == 1} { + set_property used_in_synthesis false [get_files timing_constr.xdc] +} + +set_property strategy Performance_RefinePlacement [get_runs impl_1] + +adi_project_run ad9084_ebz_vcu118 diff --git a/projects/ad9084_ebz/vcu118/system_top.v b/projects/ad9084_ebz/vcu118/system_top.v new file mode 100755 index 00000000000..27000084add --- /dev/null +++ b/projects/ad9084_ebz/vcu118/system_top.v @@ -0,0 +1,608 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_NUM_LINKS = 1, + parameter RX_NUM_LINKS = 1, + parameter ASYMMETRIC_A_B_MODE = 1 +) ( + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + input uart_sin, + output uart_sout, + + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, + + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, + + inout [16:0] gpio_bd, + + output iic_rstn, + inout iic_scl, + inout iic_sda, + + // FMC HPC+ IOs + output [11:0] srxa_p, + output [11:0] srxa_n, + + output [11:0] srxb_p, + output [11:0] srxb_n, + + input [11:0] stxa_p, + input [11:0] stxa_n, + + input [11:0] stxb_p, + input [11:0] stxb_n, + + inout [30:15] gpio, + inout aux_gpio, + + output syncinb_a0_p, + output syncinb_a0_n, + output syncinb_b0_p, + output syncinb_b0_n, + inout syncinb_a1_p_gpio, + inout syncinb_a1_n_gpio, + inout syncinb_b1_p_gpio, + inout syncinb_b1_n_gpio, + + input syncoutb_a0_p, + input syncoutb_a0_n, + input syncoutb_b0_p, + input syncoutb_b0_n, + inout syncoutb_a1_p_gpio, + inout syncoutb_a1_n_gpio, + inout syncoutb_b1_p_gpio, + inout syncoutb_b1_n_gpio, + + input [ 2:0] ref_clk_p, + input [ 2:0] ref_clk_n, + input ref_clk_replica_p, + input ref_clk_replica_n, + + output sysref_a_p, + output sysref_a_n, + output sysref_b_p, + output sysref_b_n, + input sysref_p, + input sysref_n, + input sysref_in_p, + input sysref_in_n, + + output spi2_sclk, + inout spi2_sdio, + input spi2_sdo, + output [ 5:0] spi2_cs, + + output dut_sdio, + input dut_sdo, + output dut_sclk, + output dut_csb, + + input [ 1:0] clk_m2c_p, + input [ 1:0] clk_m2c_n, + + output hsci_ckin_p, + output hsci_ckin_n, + output hsci_din_p, + output hsci_din_n, + input hsci_cko_p, + input hsci_cko_n, + input hsci_do_p, + input hsci_do_n, + + output [ 1:0] trig_a, + output [ 1:0] trig_b, + + input trig_in, + output resetb +); + + localparam CLK_FWD_PAT = 8'h55; + localparam SYNC_W = (ASYMMETRIC_A_B_MODE == 1)? 2 : RX_NUM_LINKS; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire spi_clk; + wire [ 7:0] spi_csn; + wire spi_sdo; + wire spi_sdio; + wire hmc7044_sdo; + + wire apollo_spi_clk; + wire [ 7:0] apollo_spi_csn; + wire apollo_spi_sdo; + wire apollo_spi_sdio; + + wire ref_clk; + wire ref_clk_replica; + wire sysref; + wire sysref_loc; + wire [SYNC_W-1:0] tx_syncin; + wire [SYNC_W-1:0] rx_syncout; + + wire clkin0; + wire clkin1; + wire clkin2; + wire clkin3; + wire tx_device_clk; + wire rx_device_clk; + wire tx_b_device_clk; + wire rx_b_device_clk; + + wire tmp_sync; + + wire pll_inclk; + wire hsci_pll_reset; + wire hsci_pclk; + wire hsci_pll_locked; + wire hsci_vtc_rdy_bsc_tx; + wire hsci_dly_rdy_bsc_tx; + wire hsci_vtc_rdy_bsc_rx; + wire hsci_dly_rdy_bsc_rx; + wire hsci_rst_seq_done; + + wire selectio_clk_in; + wire [ 7:0] hsci_menc_clk; + wire [ 7:0] hsci_data_in; + wire [ 7:0] hsci_data_out; + + assign iic_rstn = 1'b1; + + // instantiations + + IBUFDS_GTE4 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (ref_clk_p[0]), + .IB (ref_clk_n[0]), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS_GTE4 i_ibufds_ref_clk_replica ( + .CEB (1'd0), + .I (ref_clk_replica_p), + .IB (ref_clk_replica_n), + .O (ref_clk_replica), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref_in ( + .I (sysref_in_p), + .IB (sysref_in_n), + .O (sysref)); + + OBUFDS i_obufds_sysref_a ( + .I (1'b0), + .O (sysref_a_p), + .OB (sysref_a_n)); + + OBUFDS i_obufds_sysref_b ( + .I (1'b0), + .O (sysref_b_p), + .OB (sysref_b_n)); + + IBUFDS i_ibufds_sysref_ext ( + .I (sysref_p), + .IB (sysref_n), + .O ()); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clk_m2c_p[0]), + .IB (clk_m2c_n[0]), + .O (clkin0)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clk_m2c_p[1]), + .IB (clk_m2c_n[1]), + .O (clkin1)); + + IBUFDS_GTE4 i_ibufds_rx_b_device_clk ( + .I (ref_clk_p[1]), + .IB (ref_clk_n[1]), + .CEB(1'b0), + .ODIV2 (clkin2)); + + IBUFDS_GTE4 i_ibufds_tx_b_device_clk ( + .I (ref_clk_p[2]), + .IB (ref_clk_n[2]), + .CEB(1'b0), + .ODIV2 (clkin3)); + + IBUFDS i_ibufds_syncin0 ( + .I (syncoutb_a0_p), + .IB (syncoutb_a0_n), + .O (tx_syncin[0])); + + OBUFDS i_obufds_syncout0 ( + .I (rx_syncout[0]), + .O (syncinb_a0_p), + .OB (syncinb_a0_n)); + + IBUFDS i_ibufds_syncin1 ( + .I (syncoutb_b0_p), + .IB (syncoutb_b0_n), + .O (tx_syncin[1])); + + OBUFDS i_obufds_syncout1 ( + .I (rx_syncout[1]), + .O (syncinb_b0_p), + .OB (syncinb_b0_n)); + + BUFG i_rx_device_clk ( + .I (clkin0), + .O (rx_device_clk)); + + BUFG i_tx_device_clk ( + .I (clkin1), + .O (tx_device_clk)); + + BUFG_GT i_rx_b_device_clk ( + .I (clkin2), + .O (rx_b_device_clk)); + + BUFG_GT i_tx_b_device_clk ( + .I (clkin3), + .O (tx_b_device_clk)); + + BUFG i_selectio_clk_in( + .I (selectio_clk_in), + .O (pll_inclk)); + // spi + + assign spi2_cs[5:0] = spi_csn[5:0]; + assign spi2_sclk = spi_clk; + + ad9084_ebz_spi #( + .NUM_OF_SLAVES(2) + ) i_spi ( + .spi_csn (spi_csn[1:0]), + .spi_clk (spi_clk), + .spi_mosi (spi_sdio), + .spi_miso (spi_sdo), + .spi_miso_in (spi2_sdo), + .spi_sdio (spi2_sdio)); + + assign dut_csb = apollo_spi_csn[0]; + assign dut_sclk = apollo_spi_clk; + assign dut_sdio = apollo_spi_sdio; + + assign apollo_spi_sdo = ~apollo_spi_csn[0] ? dut_sdo : 1'b0; + + // gpios + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf ( + .dio_t (gpio_t[48:32]), + .dio_i (gpio_o[48:32]), + .dio_o (gpio_i[48:32]), + .dio_p ({aux_gpio, // 48 + gpio[30:15]})); // 47-32 + + assign gpio_i[53] = trig_in; + + assign trig_a[0] = gpio_o[58]; + assign trig_a[1] = gpio_o[59]; + assign trig_b[0] = gpio_o[60]; + assign trig_b[1] = gpio_o[61]; + assign resetb = gpio_o[62]; + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf_bd ( + .dio_t (gpio_t[16:0]), + .dio_i (gpio_o[16:0]), + .dio_o (gpio_i[16:0]), + .dio_p (gpio_bd)); + + assign gpio_i[63:54] = gpio_o[63:54]; + assign gpio_i[31:17] = gpio_o[31:17]; + + generate + if (ASYMMETRIC_A_B_MODE == 1) + assign sysref_loc = sysref; + else + assign sysref_loc = 0; + endgenerate + + // trigger_generator trig_i ( + // .sysref (sysref), + // .device_clk (rx_device_clk), + // .gpio (aux_gpio), + // .rstn (trig_rstn), + // .trigger (trig) + // ); + + hsci_phy_top hsci_phy_top( + .pll_inclk (pll_inclk), + .hsci_pll_reset (hsci_pll_reset), + + .hsci_pclk (hsci_pclk), + .hsci_mosi_d_p (hsci_din_p), + .hsci_mosi_d_n (hsci_din_n), + + .hsci_miso_d_p (hsci_do_p), + .hsci_miso_d_n (hsci_do_n), + + .hsci_pll_locked (hsci_pll_locked), + + .hsci_mosi_clk_p (hsci_ckin_p), + .hsci_mosi_clk_n (hsci_ckin_n), + + .hsci_miso_clk_p (hsci_cko_p), + .hsci_miso_clk_n (hsci_cko_n), + + .hsci_menc_clk (hsci_menc_clk), + .hsci_mosi_data (hsci_data_out), + .hsci_miso_data (hsci_data_in), + + .vtc_rdy_bsc_tx (hsci_vtc_rdy_bsc_tx), + .dly_rdy_bsc_tx (hsci_dly_rdy_bsc_tx), + .vtc_rdy_bsc_rx (hsci_vtc_rdy_bsc_rx), + .dly_rdy_bsc_rx (hsci_dly_rdy_bsc_rx), + .rst_seq_done (hsci_rst_seq_done)); + + system_wrapper i_system_wrapper ( + .sys_rst (sys_rst), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .ddr4_act_n (ddr4_act_n), + .ddr4_adr (ddr4_addr), + .ddr4_ba (ddr4_ba), + .ddr4_bg (ddr4_bg), + .ddr4_ck_c (ddr4_ck_n), + .ddr4_ck_t (ddr4_ck_p), + .ddr4_cke (ddr4_cke), + .ddr4_cs_n (ddr4_cs_n), + .ddr4_dm_n (ddr4_dm_n), + .ddr4_dq (ddr4_dq), + .ddr4_dqs_c (ddr4_dqs_n), + .ddr4_dqs_t (ddr4_dqs_p), + .ddr4_odt (ddr4_odt), + .ddr4_reset_n (ddr4_reset_n), + .phy_sd (1'b1), + .phy_rst_n (phy_rst_n), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .sgmii_phyclk_clk_n (phy_clk_n), + .sgmii_phyclk_clk_p (phy_clk_p), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .uart_sin (uart_sin), + .uart_sout (uart_sout), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_sdo), + .spi_sdo_i (spi_sdio), + .spi_sdo_o (spi_sdio), + + .apollo_spi_clk_i (apollo_spi_clk), + .apollo_spi_clk_o (apollo_spi_clk), + .apollo_spi_csn_i (apollo_spi_csn), + .apollo_spi_csn_o (apollo_spi_csn), + .apollo_spi_sdi_i (apollo_spi_sdo), + .apollo_spi_sdo_i (apollo_spi_sdio), + .apollo_spi_sdo_o (apollo_spi_sdio), + + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + // FMC HPC+ + // quad 125 + .tx_data_0_n (srxa_n[10]), + .tx_data_0_p (srxa_p[10]), + .tx_data_1_n (srxa_n[8]), + .tx_data_1_p (srxa_p[8]), + .tx_data_2_n (srxa_n[9]), + .tx_data_2_p (srxa_p[9]), + .tx_data_3_n (srxa_n[11]), + .tx_data_3_p (srxa_p[11]), + // quad 126 + .tx_data_4_n (srxa_n[5]), + .tx_data_4_p (srxa_p[5]), + .tx_data_5_n (srxa_n[1]), + .tx_data_5_p (srxa_p[1]), + .tx_data_6_n (srxa_n[3]), + .tx_data_6_p (srxa_p[3]), + .tx_data_7_n (srxa_n[7]), + .tx_data_7_p (srxa_p[7]), + // quad 127 + .tx_data_8_n (srxa_n[4]), + .tx_data_8_p (srxa_p[4]), + .tx_data_9_n (srxa_n[6]), + .tx_data_9_p (srxa_p[6]), + .tx_data_10_n (srxa_n[2]), + .tx_data_10_p (srxa_p[2]), + .tx_data_11_n (srxa_n[0]), + .tx_data_11_p (srxa_p[0]), + + // quad 120 + .tx_data_12_n (srxb_n[4]), + .tx_data_12_p (srxb_p[4]), + .tx_data_13_n (srxb_n[6]), + .tx_data_13_p (srxb_p[6]), + .tx_data_14_n (srxb_n[2]), + .tx_data_14_p (srxb_p[2]), + .tx_data_15_n (srxb_n[0]), + .tx_data_15_p (srxb_p[0]), + // quad 121 + .tx_data_16_n (srxb_n[1]), + .tx_data_16_p (srxb_p[1]), + .tx_data_17_n (srxb_n[7]), + .tx_data_17_p (srxb_p[7]), + .tx_data_18_n (srxb_n[10]), + .tx_data_18_p (srxb_p[10]), + .tx_data_19_n (srxb_n[3]), + .tx_data_19_p (srxb_p[3]), + // quad 122 + .tx_data_20_n (srxb_n[5]), + .tx_data_20_p (srxb_p[5]), + .tx_data_21_n (srxb_n[8]), + .tx_data_21_p (srxb_p[8]), + .tx_data_22_n (srxb_n[9]), + .tx_data_22_p (srxb_p[9]), + .tx_data_23_n (srxb_n[11]), + .tx_data_23_p (srxb_p[11]), + + // quad 125 + .rx_data_0_n (stxa_n[7]), + .rx_data_0_p (stxa_p[7]), + .rx_data_1_n (stxa_n[5]), + .rx_data_1_p (stxa_p[5]), + .rx_data_2_n (stxa_n[1]), + .rx_data_2_p (stxa_p[1]), + .rx_data_3_n (stxa_n[2]), + .rx_data_3_p (stxa_p[2]), + // quad 126 + .rx_data_4_n (stxa_n[11]), + .rx_data_4_p (stxa_p[11]), + .rx_data_5_n (stxa_n[3]), + .rx_data_5_p (stxa_p[3]), + .rx_data_6_n (stxa_n[8]), + .rx_data_6_p (stxa_p[8]), + .rx_data_7_n (stxa_n[9]), + .rx_data_7_p (stxa_p[9]), + // quad 127 + .rx_data_8_n (stxa_n[10]), + .rx_data_8_p (stxa_p[10]), + .rx_data_9_n (stxa_n[6]), + .rx_data_9_p (stxa_p[6]), + .rx_data_10_n (stxa_n[4]), + .rx_data_10_p (stxa_p[4]), + .rx_data_11_n (stxa_n[0]), + .rx_data_11_p (stxa_p[0]), + + // quad 120 + .rx_data_12_n (stxb_n[10]), + .rx_data_12_p (stxb_p[10]), + .rx_data_13_n (stxb_n[6]), + .rx_data_13_p (stxb_p[6]), + .rx_data_14_n (stxb_n[4]), + .rx_data_14_p (stxb_p[4]), + .rx_data_15_n (stxb_n[0]), + .rx_data_15_p (stxb_p[0]), + // quad 121 + .rx_data_16_n (stxb_n[3]), + .rx_data_16_p (stxb_p[3]), + .rx_data_17_n (stxb_n[2]), + .rx_data_17_p (stxb_p[2]), + .rx_data_18_n (stxb_n[5]), + .rx_data_18_p (stxb_p[5]), + .rx_data_19_n (stxb_n[7]), + .rx_data_19_p (stxb_p[7]), + // quad 122 + .rx_data_20_n (stxb_n[8]), + .rx_data_20_p (stxb_p[8]), + .rx_data_21_n (stxb_n[1]), + .rx_data_21_p (stxb_p[1]), + .rx_data_22_n (stxb_n[11]), + .rx_data_22_p (stxb_p[11]), + .rx_data_23_n (stxb_n[9]), + .rx_data_23_p (stxb_p[9]), + + .ref_clk_q0 (ref_clk_replica), + .ref_clk_q1 (ref_clk_replica), + .ref_clk_q2 (ref_clk_replica), + .ref_clk_q3 (ref_clk), + .ref_clk_q4 (ref_clk), + .ref_clk_q5 (ref_clk), + + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), + .rx_b_device_clk (rx_b_device_clk), + .tx_b_device_clk (tx_b_device_clk), + + // .rx_device_clk_rstn(trig_rstn), + + .selectio_clk_in (selectio_clk_in), + .hsci_menc_clk (hsci_menc_clk), + .hsci_data_out (hsci_data_out), + .hsci_data_in (hsci_data_in), + .hsci_pclk (hsci_pclk), + .hsci_pll_reset (hsci_pll_reset), + .hsci_rst_seq_done(hsci_rst_seq_done), + .hsci_pll_locked (hsci_pll_locked), + .hsci_vtc_rdy_bsc_tx (hsci_vtc_rdy_bsc_tx), + .hsci_dly_rdy_bsc_tx (hsci_dly_rdy_bsc_tx), + .hsci_vtc_rdy_bsc_rx (hsci_vtc_rdy_bsc_rx), + .hsci_dly_rdy_bsc_rx (hsci_dly_rdy_bsc_rx), + + .rx_sync_0 (rx_syncout[0]), + .tx_sync_0 (tx_syncin[0]), + .rx_sync_12 (rx_syncout[1]), + .tx_sync_12 (tx_syncin[1]), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref), + .rx_sysref_12 (sysref_loc), + .tx_sysref_12 (sysref_loc)); + +endmodule diff --git a/projects/ad9084_ebz/vcu118/timing_constr.xdc b/projects/ad9084_ebz/vcu118/timing_constr.xdc new file mode 100755 index 00000000000..afe7e43b272 --- /dev/null +++ b/projects/ad9084_ebz/vcu118/timing_constr.xdc @@ -0,0 +1,78 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# source ../../../../hdl/scripts/adi_env.tcl +# Primary clock definitions + +# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block +# Maximum values for Link clock: +# 204B - 15.5 Gbps /40 = 387.5MHz +# 204C - 24.75 Gbps /66 = 375MHz + +set link_mode [get_property LINK_MODE [get_cells i_system_wrapper/system_i/util_apollo_xcvr/inst]] + +set rx_lane_rate [get_property RX_LANE_RATE [get_cells i_system_wrapper/system_i/util_apollo_xcvr/inst]] +set tx_lane_rate [get_property TX_LANE_RATE [get_cells i_system_wrapper/system_i/util_apollo_xcvr/inst]] + +set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] +set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] + +set rx_link_clk_period [expr 1000/$rx_link_clk] +set tx_link_clk_period [expr 1000/$tx_link_clk] + +set rx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_jesd/rx/inst]] +set tx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_jesd/tx/inst]] +set rx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_jesd/rx/inst]] +set tx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_jesd/tx/inst]] + +set rx_device_clk [expr $rx_link_clk*$rx_ll_width/$rx_tpl_width] +set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width] +set rx_device_clk_period [expr 1000/$rx_device_clk] +set tx_device_clk_period [expr 1000/$tx_device_clk] + +# refclk and refclk_replica are connect to the same source on the PCB +# Set reference clock to same frequency as the link clock, +# this will ease the XCVR out clocks propagation calculation. +# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE +create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p[0]] +create_clock -name refclk1 -period $rx_link_clk_period [get_ports ref_clk_replica_p] + +# device clock +create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clk_m2c_p[0]] +create_clock -name tx_device_clk -period $tx_device_clk_period [get_ports clk_m2c_p[1]] + +# hsci input clock +create_clock -name hsci_clk_out -period 1.25 [get_ports hsci_cko_p] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay -clock [get_clocks rx_device_clk] \ + [get_property PERIOD [get_clocks rx_device_clk]] \ + [get_ports {sysref_in*}] +set_input_delay -clock [get_clocks tx_device_clk] -add_delay\ + [get_property PERIOD [get_clocks tx_device_clk]] \ + [get_ports {sysref_in*}] + +set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous + +create_clock -name rx_b_device_clk -period $rx_device_clk_period [get_ports ref_clk_p[1]] +create_clock -name tx_b_device_clk -period $tx_device_clk_period [get_ports ref_clk_p[2]] + +set_clock_groups -group rx_b_device_clk -group tx_b_device_clk -asynchronous + +# For transceiver output clocks use reference clock divided by one +# This will help autoderive the clocks correcly +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]] + +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]] diff --git a/projects/ad9084_ebz/vpk180/Makefile b/projects/ad9084_ebz/vpk180/Makefile new file mode 100755 index 00000000000..f5a3580db6f --- /dev/null +++ b/projects/ad9084_ebz/vpk180/Makefile @@ -0,0 +1,49 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9084_ebz_vpk180 + +M_DEPS += ../common/versal_transceiver.tcl +M_DEPS += ../common/versal_hsci_phy.tcl +M_DEPS += ../common/ad9084_ebz_spi.v +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../common/vpk180/vpk180_system_constr.xdc +M_DEPS += ../../common/vpk180/vpk180_system_bd.tcl +M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../projects/common/xilinx/data_offload_bd.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hsci +LIB_DEPS += axi_sysid +LIB_DEPS += axi_tdd +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_tdd_sync +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9084_ebz/vpk180/system_bd.tcl b/projects/ad9084_ebz/vpk180/system_bd.tcl new file mode 100755 index 00000000000..da93ee8707b --- /dev/null +++ b/projects/ad9084_ebz/vpk180/system_bd.tcl @@ -0,0 +1,85 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +set ASYMMETRIC_A_B_MODE [ expr { [info exists ad_project_params(ASYMMETRIC_A_B_MODE)] \ + ? $ad_project_params(ASYMMETRIC_A_B_MODE) : 0 } ] + +if {$ASYMMETRIC_A_B_MODE == 1} { + ## ADC B Side FIFO depth in samples per converter + set adc_b_fifo_samples_per_converter [expr $ad_project_params(RX_B_KS_PER_CHANNEL)*1024] + ## DAC B Side FIFO depth in samples per converter + set dac_b_fifo_samples_per_converter [expr $ad_project_params(TX_B_KS_PER_CHANNEL)*1024] +} + +source $ad_hdl_dir/projects/common/vpk180/vpk180_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl + +set ADI_PHY_SEL 0 +set MAX_NUMBER_OF_QUADS 2 +set TRANSCEIVER_TYPE GTYP +set HSCI_BANKS 1 +set HSCI_ENABLE [ expr { [info exists ad_project_params(HSCI_ENABLE)] \ + ? $ad_project_params(HSCI_ENABLE) : 1 } ] + +adi_project_files ad9084_ebz_vpk180 [list \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ +] + +source $ad_hdl_dir/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2 +ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 + +if {$ASYMMETRIC_A_B_MODE == 1} { + ad_ip_parameter axi_apollo_rx_b_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2 + ad_ip_parameter axi_apollo_tx_b_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 +} + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +# Second SPI controller +create_bd_port -dir O -from 7 -to 0 apollo_spi_csn_o +create_bd_port -dir I -from 7 -to 0 apollo_spi_csn_i +create_bd_port -dir I apollo_spi_clk_i +create_bd_port -dir O apollo_spi_clk_o +create_bd_port -dir I apollo_spi_sdo_i +create_bd_port -dir O apollo_spi_sdo_o +create_bd_port -dir I apollo_spi_sdi_i + +ad_ip_instance axi_quad_spi axi_spi_2 +ad_ip_parameter axi_spi_2 CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_2 CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi_2 CONFIG.C_SCK_RATIO 16 +ad_ip_parameter axi_spi_2 CONFIG.Multiples16 1 + +ad_connect apollo_spi_csn_i axi_spi_2/ss_i +ad_connect apollo_spi_csn_o axi_spi_2/ss_o +ad_connect apollo_spi_clk_i axi_spi_2/sck_i +ad_connect apollo_spi_clk_o axi_spi_2/sck_o +ad_connect apollo_spi_sdo_i axi_spi_2/io0_i +ad_connect apollo_spi_sdo_o axi_spi_2/io0_o +ad_connect apollo_spi_sdi_i axi_spi_2/io1_i + +ad_connect $sys_cpu_clk axi_spi_2/ext_spi_clk + +ad_cpu_interrupt ps-9 mb-16 axi_spi_2/ip2intc_irpt + +ad_cpu_interconnect 0x44A80000 axi_spi_2 + +if {$HSCI_ENABLE} { + set_property range 256K [get_bd_addr_segs {sys_cips/M_AXI_FPD/SEG_data_axi_hsci_0}] +} diff --git a/projects/ad9084_ebz/vpk180/system_constr.xdc b/projects/ad9084_ebz/vpk180/system_constr.xdc new file mode 100644 index 00000000000..bf4f104e0ec --- /dev/null +++ b/projects/ad9084_ebz/vpk180/system_constr.xdc @@ -0,0 +1,126 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# +## Apollo +# + +set_property -dict {PACKAGE_PIN CB62 } [get_ports stx_n[0] ] ; ## FMCP1_DP0_M2C_N GTYP_200 +set_property -dict {PACKAGE_PIN CB61 } [get_ports stx_p[0] ] ; ## FMCP1_DP0_M2C_P GTYP_200 +set_property -dict {PACKAGE_PIN BY62 } [get_ports stx_n[1] ] ; ## FMCP1_DP1_M2C_N GTYP_200 +set_property -dict {PACKAGE_PIN BY61 } [get_ports stx_p[1] ] ; ## FMCP1_DP1_M2C_P GTYP_200 +set_property -dict {PACKAGE_PIN BW64 } [get_ports stx_n[2] ] ; ## FMCP1_DP2_M2C_N GTYP_200 +set_property -dict {PACKAGE_PIN BW63 } [get_ports stx_p[2] ] ; ## FMCP1_DP2_M2C_P GTYP_200 +set_property -dict {PACKAGE_PIN BV62 } [get_ports stx_n[3] ] ; ## FMCP1_DP3_M2C_N GTYP_200 +set_property -dict {PACKAGE_PIN BV61 } [get_ports stx_p[3] ] ; ## FMCP1_DP3_M2C_P GTYP_200 +set_property -dict {PACKAGE_PIN BU64 } [get_ports stx_n[4] ] ; ## FMCP1_DP4_M2C_N GTYP_201 +set_property -dict {PACKAGE_PIN BU63 } [get_ports stx_p[4] ] ; ## FMCP1_DP4_M2C_P GTYP_201 +set_property -dict {PACKAGE_PIN BT62 } [get_ports stx_n[5] ] ; ## FMCP1_DP5_M2C_N GTYP_201 +set_property -dict {PACKAGE_PIN BT61 } [get_ports stx_p[5] ] ; ## FMCP1_DP5_M2C_P GTYP_201 +set_property -dict {PACKAGE_PIN BR64 } [get_ports stx_n[6] ] ; ## FMCP1_DP6_M2C_N GTYP_201 +set_property -dict {PACKAGE_PIN BR63 } [get_ports stx_p[6] ] ; ## FMCP1_DP6_M2C_P GTYP_201 +set_property -dict {PACKAGE_PIN BR60 } [get_ports stx_n[7] ] ; ## FMCP1_DP7_M2C_N GTYP_201 +set_property -dict {PACKAGE_PIN BR59 } [get_ports stx_p[7] ] ; ## FMCP1_DP7_M2C_P GTYP_201 + +set_property -dict {PACKAGE_PIN CD55 } [get_ports srx_n[0] ] ; ## FMCP1_DP0_C2M_N GTYP_200 +set_property -dict {PACKAGE_PIN CD54 } [get_ports srx_p[0] ] ; ## FMCP1_DP0_C2M_P GTYP_200 +set_property -dict {PACKAGE_PIN CD59 } [get_ports srx_n[1] ] ; ## FMCP1_DP1_C2M_N GTYP_200 +set_property -dict {PACKAGE_PIN CD58 } [get_ports srx_p[1] ] ; ## FMCP1_DP1_C2M_P GTYP_200 +set_property -dict {PACKAGE_PIN CC57 } [get_ports srx_n[2] ] ; ## FMCP1_DP2_C2M_N GTYP_200 +set_property -dict {PACKAGE_PIN CC56 } [get_ports srx_p[2] ] ; ## FMCP1_DP2_C2M_P GTYP_200 +set_property -dict {PACKAGE_PIN CB59 } [get_ports srx_n[3] ] ; ## FMCP1_DP3_C2M_N GTYP_200 +set_property -dict {PACKAGE_PIN CB58 } [get_ports srx_p[3] ] ; ## FMCP1_DP3_C2M_P GTYP_200 +set_property -dict {PACKAGE_PIN CB55 } [get_ports srx_n[4] ] ; ## FMCP1_DP4_C2M_N GTYP_201 +set_property -dict {PACKAGE_PIN CB54 } [get_ports srx_p[4] ] ; ## FMCP1_DP4_C2M_P GTYP_201 +set_property -dict {PACKAGE_PIN CA57 } [get_ports srx_n[5] ] ; ## FMCP1_DP5_C2M_N GTYP_201 +set_property -dict {PACKAGE_PIN CA56 } [get_ports srx_p[5] ] ; ## FMCP1_DP5_C2M_P GTYP_201 +set_property -dict {PACKAGE_PIN BY59 } [get_ports srx_n[6] ] ; ## FMCP1_DP6_C2M_N GTYP_201 +set_property -dict {PACKAGE_PIN BY58 } [get_ports srx_p[6] ] ; ## FMCP1_DP6_C2M_P GTYP_201 +set_property -dict {PACKAGE_PIN BY55 } [get_ports srx_n[7] ] ; ## FMCP1_DP7_C2M_N GTYP_201 +set_property -dict {PACKAGE_PIN BY54 } [get_ports srx_p[7] ] ; ## FMCP1_DP7_C2M_P GTYP_201 + +set_property -dict {PACKAGE_PIN CA44 IOSTANDARD LVCMOS15 } [get_ports gpio[15] ] ; ## FMCP1_LA06_P +set_property -dict {PACKAGE_PIN CB45 IOSTANDARD LVCMOS15 } [get_ports gpio[16] ] ; ## FMCP1_LA06_N +set_property -dict {PACKAGE_PIN BY51 IOSTANDARD LVCMOS15 } [get_ports gpio[23] ] ; ## FMCP1_LA14_P +set_property -dict {PACKAGE_PIN CA52 IOSTANDARD LVCMOS15 } [get_ports gpio[24] ] ; ## FMCP1_LA14_N +set_property -dict {PACKAGE_PIN BW39 IOSTANDARD LVCMOS15 } [get_ports gpio[27] ] ; ## FMCP1_LA18_CC_P +set_property -dict {PACKAGE_PIN BY39 IOSTANDARD LVCMOS15 } [get_ports gpio[28] ] ; ## FMCP1_LA18_CC_N +set_property -dict {PACKAGE_PIN BW49 IOSTANDARD LVCMOS15 } [get_ports gpio[21] ] ; ## FMCP1_LA12_P +set_property -dict {PACKAGE_PIN BW50 IOSTANDARD LVCMOS15 } [get_ports gpio[22] ] ; ## FMCP1_LA12_N +set_property -dict {PACKAGE_PIN CB49 IOSTANDARD LVCMOS15 } [get_ports gpio[17] ] ; ## FMCP1_LA07_P +set_property -dict {PACKAGE_PIN CC50 IOSTANDARD LVCMOS15 } [get_ports gpio[18] ] ; ## FMCP1_LA07_N +set_property -dict {PACKAGE_PIN CB51 IOSTANDARD LVCMOS15 } [get_ports gpio[19] ] ; ## FMCP1_LA11_P +set_property -dict {PACKAGE_PIN CC52 IOSTANDARD LVCMOS15 } [get_ports gpio[20] ] ; ## FMCP1_LA11_N +set_property -dict {PACKAGE_PIN CD51 IOSTANDARD LVCMOS15 } [get_ports gpio[25] ] ; ## FMCP1_LA15_P +set_property -dict {PACKAGE_PIN CD52 IOSTANDARD LVCMOS15 } [get_ports gpio[26] ] ; ## FMCP1_LA15_N +set_property -dict {PACKAGE_PIN BN40 IOSTANDARD LVCMOS15 } [get_ports gpio[29] ] ; ## FMCP1_LA19_P +set_property -dict {PACKAGE_PIN BP40 IOSTANDARD LVCMOS15 } [get_ports gpio[30] ] ; ## FMCP1_LA19_N +set_property -dict {PACKAGE_PIN CA41 IOSTANDARD LVCMOS15 } [get_ports aux_gpio ] ; ## FMCP1_LA32_N + +set_property -dict {PACKAGE_PIN BR42 IOSTANDARD LVCMOS15 } [get_ports syncinb_a1_p_gpio ] ; ## FMCP1_LA20_P +set_property -dict {PACKAGE_PIN BT41 IOSTANDARD LVCMOS15 } [get_ports syncinb_a1_n_gpio ] ; ## FMCP1_LA20_N +set_property -dict {PACKAGE_PIN CD42 IOSTANDARD LVCMOS15 } [get_ports syncinb_b1_p_gpio ] ; ## FMCP1_LA22_P +set_property -dict {PACKAGE_PIN CD43 IOSTANDARD LVCMOS15 } [get_ports syncinb_b1_n_gpio ] ; ## FMCP1_LA22_N +set_property -dict {PACKAGE_PIN CD40 IOSTANDARD LVCMOS15 } [get_ports syncoutb_a1_p_gpio ] ; ## FMCP1_LA21_P +set_property -dict {PACKAGE_PIN CD41 IOSTANDARD LVCMOS15 } [get_ports syncoutb_a1_n_gpio ] ; ## FMCP1_LA21_N +set_property -dict {PACKAGE_PIN CB40 IOSTANDARD LVCMOS15 } [get_ports syncoutb_b1_p_gpio ] ; ## FMCP1_LA23_P +set_property -dict {PACKAGE_PIN CC40 IOSTANDARD LVCMOS15 } [get_ports syncoutb_b1_n_gpio ] ; ## FMCP1_LA23_N + +set_property -dict {PACKAGE_PIN CA49 IOSTANDARD LVDS15 } [get_ports syncinb_a0_p ] ; ## FMCP1_LA04_P +set_property -dict {PACKAGE_PIN CB50 IOSTANDARD LVDS15 } [get_ports syncinb_a0_n ] ; ## FMCP1_LA04_N +set_property -dict {PACKAGE_PIN BY49 IOSTANDARD LVDS15 } [get_ports syncinb_b0_p ] ; ## FMCP1_LA08_P +set_property -dict {PACKAGE_PIN BY50 IOSTANDARD LVDS15 } [get_ports syncinb_b0_n ] ; ## FMCP1_LA08_N +set_property -dict {PACKAGE_PIN CC43 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_a0_p ] ; ## FMCP1_LA05_P +set_property -dict {PACKAGE_PIN CB44 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_a0_n ] ; ## FMCP1_LA05_N +set_property -dict {PACKAGE_PIN CC45 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_b0_p ] ; ## FMCP1_LA09_P +set_property -dict {PACKAGE_PIN CD46 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports syncoutb_b0_n ] ; ## FMCP1_LA09_N + +set_property -dict {PACKAGE_PIN AT48 } [get_ports ref_clk_p ] ; ## FMCP1_GBTCLK0_M2C_C_P GTYP_REFCLKP0_200 +set_property -dict {PACKAGE_PIN AT49 } [get_ports ref_clk_n ] ; ## FMCP1_GBTCLK0_M2C_C_N GTYP_REFCLKN0_200 + +set_property -dict {PACKAGE_PIN CA51 IOSTANDARD LVDS15 } [get_ports sysref_a_p ] ; ## FMCP1_LA16_P +set_property -dict {PACKAGE_PIN CB52 IOSTANDARD LVDS15 } [get_ports sysref_a_n ] ; ## FMCP1_LA16_N +set_property -dict {PACKAGE_PIN BU41 IOSTANDARD LVDS15 } [get_ports sysref_b_p ] ; ## FMCP1_LA17_CC_P +set_property -dict {PACKAGE_PIN BU42 IOSTANDARD LVDS15 } [get_ports sysref_b_n ] ; ## FMCP1_LA17_CC_N +set_property -dict {PACKAGE_PIN BV49 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref_p ] ; ## FMCP1_LA00_CC_P +set_property -dict {PACKAGE_PIN BV50 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref_n ] ; ## FMCP1_LA00_CC_N +set_property -dict {PACKAGE_PIN BV41 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref_in_p ] ; ## FMCP1_LA33_P +set_property -dict {PACKAGE_PIN BW41 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref_in_n ] ; ## FMCP1_LA33_N + +set_property -dict {PACKAGE_PIN BY40 IOSTANDARD LVCMOS15 } [get_ports spi2_sclk ] ; ## FMCP1_LA24_P +set_property -dict {PACKAGE_PIN CA39 IOSTANDARD LVCMOS15 } [get_ports spi2_sdio ] ; ## FMCP1_LA24_N +set_property -dict {PACKAGE_PIN CB41 IOSTANDARD LVCMOS15 } [get_ports spi2_sdo ] ; ## FMCP1_LA26_P +set_property -dict {PACKAGE_PIN CC42 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[0] ] ; ## FMCP1_LA26_N +set_property -dict {PACKAGE_PIN BY38 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[1] ] ; ## FMCP1_LA29_P +set_property -dict {PACKAGE_PIN CA37 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[2] ] ; ## FMCP1_LA29_N +set_property -dict {PACKAGE_PIN BR39 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[3] ] ; ## FMCP1_LA30_P +set_property -dict {PACKAGE_PIN BT39 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[4] ] ; ## FMCP1_LA30_N +set_property -dict {PACKAGE_PIN BY41 IOSTANDARD LVCMOS15 } [get_ports spi2_cs[5] ] ; ## FMCP1_LA32_P + +set_property -dict {PACKAGE_PIN CD47 IOSTANDARD LVCMOS15 } [get_ports dut_sdio ] ; ## FMCP1_LA03_P +set_property -dict {PACKAGE_PIN CD48 IOSTANDARD LVCMOS15 } [get_ports dut_sdo ] ; ## FMCP1_LA03_N +set_property -dict {PACKAGE_PIN CB46 IOSTANDARD LVCMOS15 } [get_ports dut_sclk ] ; ## FMCP1_LA02_P +set_property -dict {PACKAGE_PIN CC47 IOSTANDARD LVCMOS15 } [get_ports dut_csb ] ; ## FMCP1_LA02_N + +set_property -dict {PACKAGE_PIN BY43 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_p[0] ] ; ## FMCP1_CLK0_M2C_P +set_property -dict {PACKAGE_PIN BY44 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_n[0] ] ; ## FMCP1_CLK0_M2C_N +set_property -dict {PACKAGE_PIN BN39 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_p[1] ] ; ## FMCP1_CLK1_M2C_P +set_property -dict {PACKAGE_PIN BP38 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clk_m2c_n[1] ] ; ## FMCP1_CLK1_M2C_N + +set_property -dict {PACKAGE_PIN CC44 IOSTANDARD LVCMOS15 } [get_ports trig_a[0] ] ; ## FMCP1_LA10_P +set_property -dict {PACKAGE_PIN CD45 IOSTANDARD LVCMOS15 } [get_ports trig_a[1] ] ; ## FMCP1_LA10_N +set_property -dict {PACKAGE_PIN CC49 IOSTANDARD LVCMOS15 } [get_ports trig_b[0] ] ; ## FMCP1_LA13_P +set_property -dict {PACKAGE_PIN CD50 IOSTANDARD LVCMOS15 } [get_ports trig_b[1] ] ; ## FMCP1_LA13_N +set_property -dict {PACKAGE_PIN BW52 IOSTANDARD LVCMOS15 } [get_ports trig_in ] ; ## FMCP1_LA01_CC_N +set_property -dict {PACKAGE_PIN BW51 IOSTANDARD LVCMOS15 } [get_ports resetb ] ; ## FMCP1_LA01_CC_P + +set_property -dict {PACKAGE_PIN CA38 IOSTANDARD LVDS15 } [get_ports hsci_ckin_p ] ; ## FMCP1_LA27_P BANK 709 +set_property -dict {PACKAGE_PIN CB39 IOSTANDARD LVDS15 } [get_ports hsci_ckin_n ] ; ## FMCP1_LA27_N BANK 709 +set_property -dict {PACKAGE_PIN CC38 IOSTANDARD LVDS15 } [get_ports hsci_din_p ] ; ## FMCP1_LA25_P BANK 709 +set_property -dict {PACKAGE_PIN CC39 IOSTANDARD LVDS15 } [get_ports hsci_din_n ] ; ## FMCP1_LA25_N BANK 709 +set_property -dict {PACKAGE_PIN BR41 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_p ] ; ## FMCP1_LA31_P BANK 709 +set_property -dict {PACKAGE_PIN BT40 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_n ] ; ## FMCP1_LA31_N BANK 709 +set_property -dict {PACKAGE_PIN BR37 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_p ] ; ## FMCP1_LA28_P BANK 709 +set_property -dict {PACKAGE_PIN BR38 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_n ] ; ## FMCP1_LA28_N BANK 709 diff --git a/projects/ad9084_ebz/vpk180/system_project.tcl b/projects/ad9084_ebz/vpk180/system_project.tcl new file mode 100755 index 00000000000..538858a7d4a --- /dev/null +++ b/projects/ad9084_ebz/vpk180/system_project.tcl @@ -0,0 +1,94 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../../projects/scripts/adi_project_xilinx.tcl +source ../../../projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make JESD_MODE=64B66B RX_LANE_RATE=10.3125 TX_LANE_RATE=10.3125 RX_JESD_M=4 TX_JESD_M=4 RX_JESD_L=8 TX_JESD_L=8 RX_JESD_S=1 TX_JESD_S=1 RX_JESD_NP=16 TX_JESD_NP=16 +# + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C +# 8B10B - 8b10b link layer defined in JESD 204B +# +# REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B +# HSCI_ENABLE : If set, adds and enables the HSCI core in the design +# RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample +# [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 +# [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) +# ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link +# RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side +# TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side +# [RX/TX]_B_JESD_M : Number of converters per link for B side +# [RX/TX]_B_JESD_L : Number of lanes per link for B side +# [RX/TX]_B_JESD_NP : Number of bits per sample for B side +# [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side +# + +adi_project ad9084_ebz_vpk180 0 [list \ + JESD_MODE [get_env_param JESD_MODE 64B66B ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 312.5 ] \ + ENABLE_HSCI [get_env_param HSCI_ENABLE 1 ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 20.625 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 20.625 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 2 ] \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 2 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ + ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0 ] \ + RX_B_LANE_RATE [get_env_param RX_B_LANE_RATE 20.625 ] \ + TX_B_LANE_RATE [get_env_param TX_B_LANE_RATE 20.625 ] \ + RX_B_JESD_M [get_env_param RX_B_JESD_M 4 ] \ + RX_B_JESD_L [get_env_param RX_B_JESD_L 4 ] \ + RX_B_JESD_S [get_env_param RX_B_JESD_S 1 ] \ + RX_B_JESD_NP [get_env_param RX_B_JESD_NP 16 ] \ + TX_B_JESD_M [get_env_param TX_B_JESD_M 4 ] \ + TX_B_JESD_L [get_env_param TX_B_JESD_L 4 ] \ + TX_B_JESD_S [get_env_param TX_B_JESD_S 1 ] \ + TX_B_JESD_NP [get_env_param TX_B_JESD_NP 16 ] \ + RX_B_KS_PER_CHANNEL [get_env_param RX_B_KS_PER_CHANNEL 64 ] \ + TX_B_KS_PER_CHANNEL [get_env_param TX_B_KS_PER_CHANNEL 64 ] \ +] + +adi_project_files ad9084_ebz_vpk180 [list \ + "system_top.v" \ + "system_constr.xdc" \ + "timing_constr.tcl" \ + "../common/ad9084_ebz_spi.v" \ + "../common/versal_transceiver.tcl" \ + "../common/versal_hsci_phy.tcl" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vpk180/vpk180_system_constr.xdc" ] + +# Avoid critical warning in OOC mode from the clock definitions +# since at that stage the submodules are not stiched together yet +if {$ADI_USE_OOC_SYNTHESIS == 1} { + set_property used_in_synthesis false [get_files timing_constr.tcl] +} + +set_property strategy Performance_RefinePlacement [get_runs impl_1] + +adi_project_run ad9084_ebz_vpk180 diff --git a/projects/ad9084_ebz/vpk180/system_top.v b/projects/ad9084_ebz/vpk180/system_top.v new file mode 100755 index 00000000000..e4271cee8f8 --- /dev/null +++ b/projects/ad9084_ebz/vpk180/system_top.v @@ -0,0 +1,493 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_NUM_LINKS = 1, + parameter RX_NUM_LINKS = 1, + parameter ASYMMETRIC_A_B_MODE = 0 +) ( + input sys_clk_n, + input sys_clk_p, + + output [ 5:0] ch0_lpddr4_trip1_ca_a, + output [ 5:0] ch0_lpddr4_trip1_ca_b, + output ch0_lpddr4_trip1_ck_c_a, + output ch0_lpddr4_trip1_ck_c_b, + output ch0_lpddr4_trip1_ck_t_a, + output ch0_lpddr4_trip1_ck_t_b, + output ch0_lpddr4_trip1_cke_a, + output ch0_lpddr4_trip1_cke_b, + output ch0_lpddr4_trip1_cs_a, + output ch0_lpddr4_trip1_cs_b, + inout [ 1:0] ch0_lpddr4_trip1_dmi_a, + inout [ 1:0] ch0_lpddr4_trip1_dmi_b, + inout [15:0] ch0_lpddr4_trip1_dq_a, + inout [15:0] ch0_lpddr4_trip1_dq_b, + inout [ 1:0] ch0_lpddr4_trip1_dqs_c_a, + inout [ 1:0] ch0_lpddr4_trip1_dqs_c_b, + inout [ 1:0] ch0_lpddr4_trip1_dqs_t_a, + inout [ 1:0] ch0_lpddr4_trip1_dqs_t_b, + output ch0_lpddr4_trip1_reset_n, + output [ 5:0] ch1_lpddr4_trip1_ca_a, + output [ 5:0] ch1_lpddr4_trip1_ca_b, + output ch1_lpddr4_trip1_ck_c_a, + output ch1_lpddr4_trip1_ck_c_b, + output ch1_lpddr4_trip1_ck_t_a, + output ch1_lpddr4_trip1_ck_t_b, + output ch1_lpddr4_trip1_cke_a, + output ch1_lpddr4_trip1_cke_b, + output ch1_lpddr4_trip1_cs_a, + output ch1_lpddr4_trip1_cs_b, + inout [ 1:0] ch1_lpddr4_trip1_dmi_a, + inout [ 1:0] ch1_lpddr4_trip1_dmi_b, + inout [15:0] ch1_lpddr4_trip1_dq_a, + inout [15:0] ch1_lpddr4_trip1_dq_b, + inout [ 1:0] ch1_lpddr4_trip1_dqs_c_a, + inout [ 1:0] ch1_lpddr4_trip1_dqs_c_b, + inout [ 1:0] ch1_lpddr4_trip1_dqs_t_a, + inout [ 1:0] ch1_lpddr4_trip1_dqs_t_b, + output ch1_lpddr4_trip1_reset_n, + + // GPIOs + output [ 3:0] gpio_led, + input [ 3:0] gpio_dip_sw, + input [ 1:0] gpio_pb, + + // FMC HPC+ IOs + + output [ 7:0] srx_p, + output [ 7:0] srx_n, + input [ 7:0] stx_p, + input [ 7:0] stx_n, + + inout [30:15] gpio, + inout aux_gpio, + + output syncinb_a0_p, + output syncinb_a0_n, + output syncinb_b0_p, + output syncinb_b0_n, + inout syncinb_a1_p_gpio, + inout syncinb_a1_n_gpio, + inout syncinb_b1_p_gpio, + inout syncinb_b1_n_gpio, + + input syncoutb_a0_p, + input syncoutb_a0_n, + input syncoutb_b0_p, + input syncoutb_b0_n, + inout syncoutb_a1_p_gpio, + inout syncoutb_a1_n_gpio, + inout syncoutb_b1_p_gpio, + inout syncoutb_b1_n_gpio, + + input ref_clk_p, + input ref_clk_n, + + output sysref_a_p, + output sysref_a_n, + output sysref_b_p, + output sysref_b_n, + input sysref_p, + input sysref_n, + input sysref_in_p, + input sysref_in_n, + + output spi2_sclk, + inout spi2_sdio, + input spi2_sdo, + output [ 5:0] spi2_cs, + + output dut_sdio, + input dut_sdo, + output dut_sclk, + output dut_csb, + + input [ 1:0] clk_m2c_p, + input [ 1:0] clk_m2c_n, + + output hsci_ckin_p, + output hsci_ckin_n, + output hsci_din_p, + output hsci_din_n, + input hsci_cko_p, + input hsci_cko_n, + input hsci_do_p, + input hsci_do_n, + + output [ 1:0] trig_a, + output [ 1:0] trig_b, + + input trig_in, + output resetb +); + + localparam SYNC_W = (ASYMMETRIC_A_B_MODE == 1)? 2 : RX_NUM_LINKS; + + // internal signals + + wire [95:0] gpio_i; + wire [95:0] gpio_o; + wire [95:0] gpio_t; + + wire spi_clk; + wire [ 7:0] spi_csn; + wire spi_sdo; + wire spi_sdio; + wire hmc7044_sdo; + + wire apollo_spi_clk; + wire [ 7:0] apollo_spi_csn; + wire apollo_spi_sdo; + wire apollo_spi_sdio; + + wire ref_clk; + wire sysref; + wire [SYNC_W-1:0] tx_syncin; + wire [SYNC_W-1:0] rx_syncout; + + wire clkin0; + wire clkin1; + wire tx_device_clk; + wire rx_device_clk; + + wire intf_rdy; + wire fifo_empty; + wire fifo_rd_en; + wire [ 7:0] hsci_data_out; + wire [ 7:0] data_from_fabric; + wire [ 7:0] data_to_fabric; + wire [ 7:0] hsci_data_in; + + wire gt_reset; + wire rx_reset_pll_and_datapath; + wire tx_reset_pll_and_datapath; + wire rx_reset_datapath; + wire tx_reset_datapath; + wire rx_resetdone; + wire tx_resetdone; + wire gt_b_reset; + wire rx_b_reset_pll_and_datapath; + wire tx_b_reset_pll_and_datapath; + wire rx_b_reset_datapath; + wire tx_b_reset_datapath; + wire rx_b_resetdone; + wire tx_b_resetdone; + wire gt_powergood; + + wire [7:0] rx_data_p_loc; + wire [7:0] rx_data_n_loc; + wire [7:0] tx_data_p_loc; + wire [7:0] tx_data_n_loc; + + // instantiations + + IBUFDS_GTE5 i_ibufds_ref_clk ( + .CEB (1'b0), + .I (ref_clk_p), + .IB (ref_clk_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref_in ( + .I (sysref_in_p), + .IB (sysref_in_n), + .O (sysref)); + + OBUFDS i_obufds_sysref_a ( + .I (1'b0), + .O (sysref_a_p), + .OB (sysref_a_n)); + + OBUFDS i_obufds_sysref_b ( + .I (1'b0), + .O (sysref_b_p), + .OB (sysref_b_n)); + + IBUFDS i_ibufds_sysref_ext ( + .I (sysref_p), + .IB (sysref_n), + .O ()); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clk_m2c_p[0]), + .IB (clk_m2c_n[0]), + .O (clkin0)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clk_m2c_p[1]), + .IB (clk_m2c_n[1]), + .O (clkin1)); + + IBUFDS i_ibufds_syncin0 ( + .I (syncoutb_a0_p), + .IB (syncoutb_a0_n), + .O (tx_syncin[0])); + + OBUFDS i_obufds_syncout0 ( + .I (rx_syncout[0]), + .O (syncinb_a0_p), + .OB (syncinb_a0_n)); + + IBUFDS i_ibufds_syncin1 ( + .I (syncoutb_b0_p), + .IB (syncoutb_b0_n), + .O (tx_syncin[1])); + + OBUFDS i_obufds_syncout1 ( + .I (rx_syncout[1]), + .O (syncinb_b0_p), + .OB (syncinb_b0_n)); + + BUFG i_rx_device_clk ( + .I (clkin0), + .O (rx_device_clk)); + + BUFG i_tx_device_clk ( + .I (clkin1), + .O (tx_device_clk)); + + // spi + assign spi2_cs[5:0] = spi_csn[5:0]; + assign spi2_sclk = spi_clk; + + ad9084_ebz_spi #( + .NUM_OF_SLAVES(2) + ) i_spi ( + .spi_csn (spi_csn[1:0]), + .spi_clk (spi_clk), + .spi_mosi (spi_sdio), + .spi_miso (spi_sdo), + .spi_miso_in (spi2_sdo), + .spi_sdio (spi2_sdio)); + + assign dut_csb = apollo_spi_csn[0]; + assign dut_sclk = apollo_spi_clk; + assign dut_sdio = apollo_spi_sdio; + + assign apollo_spi_sdo = ~apollo_spi_csn[0] ? dut_sdo : 1'b0; + + // gpios + /* Board GPIOS. Buttons, LEDs, etc... */ + assign gpio_led = gpio_o[3:0]; + assign gpio_i[3:0] = gpio_o[3:0]; + assign gpio_i[7:4] = gpio_dip_sw; + assign gpio_i[9:8] = gpio_pb; + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf ( + .dio_t (gpio_t[48:32]), + .dio_i (gpio_o[48:32]), + .dio_o (gpio_i[48:32]), + .dio_p ({aux_gpio, // 48 + gpio[30:15]})); // 47-32 + + assign gpio_i[53] = trig_in; + + assign trig_a[0] = gpio_o[58]; + assign trig_a[1] = gpio_o[59]; + assign trig_b[0] = gpio_o[60]; + assign trig_b[1] = gpio_o[61]; + assign resetb = gpio_o[62]; + + assign gpio_i[64] = rx_resetdone; + assign gpio_i[65] = tx_resetdone; + assign gpio_i[66] = rx_resetdone & tx_resetdone; + assign gt_reset = gpio_o[67]; + assign rx_reset_pll_and_datapath = gpio_o[68]; + assign tx_reset_pll_and_datapath = gpio_o[69]; + assign rx_reset_datapath = gpio_o[70]; + assign tx_reset_datapath = gpio_o[71]; + + assign gpio_i[72] = rx_b_resetdone; + assign gpio_i[73] = tx_b_resetdone; + assign gpio_i[74] = rx_b_resetdone & tx_b_resetdone; + assign gt_b_reset = gpio_o[75]; + assign rx_b_reset_pll_and_datapath = gpio_o[76]; + assign tx_b_reset_pll_and_datapath = gpio_o[77]; + assign rx_b_reset_datapath = gpio_o[78]; + assign tx_b_reset_datapath = gpio_o[79]; + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf_bd ( + .dio_t (gpio_t[26:10]), + .dio_i (gpio_o[26:10]), + .dio_o (gpio_i[26:10]), + .dio_p (gpio_bd)); + + assign gpio_i[95:80] = gpio_o[95:80]; + assign gpio_i[62:54] = gpio_o[62:54]; + assign gpio_i[31:27] = gpio_o[31:27]; + + assign fifo_rd_en = ~fifo_empty & intf_rdy; + assign data_from_fabric = {hsci_data_out[0], hsci_data_out[1], hsci_data_out[2], hsci_data_out[3], hsci_data_out[4], hsci_data_out[5], hsci_data_out[6], hsci_data_out[7]}; + assign hsci_data_in = (intf_rdy) ? {data_to_fabric[0], data_to_fabric[1], data_to_fabric[2], data_to_fabric[3], data_to_fabric[4], data_to_fabric[5], data_to_fabric[6], data_to_fabric[7]} : 8'h0; + + system_wrapper i_system_wrapper ( + .lpddr4_clk1_clk_n (sys_clk_n), + .lpddr4_clk1_clk_p (sys_clk_p), + + .ch0_lpddr4_trip1_ca_a (ch0_lpddr4_trip1_ca_a), + .ch0_lpddr4_trip1_ca_b (ch0_lpddr4_trip1_ca_b), + .ch0_lpddr4_trip1_ck_c_a (ch0_lpddr4_trip1_ck_c_a), + .ch0_lpddr4_trip1_ck_c_b (ch0_lpddr4_trip1_ck_c_b), + .ch0_lpddr4_trip1_ck_t_a (ch0_lpddr4_trip1_ck_t_a), + .ch0_lpddr4_trip1_ck_t_b (ch0_lpddr4_trip1_ck_t_b), + .ch0_lpddr4_trip1_cke_a (ch0_lpddr4_trip1_cke_a), + .ch0_lpddr4_trip1_cke_b (ch0_lpddr4_trip1_cke_b), + .ch0_lpddr4_trip1_cs_a (ch0_lpddr4_trip1_cs_a), + .ch0_lpddr4_trip1_cs_b (ch0_lpddr4_trip1_cs_b), + .ch0_lpddr4_trip1_dmi_a (ch0_lpddr4_trip1_dmi_a), + .ch0_lpddr4_trip1_dmi_b (ch0_lpddr4_trip1_dmi_b), + .ch0_lpddr4_trip1_dq_a (ch0_lpddr4_trip1_dq_a), + .ch0_lpddr4_trip1_dq_b (ch0_lpddr4_trip1_dq_b), + .ch0_lpddr4_trip1_dqs_c_a (ch0_lpddr4_trip1_dqs_c_a), + .ch0_lpddr4_trip1_dqs_c_b (ch0_lpddr4_trip1_dqs_c_b), + .ch0_lpddr4_trip1_dqs_t_a (ch0_lpddr4_trip1_dqs_t_a), + .ch0_lpddr4_trip1_dqs_t_b (ch0_lpddr4_trip1_dqs_t_b), + .ch0_lpddr4_trip1_reset_n (ch0_lpddr4_trip1_reset_n), + .ch1_lpddr4_trip1_ca_a (ch1_lpddr4_trip1_ca_a), + .ch1_lpddr4_trip1_ca_b (ch1_lpddr4_trip1_ca_b), + .ch1_lpddr4_trip1_ck_c_a (ch1_lpddr4_trip1_ck_c_a), + .ch1_lpddr4_trip1_ck_c_b (ch1_lpddr4_trip1_ck_c_b), + .ch1_lpddr4_trip1_ck_t_a (ch1_lpddr4_trip1_ck_t_a), + .ch1_lpddr4_trip1_ck_t_b (ch1_lpddr4_trip1_ck_t_b), + .ch1_lpddr4_trip1_cke_a (ch1_lpddr4_trip1_cke_a), + .ch1_lpddr4_trip1_cke_b (ch1_lpddr4_trip1_cke_b), + .ch1_lpddr4_trip1_cs_a (ch1_lpddr4_trip1_cs_a), + .ch1_lpddr4_trip1_cs_b (ch1_lpddr4_trip1_cs_b), + .ch1_lpddr4_trip1_dmi_a (ch1_lpddr4_trip1_dmi_a), + .ch1_lpddr4_trip1_dmi_b (ch1_lpddr4_trip1_dmi_b), + .ch1_lpddr4_trip1_dq_a (ch1_lpddr4_trip1_dq_a), + .ch1_lpddr4_trip1_dq_b (ch1_lpddr4_trip1_dq_b), + .ch1_lpddr4_trip1_dqs_c_a (ch1_lpddr4_trip1_dqs_c_a), + .ch1_lpddr4_trip1_dqs_c_b (ch1_lpddr4_trip1_dqs_c_b), + .ch1_lpddr4_trip1_dqs_t_a (ch1_lpddr4_trip1_dqs_t_a), + .ch1_lpddr4_trip1_dqs_t_b (ch1_lpddr4_trip1_dqs_t_b), + .ch1_lpddr4_trip1_reset_n (ch1_lpddr4_trip1_reset_n), + .spi0_csn (spi_csn), + .spi0_miso (spi_sdo), + .spi0_mosi (spi_sdio), + .spi0_sclk (spi_clk), + + .apollo_spi_clk_i (apollo_spi_clk), + .apollo_spi_clk_o (apollo_spi_clk), + .apollo_spi_csn_i (apollo_spi_csn), + .apollo_spi_csn_o (apollo_spi_csn), + .apollo_spi_sdi_i (apollo_spi_sdo), + .apollo_spi_sdo_i (apollo_spi_sdio), + .apollo_spi_sdo_o (apollo_spi_sdio), + + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .gpio2_i (gpio_i[95:64]), + .gpio2_o (gpio_o[95:64]), + .gpio2_t (gpio_t[95:64]), + + // FMC HPC + // Apollo A-side + .tx_0_p (tx_data_p_loc[3:0]), + .tx_0_n (tx_data_n_loc[3:0]), + .rx_0_p (rx_data_p_loc[3:0]), + .rx_0_n (rx_data_n_loc[3:0]), + // Apollo B-Side + .tx_1_p (tx_data_p_loc[7:4]), + .tx_1_n (tx_data_n_loc[7:4]), + .rx_1_p (rx_data_p_loc[7:4]), + .rx_1_n (rx_data_n_loc[7:4]), + + .gt_powergood (gt_powergood), + .gt_reset (gt_reset & gt_powergood), + .gt_reset_rx_datapath (rx_reset_datapath), + .gt_reset_tx_datapath (tx_reset_datapath), + .gt_reset_rx_pll_and_datapath (rx_reset_pll_and_datapath), + .gt_reset_tx_pll_and_datapath (tx_reset_pll_and_datapath), + .rx_resetdone (rx_resetdone), + .tx_resetdone (tx_resetdone), + + .gt_b_reset (gt_b_reset & gt_powergood), + .gt_b_reset_rx_datapath (rx_b_reset_datapath), + .gt_b_reset_tx_datapath (tx_b_reset_datapath), + .gt_b_reset_rx_pll_and_datapath (rx_b_reset_pll_and_datapath), + .gt_b_reset_tx_pll_and_datapath (tx_b_reset_pll_and_datapath), + .rx_b_resetdone (rx_b_resetdone), + .tx_b_resetdone (tx_b_resetdone), + + .ref_clk_a (ref_clk), + .ref_clk_b (ref_clk), + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), + .rx_b_device_clk (rx_device_clk), + .tx_b_device_clk (tx_device_clk), + + .data_in_p (hsci_do_p), + .data_in_n (hsci_do_n), + .clk_in_p (hsci_cko_p), + .clk_in_n (hsci_cko_n), + .data_out_p (hsci_din_p), + .data_out_n (hsci_din_n), + .clk_out_p (hsci_ckin_p), + .clk_out_n (hsci_ckin_n), + .intf_rdy (intf_rdy), + .fifo_empty (fifo_empty), + .fifo_rd_en (fifo_rd_en), + .hsci_data_out (hsci_data_out), + .hsci_data_in (hsci_data_in), + .data_from_fabric (data_from_fabric), + .data_to_fabric (data_to_fabric), + + .rx_sync_0 (rx_syncout[0]), + .tx_sync_0 (tx_syncin[0]), + .rx_sync_12 (rx_syncout[1]), + .tx_sync_12 (tx_syncin[1]), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref), + .rx_sysref_12 (sysref), + .tx_sysref_12 (sysref)); + + assign rx_data_p_loc = stx_p; + assign rx_data_n_loc = stx_n; + assign srx_p = tx_data_p_loc; + assign srx_n = tx_data_n_loc; + +endmodule diff --git a/projects/ad9084_ebz/vpk180/timing_constr.tcl b/projects/ad9084_ebz/vpk180/timing_constr.tcl new file mode 100755 index 00000000000..4bed408481f --- /dev/null +++ b/projects/ad9084_ebz/vpk180/timing_constr.tcl @@ -0,0 +1,79 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +# Primary clock definitions + +# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block +# Maximum values for Link clock: +# 204B - 15.5 Gbps /40 = 387.5MHz +# 204C - 24.75 Gbps /66 = 375MHz +set jesd_mode [get_env_param JESD_MODE 64B66B] +set link_mode [expr {$jesd_mode=="64B66B"?2:1}] +# set link_mode 1 + +set rx_lane_rate [get_env_param RX_LANE_RATE 20.625] +set tx_lane_rate [get_env_param TX_LANE_RATE 20.625] + +set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] +set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] + +set rx_link_clk_period [expr 1000/$rx_link_clk] +set tx_link_clk_period [expr 1000/$tx_link_clk] + +set rx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_jesd/rx/inst]] +set tx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_jesd/tx/inst]] +set rx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_jesd/rx/inst]] +set tx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_jesd/tx/inst]] + +set rx_device_clk [expr $rx_link_clk*$rx_ll_width/$rx_tpl_width] +set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width] +set rx_device_clk_period [expr 1000/$rx_device_clk] +set tx_device_clk_period [expr 1000/$tx_device_clk] + +set ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0] + +if {$ASYMMETRIC_A_B_MODE} { + set rx_b_lane_rate [get_env_param RX_B_LANE_RATE 20.625] + set tx_b_lane_rate [get_env_param TX_B_LANE_RATE 20.625] + + set rx_b_link_clk [expr $rx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]] + set tx_b_link_clk [expr $tx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]] + + set rx_b_link_clk_period [expr 1000/$rx_b_link_clk] + set tx_b_link_clk_period [expr 1000/$tx_b_link_clk] + + set rx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]] + set tx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]] + set rx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]] + set tx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]] + + set rx_b_device_clk [expr $rx_b_link_clk*$rx_b_ll_width/$rx_b_tpl_width] + set tx_b_device_clk [expr $tx_b_link_clk*$tx_b_ll_width/$tx_b_tpl_width] + set rx_b_device_clk_period [expr 1000/$rx_b_device_clk] + set tx_b_device_clk_period [expr 1000/$tx_b_device_clk] +} + +# refclk and refclk_replica are connect to the same source on the PCB +# Set reference clock to same frequency as the link clock, +# this will ease the XCVR out clocks propagation calculation. +# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE +create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p] + +# device clock +create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clk_m2c_p[0]] +create_clock -name tx_device_clk -period $tx_device_clk_period [get_ports clk_m2c_p[1]] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay -clock [get_clocks rx_device_clk] \ + [get_property PERIOD [get_clocks rx_device_clk]] \ + [get_ports {sysref_in*}] +set_input_delay -clock [get_clocks tx_device_clk] -add_delay\ + [get_property PERIOD [get_clocks tx_device_clk]] \ + [get_ports {sysref_in*}] + +set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous From 02079539e8c9f2abb7347d66cb3c9a34a8b75201 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Fri, 27 Jun 2025 13:58:35 +0200 Subject: [PATCH 02/15] ad9084_ebz/common: Use on source Allow to be sourced from testbench Signed-off-by: Jorge Marques --- projects/ad9084_ebz/common/ad9084_ebz_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl index 4d49deaf02b..c1294ee63c0 100755 --- a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl +++ b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl @@ -7,8 +7,8 @@ if {![info exists ADI_PHY_SEL]} { set ADI_PHY_SEL 1 } -source ../../../projects/common/xilinx/data_offload_bd.tcl -source ../../../library/jesd204/scripts/jesd204.tcl +source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl +source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl # Common parameter for TX and RX set JESD_MODE $ad_project_params(JESD_MODE) From 9a1e51ad932234af23eea8e72692b6fe780d7060 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Fri, 27 Jun 2025 14:21:25 +0200 Subject: [PATCH 03/15] fix: ad9084_ebz/common: Invalid hsci clock with ADI_PHY 1 Signed-off-by: Jorge Marques --- projects/ad9084_ebz/common/ad9084_ebz_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl index c1294ee63c0..dd65f858a9b 100755 --- a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl +++ b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl @@ -220,7 +220,7 @@ if {$HSCI_ENABLE} { ad_ip_parameter axi_hsci_clkgen CONFIG.VCO_MUL 8 ad_ip_parameter axi_hsci_clkgen CONFIG.CLK0_DIV 4 - ad_connect axi_ddr_cntrl/addn_ui_clkout1 axi_hsci_clkgen/clk + ad_connect $sys_cpu_clk axi_hsci_clkgen/clk ad_connect selectio_clk_in axi_hsci_clkgen/clk_0 } else { source ../common/versal_hsci_phy.tcl From 2ee96d62df0daf209a4a57a4c97e2bd15f0ee8d9 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Tue, 1 Jul 2025 15:52:51 +0200 Subject: [PATCH 04/15] apollo: spi: Set 4 wire spi through parameters Simplifies identifying which SPI are 4-wire or 3-wire. Also, for vck190, since the SPI interface only has 3 outputs, route adf4030 to the third. The adf4030 linux driver defaults to 4-wire, and 3-wire (datasheet default) can be set through devicetree property adi,spi-3wire-enable. Signed-off-by: Jorge Marques --- projects/ad9084_ebz/common/ad9084_ebz_spi.v | 15 +++++++++++++-- projects/ad9084_ebz/fm87/system_top.v | 3 ++- projects/ad9084_ebz/vck190/system_top.v | 8 +++++--- projects/ad9084_ebz/vcu118/system_top.v | 3 ++- projects/ad9084_ebz/vpk180/system_top.v | 3 ++- 5 files changed, 24 insertions(+), 8 deletions(-) diff --git a/projects/ad9084_ebz/common/ad9084_ebz_spi.v b/projects/ad9084_ebz/common/ad9084_ebz_spi.v index d50281113fd..9f26fee9e1a 100644 --- a/projects/ad9084_ebz/common/ad9084_ebz_spi.v +++ b/projects/ad9084_ebz/common/ad9084_ebz_spi.v @@ -36,7 +36,8 @@ `timescale 1ns/100ps module ad9084_ebz_spi #( - parameter NUM_OF_SLAVES = 8 + parameter NUM_OF_SLAVES = 8, + parameter IS_4WIRE = 8'b00000001 ) ( input [NUM_OF_SLAVES-1:0] spi_csn, input spi_clk, @@ -57,6 +58,8 @@ module ad9084_ebz_spi #( wire spi_csn_s; wire spi_enable_s; + wire [NUM_OF_SLAVES-1:0] spi_csn_4wire; + // check on rising edge and change on falling edge assign spi_csn_s = & spi_csn; @@ -86,7 +89,15 @@ module ad9084_ebz_spi #( // io buffer - assign spi_miso = (spi_csn[0] == 1'b0) ? spi_miso_in : spi_sdio; + genvar i; + + generate + for (i = 0; i < NUM_OF_SLAVES ; i = i + 1) begin + assign spi_csn_4wire[i] = (IS_4WIRE[i] == 1'b1) ? spi_csn[i] : 1'b1; + end + endgenerate + + assign spi_miso = (&spi_csn_4wire == 1'b0) ? spi_miso_in : spi_sdio; assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; endmodule \ No newline at end of file diff --git a/projects/ad9084_ebz/fm87/system_top.v b/projects/ad9084_ebz/fm87/system_top.v index 0baed7d092c..8b496f1d302 100644 --- a/projects/ad9084_ebz/fm87/system_top.v +++ b/projects/ad9084_ebz/fm87/system_top.v @@ -224,7 +224,8 @@ module system_top #( assign spi2_sclk = spi_clk; ad9084_ebz_spi #( - .NUM_OF_SLAVES(2) + .NUM_OF_SLAVES(2), + .IS_4WIRE(2'b01) ) i_spi ( .spi_csn (spi_csn[1:0]), .spi_clk (spi_clk), diff --git a/projects/ad9084_ebz/vck190/system_top.v b/projects/ad9084_ebz/vck190/system_top.v index 3bb4e25a935..e813cc3fb77 100755 --- a/projects/ad9084_ebz/vck190/system_top.v +++ b/projects/ad9084_ebz/vck190/system_top.v @@ -262,13 +262,15 @@ module system_top #( .O (tx_device_clk)); // spi - assign spi2_cs[5:0] = spi_csn[5:0]; + assign spi2_cs[1:0] = spi_csn[1:0]; + assign spi2_cs[4] = spi_csn[2]; assign spi2_sclk = spi_clk; ad9084_ebz_spi #( - .NUM_OF_SLAVES(2) + .NUM_OF_SLAVES(3), + .IS_4WIRE(3'b101) ) i_spi ( - .spi_csn (spi_csn[1:0]), + .spi_csn (spi_csn[2:0]), .spi_clk (spi_clk), .spi_mosi (spi_sdio), .spi_miso (spi_sdo), diff --git a/projects/ad9084_ebz/vcu118/system_top.v b/projects/ad9084_ebz/vcu118/system_top.v index 27000084add..bf38005d019 100755 --- a/projects/ad9084_ebz/vcu118/system_top.v +++ b/projects/ad9084_ebz/vcu118/system_top.v @@ -313,7 +313,8 @@ module system_top #( assign spi2_sclk = spi_clk; ad9084_ebz_spi #( - .NUM_OF_SLAVES(2) + .NUM_OF_SLAVES(2), + .IS_4WIRE(2'b01) ) i_spi ( .spi_csn (spi_csn[1:0]), .spi_clk (spi_clk), diff --git a/projects/ad9084_ebz/vpk180/system_top.v b/projects/ad9084_ebz/vpk180/system_top.v index e4271cee8f8..5343c9f6313 100755 --- a/projects/ad9084_ebz/vpk180/system_top.v +++ b/projects/ad9084_ebz/vpk180/system_top.v @@ -286,7 +286,8 @@ module system_top #( assign spi2_sclk = spi_clk; ad9084_ebz_spi #( - .NUM_OF_SLAVES(2) + .NUM_OF_SLAVES(2), + .IS_4WIRE(2'b01) ) i_spi ( .spi_csn (spi_csn[1:0]), .spi_clk (spi_clk), From 959c50c8aab89976ad7922731ca7d673797e8eb4 Mon Sep 17 00:00:00 2001 From: "Filip.Gherman" Date: Mon, 25 Aug 2025 17:49:33 +0300 Subject: [PATCH 05/15] ad9084_ebz/vcu118: Fix spi2 by adding a clear muxing logic between 3w/4w and unused slave devices Signed-off-by: Filip Gherman --- projects/ad9084_ebz/common/ad9084_ebz_spi.v | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/projects/ad9084_ebz/common/ad9084_ebz_spi.v b/projects/ad9084_ebz/common/ad9084_ebz_spi.v index 9f26fee9e1a..54256cb9fae 100644 --- a/projects/ad9084_ebz/common/ad9084_ebz_spi.v +++ b/projects/ad9084_ebz/common/ad9084_ebz_spi.v @@ -37,7 +37,7 @@ module ad9084_ebz_spi #( parameter NUM_OF_SLAVES = 8, - parameter IS_4WIRE = 8'b00000001 + parameter [NUM_OF_SLAVES-1:0] IS_4WIRE = 8'b00000001 ) ( input [NUM_OF_SLAVES-1:0] spi_csn, input spi_clk, @@ -58,7 +58,8 @@ module ad9084_ebz_spi #( wire spi_csn_s; wire spi_enable_s; - wire [NUM_OF_SLAVES-1:0] spi_csn_4wire; + wire any_4wire_sel; + wire any_3wire_sel; // check on rising edge and change on falling edge @@ -87,17 +88,11 @@ module ad9084_ebz_spi #( end end - // io buffer + assign any_4wire_sel = |(~spi_csn & IS_4WIRE); + assign any_3wire_sel = |(~spi_csn & ~IS_4WIRE); - genvar i; - - generate - for (i = 0; i < NUM_OF_SLAVES ; i = i + 1) begin - assign spi_csn_4wire[i] = (IS_4WIRE[i] == 1'b1) ? spi_csn[i] : 1'b1; - end - endgenerate - - assign spi_miso = (&spi_csn_4wire == 1'b0) ? spi_miso_in : spi_sdio; + assign spi_miso = (any_4wire_sel) ? spi_miso_in : + (any_3wire_sel) ? spi_sdio : 1'bz; assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; endmodule \ No newline at end of file From 27ce96b13880cee767862ecb4913d8f090d241aa Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Fri, 12 Sep 2025 15:44:56 +0300 Subject: [PATCH 06/15] projects: ad9084_ebz: Change spi to 3 wire Signed-off-by: Bogdan Luncan --- projects/ad9084_ebz/common/ad9084_ebz_spi.v | 98 ------------------- projects/ad9084_ebz/fm87/Makefile | 1 - projects/ad9084_ebz/fm87/system_project.tcl | 1 - projects/ad9084_ebz/fm87/system_top.v | 6 +- projects/ad9084_ebz/vck190/Makefile | 2 +- projects/ad9084_ebz/vck190/system_project.tcl | 2 +- projects/ad9084_ebz/vck190/system_top.v | 6 +- projects/ad9084_ebz/vcu118/Makefile | 2 +- projects/ad9084_ebz/vcu118/system_project.tcl | 2 +- projects/ad9084_ebz/vcu118/system_top.v | 8 +- projects/ad9084_ebz/vpk180/Makefile | 2 +- projects/ad9084_ebz/vpk180/system_project.tcl | 4 +- projects/ad9084_ebz/vpk180/system_top.v | 8 +- 13 files changed, 17 insertions(+), 125 deletions(-) delete mode 100644 projects/ad9084_ebz/common/ad9084_ebz_spi.v diff --git a/projects/ad9084_ebz/common/ad9084_ebz_spi.v b/projects/ad9084_ebz/common/ad9084_ebz_spi.v deleted file mode 100644 index 54256cb9fae..00000000000 --- a/projects/ad9084_ebz/common/ad9084_ebz_spi.v +++ /dev/null @@ -1,98 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad9084_ebz_spi #( - parameter NUM_OF_SLAVES = 8, - parameter [NUM_OF_SLAVES-1:0] IS_4WIRE = 8'b00000001 -) ( - input [NUM_OF_SLAVES-1:0] spi_csn, - input spi_clk, - input spi_mosi, - output spi_miso, - input spi_miso_in, - inout spi_sdio -); - - // internal registers - - reg [ 5:0] spi_count = 'd0; - reg spi_rd_wr_n = 'd0; - reg spi_enable = 'd0; - - // internal signals - - wire spi_csn_s; - wire spi_enable_s; - - wire any_4wire_sel; - wire any_3wire_sel; - - // check on rising edge and change on falling edge - - assign spi_csn_s = & spi_csn; - assign spi_enable_s = spi_enable & ~spi_csn_s; - - always @(posedge spi_clk or posedge spi_csn_s) begin - if (spi_csn_s == 1'b1) begin - spi_count <= 6'd0; - spi_rd_wr_n <= 1'd0; - end else begin - spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count; - if (spi_count == 6'd0) begin - spi_rd_wr_n <= spi_mosi; - end - end - end - - always @(negedge spi_clk or posedge spi_csn_s) begin - if (spi_csn_s == 1'b1) begin - spi_enable <= 1'b0; - end else begin - if (spi_count == 6'd16) begin - spi_enable <= spi_rd_wr_n; - end - end - end - - assign any_4wire_sel = |(~spi_csn & IS_4WIRE); - assign any_3wire_sel = |(~spi_csn & ~IS_4WIRE); - - assign spi_miso = (any_4wire_sel) ? spi_miso_in : - (any_3wire_sel) ? spi_sdio : 1'bz; - assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; - -endmodule \ No newline at end of file diff --git a/projects/ad9084_ebz/fm87/Makefile b/projects/ad9084_ebz/fm87/Makefile index 39053d8cdff..bd07882ca63 100755 --- a/projects/ad9084_ebz/fm87/Makefile +++ b/projects/ad9084_ebz/fm87/Makefile @@ -6,7 +6,6 @@ PROJECT_NAME := ad9084_ebz_fm87 -M_DEPS += ../common/ad9084_ebz_spi.v M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/intel/adcfifo_qsys.tcl M_DEPS += ../../common/fm87/system_qsys.tcl diff --git a/projects/ad9084_ebz/fm87/system_project.tcl b/projects/ad9084_ebz/fm87/system_project.tcl index 884eb5b2670..95db30d3ee2 100644 --- a/projects/ad9084_ebz/fm87/system_project.tcl +++ b/projects/ad9084_ebz/fm87/system_project.tcl @@ -70,7 +70,6 @@ source $ad_hdl_dir/projects/common/fm87/fm87_plddr_system_assign.tcl set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_3w_spi.v set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v set_global_assignment -name VERILOG_FILE $ad_hdl_dir/projects/common/fm87/gpio_slave.v -set_global_assignment -name VERILOG_FILE ../common/ad9084_ebz_spi.v set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to fpga_refclk_in set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to syncinb_a0 diff --git a/projects/ad9084_ebz/fm87/system_top.v b/projects/ad9084_ebz/fm87/system_top.v index 8b496f1d302..e84a4f80f21 100644 --- a/projects/ad9084_ebz/fm87/system_top.v +++ b/projects/ad9084_ebz/fm87/system_top.v @@ -223,15 +223,13 @@ module system_top #( assign spi2_cs[5:0] = spi_csn[5:0]; assign spi2_sclk = spi_clk; - ad9084_ebz_spi #( - .NUM_OF_SLAVES(2), - .IS_4WIRE(2'b01) + ad_3w_spi #( + .NUM_OF_SLAVES(2) ) i_spi ( .spi_csn (spi_csn[1:0]), .spi_clk (spi_clk), .spi_mosi (spi_sdio), .spi_miso (spi_sdo), - .spi_miso_in (spi2_sdo), .spi_sdio (spi2_sdio)); assign dut_csb = apollo_spi_csn[0]; diff --git a/projects/ad9084_ebz/vck190/Makefile b/projects/ad9084_ebz/vck190/Makefile index 9c8951c93fe..23c3c73d63a 100755 --- a/projects/ad9084_ebz/vck190/Makefile +++ b/projects/ad9084_ebz/vck190/Makefile @@ -8,7 +8,6 @@ PROJECT_NAME := ad9084_ebz_vck190 M_DEPS += ../common/versal_transceiver.tcl M_DEPS += ../common/versal_hsci_phy.tcl -M_DEPS += ../common/ad9084_ebz_spi.v M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/xilinx/dacfifo_bd.tcl M_DEPS += ../../common/xilinx/adcfifo_bd.tcl @@ -19,6 +18,7 @@ M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_bd.tcl M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v M_DEPS += ../../../projects/common/xilinx/data_offload_bd.tcl M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl diff --git a/projects/ad9084_ebz/vck190/system_project.tcl b/projects/ad9084_ebz/vck190/system_project.tcl index 34de1e17efc..f6623ffd102 100755 --- a/projects/ad9084_ebz/vck190/system_project.tcl +++ b/projects/ad9084_ebz/vck190/system_project.tcl @@ -78,8 +78,8 @@ adi_project_files ad9084_ebz_vck190 [list \ "system_constr.xdc" \ "timing_constr.tcl" \ "../common/versal_hsci_phy.tcl" \ - "../common/ad9084_ebz_spi.v" \ "../common/versal_transceiver.tcl" \ + "$ad_hdl_dir/library/common/ad_3w_spi.v" \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc" ] diff --git a/projects/ad9084_ebz/vck190/system_top.v b/projects/ad9084_ebz/vck190/system_top.v index e813cc3fb77..42baae8e419 100755 --- a/projects/ad9084_ebz/vck190/system_top.v +++ b/projects/ad9084_ebz/vck190/system_top.v @@ -266,15 +266,13 @@ module system_top #( assign spi2_cs[4] = spi_csn[2]; assign spi2_sclk = spi_clk; - ad9084_ebz_spi #( - .NUM_OF_SLAVES(3), - .IS_4WIRE(3'b101) + ad_3w_spi #( + .NUM_OF_SLAVES(3) ) i_spi ( .spi_csn (spi_csn[2:0]), .spi_clk (spi_clk), .spi_mosi (spi_sdio), .spi_miso (spi_sdo), - .spi_miso_in (spi2_sdo), .spi_sdio (spi2_sdio)); assign dut_csb = apollo_spi_csn[0]; diff --git a/projects/ad9084_ebz/vcu118/Makefile b/projects/ad9084_ebz/vcu118/Makefile index 16d78ecab6e..5dcac75a029 100755 --- a/projects/ad9084_ebz/vcu118/Makefile +++ b/projects/ad9084_ebz/vcu118/Makefile @@ -8,7 +8,6 @@ PROJECT_NAME := ad9084_ebz_vcu118 M_DEPS += timing_constr.xdc M_DEPS += ../common/versal_hsci_phy.tcl -M_DEPS += ../common/ad9084_ebz_spi.v M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/xilinx/dacfifo_bd.tcl M_DEPS += ../../common/xilinx/adcfifo_bd.tcl @@ -19,6 +18,7 @@ M_DEPS += ../../../library/xilinx/common/ad_rst_constr.xdc M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl M_DEPS += ../../../library/common/ad_rst.v M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v M_DEPS += ../../../projects/common/xilinx/data_offload_bd.tcl M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl diff --git a/projects/ad9084_ebz/vcu118/system_project.tcl b/projects/ad9084_ebz/vcu118/system_project.tcl index 0ca801cecc6..4c761cea8c3 100755 --- a/projects/ad9084_ebz/vcu118/system_project.tcl +++ b/projects/ad9084_ebz/vcu118/system_project.tcl @@ -76,9 +76,9 @@ adi_project_files ad9084_ebz_vcu118 [list \ "system_constr.xdc"\ "timing_constr.xdc"\ "../common/hsci_phy_top.sv"\ - "../common/ad9084_ebz_spi.v"\ "$ad_hdl_dir/library/common/ad_rst.v"\ "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_3w_spi.v" \ "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc"\ "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ] create_ip -name high_speed_selectio_wiz -vendor xilinx.com -library ip -version 3.6 -module_name high_speed_selectio_wiz_0 diff --git a/projects/ad9084_ebz/vcu118/system_top.v b/projects/ad9084_ebz/vcu118/system_top.v index bf38005d019..189ef4cc34a 100755 --- a/projects/ad9084_ebz/vcu118/system_top.v +++ b/projects/ad9084_ebz/vcu118/system_top.v @@ -312,15 +312,13 @@ module system_top #( assign spi2_cs[5:0] = spi_csn[5:0]; assign spi2_sclk = spi_clk; - ad9084_ebz_spi #( - .NUM_OF_SLAVES(2), - .IS_4WIRE(2'b01) + ad_3w_spi #( + .NUM_OF_SLAVES(3) ) i_spi ( - .spi_csn (spi_csn[1:0]), + .spi_csn (spi_csn[2:0]), .spi_clk (spi_clk), .spi_mosi (spi_sdio), .spi_miso (spi_sdo), - .spi_miso_in (spi2_sdo), .spi_sdio (spi2_sdio)); assign dut_csb = apollo_spi_csn[0]; diff --git a/projects/ad9084_ebz/vpk180/Makefile b/projects/ad9084_ebz/vpk180/Makefile index f5a3580db6f..30c02fb36e4 100755 --- a/projects/ad9084_ebz/vpk180/Makefile +++ b/projects/ad9084_ebz/vpk180/Makefile @@ -8,7 +8,6 @@ PROJECT_NAME := ad9084_ebz_vpk180 M_DEPS += ../common/versal_transceiver.tcl M_DEPS += ../common/versal_hsci_phy.tcl -M_DEPS += ../common/ad9084_ebz_spi.v M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/xilinx/dacfifo_bd.tcl M_DEPS += ../../common/xilinx/adcfifo_bd.tcl @@ -18,6 +17,7 @@ M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_bd.tcl M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v M_DEPS += ../../../projects/common/xilinx/data_offload_bd.tcl M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl diff --git a/projects/ad9084_ebz/vpk180/system_project.tcl b/projects/ad9084_ebz/vpk180/system_project.tcl index 538858a7d4a..b2d8e8785ef 100755 --- a/projects/ad9084_ebz/vpk180/system_project.tcl +++ b/projects/ad9084_ebz/vpk180/system_project.tcl @@ -77,9 +77,9 @@ adi_project_files ad9084_ebz_vpk180 [list \ "system_top.v" \ "system_constr.xdc" \ "timing_constr.tcl" \ - "../common/ad9084_ebz_spi.v" \ - "../common/versal_transceiver.tcl" \ "../common/versal_hsci_phy.tcl" \ + "../common/versal_transceiver.tcl" \ + "$ad_hdl_dir/library/common/ad_3w_spi.v" \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vpk180/vpk180_system_constr.xdc" ] diff --git a/projects/ad9084_ebz/vpk180/system_top.v b/projects/ad9084_ebz/vpk180/system_top.v index 5343c9f6313..4c01e13a8e1 100755 --- a/projects/ad9084_ebz/vpk180/system_top.v +++ b/projects/ad9084_ebz/vpk180/system_top.v @@ -285,15 +285,13 @@ module system_top #( assign spi2_cs[5:0] = spi_csn[5:0]; assign spi2_sclk = spi_clk; - ad9084_ebz_spi #( - .NUM_OF_SLAVES(2), - .IS_4WIRE(2'b01) + ad_3w_spi #( + .NUM_OF_SLAVES(3) ) i_spi ( - .spi_csn (spi_csn[1:0]), + .spi_csn (spi_csn[2:0]), .spi_clk (spi_clk), .spi_mosi (spi_sdio), .spi_miso (spi_sdo), - .spi_miso_in (spi2_sdo), .spi_sdio (spi2_sdio)); assign dut_csb = apollo_spi_csn[0]; From fc679fc36a58c233038bec14ac177c6f2bbcbf49 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Fri, 26 Sep 2025 10:49:08 +0300 Subject: [PATCH 07/15] projects: ad9084_ebz: common: ad9084_ebz_bd.tcl: Migrate to inline utility cores Signed-off-by: Bogdan Luncan --- projects/ad9084_ebz/common/ad9084_ebz_bd.tcl | 32 ++++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl index dd65f858a9b..8e76871cdce 100755 --- a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl +++ b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl @@ -263,7 +263,7 @@ if {$HSCI_ENABLE} { ad_connect hsci_phy/t_data_out GND ad_connect hsci_phy/t_clk_out GND - ad_ip_instance xlconcat hsci_pll_locked_concat [list \ + ad_ip_instance ilconcat hsci_pll_locked_concat [list \ NUM_PORTS ${HSCI_BANKS} \ ] ad_connect hsci_pll_locked_concat/In0 hsci_phy/bank0_pll_locked @@ -391,10 +391,10 @@ if {$ADI_PHY_SEL} { ad_connect tx_resetdone jesd204_phy/tx_resetdone # gt powergood - ad_ip_instance xlconcat gt_powergood_concat [list \ + ad_ip_instance ilconcat gt_powergood_concat [list \ NUM_PORTS 2 \ ] - ad_ip_instance util_reduced_logic gt_powergood_and [list \ + ad_ip_instance ilreduced_logic gt_powergood_and [list \ C_SIZE $num_quads \ ] ad_connect jesd204_phy/gtpowergood gt_powergood_concat/In0 @@ -1076,7 +1076,7 @@ ad_connect ext_sync_in rx_apollo_tpl_core/adc_tpl_core/adc_sync_in ad_ip_parameter tx_apollo_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1 ad_connect ext_sync_in tx_apollo_tpl_core/dac_tpl_core/dac_sync_in -ad_ip_instance util_vector_logic manual_sync_or [list \ +ad_ip_instance ilvector_logic manual_sync_or [list \ C_SIZE 1 \ C_OPERATION {or} \ ] @@ -1096,7 +1096,7 @@ if {$ASYMMETRIC_A_B_MODE == 0} { ad_ip_parameter tx_b_apollo_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1 ad_connect ext_sync_in tx_b_apollo_tpl_core/dac_tpl_core/dac_sync_in - ad_ip_instance util_vector_logic manual_sync_or_b [list \ + ad_ip_instance ilvector_logic manual_sync_or_b [list \ C_SIZE 1 \ C_OPERATION {or} \ ] @@ -1104,7 +1104,7 @@ if {$ASYMMETRIC_A_B_MODE == 0} { ad_connect rx_b_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or_b/Op1 ad_connect tx_b_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or_b/Op2 - ad_ip_instance util_vector_logic manual_sync_or_res [list \ + ad_ip_instance ilvector_logic manual_sync_or_res [list \ C_SIZE 1 \ C_OPERATION {or} \ ] @@ -1119,17 +1119,17 @@ if {$ASYMMETRIC_A_B_MODE == 0} { } # Reset pack cores -ad_ip_instance util_reduced_logic cpack_rst_logic +ad_ip_instance ilreduced_logic cpack_rst_logic ad_ip_parameter cpack_rst_logic config.c_operation {or} ad_ip_parameter cpack_rst_logic config.c_size {3} -ad_ip_instance util_vector_logic rx_do_rstout_logic +ad_ip_instance ilvector_logic rx_do_rstout_logic ad_ip_parameter rx_do_rstout_logic config.c_operation {not} ad_ip_parameter rx_do_rstout_logic config.c_size {1} ad_connect $adc_data_offload_name/s_axis_tready rx_do_rstout_logic/Op1 -ad_ip_instance xlconcat cpack_reset_sources +ad_ip_instance ilconcat cpack_reset_sources ad_ip_parameter cpack_reset_sources config.num_ports {3} ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0 ad_connect rx_apollo_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1 @@ -1139,17 +1139,17 @@ ad_connect cpack_reset_sources/dout cpack_rst_logic/op1 ad_connect cpack_rst_logic/res util_apollo_cpack/reset if {$ASYMMETRIC_A_B_MODE} { - ad_ip_instance util_reduced_logic cpack_b_rst_logic + ad_ip_instance ilreduced_logic cpack_b_rst_logic ad_ip_parameter cpack_b_rst_logic config.c_operation {or} ad_ip_parameter cpack_b_rst_logic config.c_size {3} - ad_ip_instance util_vector_logic rx_b_do_rstout_logic + ad_ip_instance ilvector_logic rx_b_do_rstout_logic ad_ip_parameter rx_b_do_rstout_logic config.c_operation {not} ad_ip_parameter rx_b_do_rstout_logic config.c_size {1} ad_connect $adc_b_data_offload_name/s_axis_tready rx_b_do_rstout_logic/Op1 - ad_ip_instance xlconcat cpack_b_reset_sources + ad_ip_instance ilconcat cpack_b_reset_sources ad_ip_parameter cpack_b_reset_sources config.num_ports {3} ad_connect rx_b_device_clk_rstgen/peripheral_reset cpack_b_reset_sources/in0 ad_connect rx_b_apollo_tpl_core/adc_tpl_core/adc_rst cpack_b_reset_sources/in1 @@ -1160,11 +1160,11 @@ if {$ASYMMETRIC_A_B_MODE} { } # Reset unpack cores -ad_ip_instance util_reduced_logic upack_rst_logic +ad_ip_instance ilreduced_logic upack_rst_logic ad_ip_parameter upack_rst_logic config.c_operation {or} ad_ip_parameter upack_rst_logic config.c_size {2} -ad_ip_instance xlconcat upack_reset_sources +ad_ip_instance ilconcat upack_reset_sources ad_ip_parameter upack_reset_sources config.num_ports {2} ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0 ad_connect tx_apollo_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1 @@ -1173,11 +1173,11 @@ ad_connect upack_reset_sources/dout upack_rst_logic/op1 ad_connect upack_rst_logic/res util_apollo_upack/reset if {$ASYMMETRIC_A_B_MODE} { - ad_ip_instance util_reduced_logic upack_b_rst_logic + ad_ip_instance ilreduced_logic upack_b_rst_logic ad_ip_parameter upack_b_rst_logic config.c_operation {or} ad_ip_parameter upack_b_rst_logic config.c_size {2} - ad_ip_instance xlconcat upack_b_reset_sources + ad_ip_instance ilconcat upack_b_reset_sources ad_ip_parameter upack_b_reset_sources config.num_ports {2} ad_connect tx_b_device_clk_rstgen/peripheral_reset upack_b_reset_sources/in0 ad_connect tx_b_apollo_tpl_core/dac_tpl_core/dac_rst upack_b_reset_sources/in1 From 6ea8862e0a0dffbb9d1053caa5be6dfb49435dac Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Fri, 26 Sep 2025 11:18:52 +0300 Subject: [PATCH 08/15] projects: ad9084_ebz: versal: Update constraints to read the lane rate automatically Signed-off-by: Bogdan Luncan --- projects/ad9084_ebz/vck190/timing_constr.tcl | 32 +++--------------- projects/ad9084_ebz/vpk180/timing_constr.tcl | 35 +++----------------- 2 files changed, 9 insertions(+), 58 deletions(-) diff --git a/projects/ad9084_ebz/vck190/timing_constr.tcl b/projects/ad9084_ebz/vck190/timing_constr.tcl index e7a80589472..58ea6fef0ae 100755 --- a/projects/ad9084_ebz/vck190/timing_constr.tcl +++ b/projects/ad9084_ebz/vck190/timing_constr.tcl @@ -3,18 +3,17 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source ../../../scripts/adi_env.tcl # Primary clock definitions # Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block # Maximum values for Link clock: # 204B - 15.5 Gbps /40 = 387.5MHz # 204C - 24.75 Gbps /66 = 375MHz -set jesd_mode [get_env_param JESD_MODE 64B66B] -set link_mode [expr {$jesd_mode=="64B66B"?2:1}] +set jesd_mode [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] INTERNAL_PRESET] +set link_mode [expr {$jesd_mode=="JESD204_64B66B" ? 2:1}] -set rx_lane_rate [get_env_param RX_LANE_RATE 20.625] -set tx_lane_rate [get_env_param TX_LANE_RATE 20.625] +set rx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] RX_LINE_RATE] +set tx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] TX_LINE_RATE] set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] @@ -32,29 +31,6 @@ set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width] set rx_device_clk_period [expr 1000/$rx_device_clk] set tx_device_clk_period [expr 1000/$tx_device_clk] -set ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0] - -if {$ASYMMETRIC_A_B_MODE} { - set rx_b_lane_rate [get_env_param RX_B_LANE_RATE 20.625] - set tx_b_lane_rate [get_env_param TX_B_LANE_RATE 20.625] - - set rx_b_link_clk [expr $rx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]] - set tx_b_link_clk [expr $tx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]] - - set rx_b_link_clk_period [expr 1000/$rx_b_link_clk] - set tx_b_link_clk_period [expr 1000/$tx_b_link_clk] - - set rx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]] - set tx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]] - set rx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]] - set tx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]] - - set rx_b_device_clk [expr $rx_b_link_clk*$rx_b_ll_width/$rx_b_tpl_width] - set tx_b_device_clk [expr $tx_b_link_clk*$tx_b_ll_width/$tx_b_tpl_width] - set rx_b_device_clk_period [expr 1000/$rx_b_device_clk] - set tx_b_device_clk_period [expr 1000/$tx_b_device_clk] -} - # refclk and refclk_replica are connect to the same source on the PCB # Set reference clock to same frequency as the link clock, # this will ease the XCVR out clocks propagation calculation. diff --git a/projects/ad9084_ebz/vpk180/timing_constr.tcl b/projects/ad9084_ebz/vpk180/timing_constr.tcl index 4bed408481f..58ea6fef0ae 100755 --- a/projects/ad9084_ebz/vpk180/timing_constr.tcl +++ b/projects/ad9084_ebz/vpk180/timing_constr.tcl @@ -3,19 +3,17 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source ../../../scripts/adi_env.tcl # Primary clock definitions # Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block # Maximum values for Link clock: # 204B - 15.5 Gbps /40 = 387.5MHz # 204C - 24.75 Gbps /66 = 375MHz -set jesd_mode [get_env_param JESD_MODE 64B66B] -set link_mode [expr {$jesd_mode=="64B66B"?2:1}] -# set link_mode 1 +set jesd_mode [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] INTERNAL_PRESET] +set link_mode [expr {$jesd_mode=="JESD204_64B66B" ? 2:1}] -set rx_lane_rate [get_env_param RX_LANE_RATE 20.625] -set tx_lane_rate [get_env_param TX_LANE_RATE 20.625] +set rx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] RX_LINE_RATE] +set tx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] TX_LINE_RATE] set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] @@ -33,34 +31,11 @@ set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width] set rx_device_clk_period [expr 1000/$rx_device_clk] set tx_device_clk_period [expr 1000/$tx_device_clk] -set ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0] - -if {$ASYMMETRIC_A_B_MODE} { - set rx_b_lane_rate [get_env_param RX_B_LANE_RATE 20.625] - set tx_b_lane_rate [get_env_param TX_B_LANE_RATE 20.625] - - set rx_b_link_clk [expr $rx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]] - set tx_b_link_clk [expr $tx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]] - - set rx_b_link_clk_period [expr 1000/$rx_b_link_clk] - set tx_b_link_clk_period [expr 1000/$tx_b_link_clk] - - set rx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]] - set tx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]] - set rx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]] - set tx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]] - - set rx_b_device_clk [expr $rx_b_link_clk*$rx_b_ll_width/$rx_b_tpl_width] - set tx_b_device_clk [expr $tx_b_link_clk*$tx_b_ll_width/$tx_b_tpl_width] - set rx_b_device_clk_period [expr 1000/$rx_b_device_clk] - set tx_b_device_clk_period [expr 1000/$tx_b_device_clk] -} - # refclk and refclk_replica are connect to the same source on the PCB # Set reference clock to same frequency as the link clock, # this will ease the XCVR out clocks propagation calculation. # TODO: this restricts RX_LANE_RATE=TX_LANE_RATE -create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p] +create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p[0]] # device clock create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clk_m2c_p[0]] From cb71a9d0cca25d225118dda45fb7f7338535bea1 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Fri, 26 Sep 2025 13:33:47 +0300 Subject: [PATCH 09/15] projects: ad9084_ebz: Add readme file Signed-off-by: Bogdan Luncan --- projects/ad9084_ebz/README.md | 15 +++++++++++ projects/ad9084_ebz/fm87/README.md | 35 +++++++++++++++++++++++++ projects/ad9084_ebz/vck190/README.md | 39 ++++++++++++++++++++++++++++ projects/ad9084_ebz/vcu118/README.md | 38 +++++++++++++++++++++++++++ projects/ad9084_ebz/vpk180/README.md | 39 ++++++++++++++++++++++++++++ 5 files changed, 166 insertions(+) create mode 100644 projects/ad9084_ebz/README.md create mode 100644 projects/ad9084_ebz/fm87/README.md create mode 100644 projects/ad9084_ebz/vck190/README.md create mode 100644 projects/ad9084_ebz/vcu118/README.md create mode 100644 projects/ad9084_ebz/vpk180/README.md diff --git a/projects/ad9084_ebz/README.md b/projects/ad9084_ebz/README.md new file mode 100644 index 00000000000..f68bead2cbc --- /dev/null +++ b/projects/ad9084_ebz/README.md @@ -0,0 +1,15 @@ +# AD9084-EBZ HDL Project + +- Evaluation board product page: [EVAL-AD9084](https://www.analog.com/eval-ad9084) +- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad9084_ebz/index.html +- Evaluation board VADJ range: 1.2V - 3.3V + +## Supported parts + +| Part name | Description | +|------------------------------------------------|--------------------------------------------------------------| +| [AD9084 (Apollo MxFE)](https://www.analog.com/ad9084) | Quad, 16-Bit 28GSPS RF DAC and Quad 12-Bit, 20GSPS RF ADC | + +## Building the project + +Please enter the folder for the FPGA carrier you want to use and read the README.md. diff --git a/projects/ad9084_ebz/fm87/README.md b/projects/ad9084_ebz/fm87/README.md new file mode 100644 index 00000000000..7c524e54cd9 --- /dev/null +++ b/projects/ad9084_ebz/fm87/README.md @@ -0,0 +1,35 @@ + + +# AD9084-EBZ/FM87 HDL Project + +- VADJ with which it was tested in hardware: 1.2V + +## Building the project + +The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration. + +:warning: **When changing the default configuration, the system_constr.sdc constraints should be updated as well!** + +``` +cd projects/ad9084_ebz/fm87 +make +``` + +All of the RX/TX link modes can be found in the [AD9084 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad9084-ug-2326.pdf). We offer support for only a few of them. + +The overwritable parameters from the environment are: + +- JESD_MODE : Used link layer encoder mode + - 64B66B - 64b66b link layer defined in JESD 204C + - 8B10B - 8b10b link layer defined in JESD 204B +- +- REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B +- DEVICE_CLK_RATE : Device clock frequency in MHz, usually the same as REF_CLK_RATE but it can vary based on the JESD configuration +- ENABLE_HSCI : If set, adds and enables the HSCI core in the design +- RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +- TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +- [RX/TX]_JESD_M : Number of converters per link +- [RX/TX]_JESD_L : Number of lanes per link +- [RX/TX]_JESD_NP : Number of bits per sample +- [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) diff --git a/projects/ad9084_ebz/vck190/README.md b/projects/ad9084_ebz/vck190/README.md new file mode 100644 index 00000000000..d59c601bb06 --- /dev/null +++ b/projects/ad9084_ebz/vck190/README.md @@ -0,0 +1,39 @@ + + +# AD9084-EBZ/VCK190 HDL Project + +- VADJ with which it was tested in hardware: 1.5V + +## Building the project + +The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration. + +``` +cd projects/ad9084_ebz/vck190 +make +``` + +All of the RX/TX link modes can be found in the [AD9084 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad9084-ug-2326.pdf). We offer support for only a few of them. + +The overwritable parameters from the environment are: + +- JESD_MODE : Used link layer encoder mode + - 64B66B - 64b66b link layer defined in JESD 204C + - 8B10B - 8b10b link layer defined in JESD 204B +- +- REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B +- HSCI_ENABLE : If set, adds and enables the HSCI core in the design +- RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +- TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +- [RX/TX]_JESD_M : Number of converters per link +- [RX/TX]_JESD_L : Number of lanes per link +- [RX/TX]_JESD_NP : Number of bits per sample +- [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) +- ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link +- RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side +- TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side +- [RX/TX]_B_JESD_M : Number of converters per link for B side +- [RX/TX]_B_JESD_L : Number of lanes per link for B side +- [RX/TX]_B_JESD_NP : Number of bits per sample for B side +- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side diff --git a/projects/ad9084_ebz/vcu118/README.md b/projects/ad9084_ebz/vcu118/README.md new file mode 100644 index 00000000000..c68e5da1775 --- /dev/null +++ b/projects/ad9084_ebz/vcu118/README.md @@ -0,0 +1,38 @@ + + +# AD9084-EBZ/VCU118 HDL Project + +- VADJ with which it was tested in hardware: 1.8V + +## Building the project + +The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration. + +``` +cd projects/ad9084_ebz/vcu118 +make +``` + +All of the RX/TX link modes can be found in the [AD9084 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad9084-ug-2326.pdf). We offer support for only a few of them. + +The overwritable parameters from the environment are: + +- JESD_MODE : Used link layer encoder mode + - 64B66B - 64b66b link layer defined in JESD 204C + - 8B10B - 8b10b link layer defined in JESD 204B +- +- REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B +- RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +- TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +- [RX/TX]_JESD_M : Number of converters per link +- [RX/TX]_JESD_L : Number of lanes per link +- [RX/TX]_JESD_NP : Number of bits per sample +- [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) +- ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link +- RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side +- TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side +- [RX/TX]_B_JESD_M : Number of converters per link for B side +- [RX/TX]_B_JESD_L : Number of lanes per link for B side +- [RX/TX]_B_JESD_NP : Number of bits per sample for B side +- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side diff --git a/projects/ad9084_ebz/vpk180/README.md b/projects/ad9084_ebz/vpk180/README.md new file mode 100644 index 00000000000..4fe4323371e --- /dev/null +++ b/projects/ad9084_ebz/vpk180/README.md @@ -0,0 +1,39 @@ + + +# AD9084-EBZ/VPK180 HDL Project + +- VADJ with which it was tested in hardware: 1.5V + +## Building the project + +The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration. + +``` +cd projects/ad9084_ebz/vpk180 +make +``` + +All of the RX/TX link modes can be found in the [AD9084 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad9084-ug-2326.pdf). We offer support for only a few of them. + +The overwritable parameters from the environment are: + +- JESD_MODE : Used link layer encoder mode + - 64B66B - 64b66b link layer defined in JESD 204C + - 8B10B - 8b10b link layer defined in JESD 204B +- +- REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B +- HSCI_ENABLE : If set, adds and enables the HSCI core in the design +- RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +- TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +- [RX/TX]_JESD_M : Number of converters per link +- [RX/TX]_JESD_L : Number of lanes per link +- [RX/TX]_JESD_NP : Number of bits per sample +- [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) +- ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link +- RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side +- TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side +- [RX/TX]_B_JESD_M : Number of converters per link for B side +- [RX/TX]_B_JESD_L : Number of lanes per link for B side +- [RX/TX]_B_JESD_NP : Number of bits per sample for B side +- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side From 7c8c2c49fcb7bfad915093bce5ef5de66ac7f745 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Fri, 26 Sep 2025 13:43:10 +0300 Subject: [PATCH 10/15] projects: ad9084_ebz: fm87: system_project: Remove unused parameters from description Signed-off-by: Bogdan Luncan --- projects/ad9084_ebz/fm87/README.md | 2 +- projects/ad9084_ebz/fm87/system_project.tcl | 9 --------- projects/ad9084_ebz/vck190/README.md | 2 +- projects/ad9084_ebz/vcu118/README.md | 2 +- projects/ad9084_ebz/vpk180/README.md | 2 +- 5 files changed, 4 insertions(+), 13 deletions(-) diff --git a/projects/ad9084_ebz/fm87/README.md b/projects/ad9084_ebz/fm87/README.md index 7c524e54cd9..bca5b629bcd 100644 --- a/projects/ad9084_ebz/fm87/README.md +++ b/projects/ad9084_ebz/fm87/README.md @@ -1,4 +1,4 @@ - + # AD9084-EBZ/FM87 HDL Project diff --git a/projects/ad9084_ebz/fm87/system_project.tcl b/projects/ad9084_ebz/fm87/system_project.tcl index 95db30d3ee2..69ad97333d5 100644 --- a/projects/ad9084_ebz/fm87/system_project.tcl +++ b/projects/ad9084_ebz/fm87/system_project.tcl @@ -31,15 +31,6 @@ source ../../../projects/scripts/adi_project_intel.tcl # [RX/TX]_JESD_NP : Number of bits per sample # [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0 # [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) -# ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link -# RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side -# TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side -# [RX/TX]_B_JESD_M : Number of converters per link for B side -# [RX/TX]_B_JESD_L : Number of lanes per link for B side -# [RX/TX]_B_JESD_NP : Number of bits per sample for B side -# [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side -# -# !!! Requires the following hdl branch: https://github.com/analogdevicesinc/hdl/tree/dev_fm87_avlfifo # adi_project ad9084_ebz_fm87 [list \ diff --git a/projects/ad9084_ebz/vck190/README.md b/projects/ad9084_ebz/vck190/README.md index d59c601bb06..a7bbf6ecac8 100644 --- a/projects/ad9084_ebz/vck190/README.md +++ b/projects/ad9084_ebz/vck190/README.md @@ -1,4 +1,4 @@ - + # AD9084-EBZ/VCK190 HDL Project diff --git a/projects/ad9084_ebz/vcu118/README.md b/projects/ad9084_ebz/vcu118/README.md index c68e5da1775..366a474af02 100644 --- a/projects/ad9084_ebz/vcu118/README.md +++ b/projects/ad9084_ebz/vcu118/README.md @@ -1,4 +1,4 @@ - + # AD9084-EBZ/VCU118 HDL Project diff --git a/projects/ad9084_ebz/vpk180/README.md b/projects/ad9084_ebz/vpk180/README.md index 4fe4323371e..9cb5be9f8c2 100644 --- a/projects/ad9084_ebz/vpk180/README.md +++ b/projects/ad9084_ebz/vpk180/README.md @@ -1,4 +1,4 @@ - + # AD9084-EBZ/VPK180 HDL Project From c1cc0c6c72477fdfeed3c831d43e197d4048bc83 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Wed, 3 Sep 2025 10:30:13 +0300 Subject: [PATCH 11/15] projects: ad9084_ebz: versal: Update to the new Transceiver Subsystem Signed-off-by: Bogdan Luncan --- projects/ad9084_ebz/common/ad9084_ebz_bd.tcl | 6 +- .../ad9084_ebz/common/versal_transceiver.tcl | 1179 ----------------- projects/ad9084_ebz/vck190/Makefile | 2 +- projects/ad9084_ebz/vck190/system_project.tcl | 2 +- projects/ad9084_ebz/vck190/timing_constr.tcl | 6 +- projects/ad9084_ebz/vpk180/Makefile | 2 +- projects/ad9084_ebz/vpk180/system_project.tcl | 2 +- projects/ad9084_ebz/vpk180/timing_constr.tcl | 8 +- 8 files changed, 14 insertions(+), 1193 deletions(-) delete mode 100644 projects/ad9084_ebz/common/versal_transceiver.tcl diff --git a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl index 8e76871cdce..030b3d0e011 100755 --- a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl +++ b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl @@ -339,7 +339,7 @@ if {$ADI_PHY_SEL} { ad_ip_parameter axi_apollo_tx_xcvr CONFIG.QPLL_ENABLE 1 ad_ip_parameter axi_apollo_tx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0 } else { - source ../common/versal_transceiver.tcl + source $ad_hdl_dir/library/xilinx/scripts/versal_xcvr_subsystem.tcl # Reset gpios create_bd_port -dir O gt_powergood @@ -372,7 +372,7 @@ if {$ADI_PHY_SEL} { set REF_CLK_RATE $ad_project_params(REF_CLK_RATE) # instantiate versal phy - create_versal_phy jesd204_phy $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX + create_versal_jesd_xcvr_subsystem jesd204_phy $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX # reset generator ad_ip_instance proc_sys_reset rx_device_clk_rstgen ad_connect rx_device_clk rx_device_clk_rstgen/slowest_sync_clk @@ -425,7 +425,7 @@ if {$ASYMMETRIC_A_B_MODE} { ad_ip_parameter axi_apollo_tx_b_xcvr CONFIG.SYS_CLK_SEL 0x2 ; # QPLL1 } else { # instantiate versal phy - create_versal_phy jesd204_phy_b $JESD_MODE $RX_B_NUM_OF_LANES $TX_B_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX + create_versal_jesd_xcvr_subsystem jesd204_phy_b $JESD_MODE $RX_B_NUM_OF_LANES $TX_B_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX ad_connect gt_b_reset jesd204_phy_b/gtreset_in ad_connect gt_b_reset_rx_datapath jesd204_phy_b/gtreset_rx_datapath diff --git a/projects/ad9084_ebz/common/versal_transceiver.tcl b/projects/ad9084_ebz/common/versal_transceiver.tcl deleted file mode 100644 index 37ee0754a2e..00000000000 --- a/projects/ad9084_ebz/common/versal_transceiver.tcl +++ /dev/null @@ -1,1179 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# Parameter description: -# ip_name : The name of the versal phy ip -# rx_num_lanes : The number of used RX lanes for the JESD mode -# tx_num_lanes : The number of used TX lanes for the JESD mode -proc create_reset_logic { - {ip_name versal_phy} - {rx_num_lanes 4} - {tx_num_lanes 0} -} { - set rx_bridge gt_bridge_ip_0 - set asymmetric_mode [expr $rx_num_lanes != $tx_num_lanes] - set tx_bridge [expr {$asymmetric_mode == 0 ? "gt_bridge_ip_0" : "gt_bridge_ip_1"}] - - create_bd_pin -dir I ${ip_name}/gtreset_in - create_bd_pin -dir I ${ip_name}/gtreset_rx_pll_and_datapath - create_bd_pin -dir I ${ip_name}/gtreset_tx_pll_and_datapath - create_bd_pin -dir I ${ip_name}/gtreset_rx_datapath - create_bd_pin -dir I ${ip_name}/gtreset_tx_datapath - create_bd_pin -dir O ${ip_name}/gtpowergood - create_bd_pin -dir O ${ip_name}/rx_resetdone - create_bd_pin -dir O ${ip_name}/tx_resetdone - - # Sync resets to apb3clk - - create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_sync - ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_sync/out_clk - ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_sync/out_resetn - ad_connect ${ip_name}/gtreset_in ${ip_name}/gtreset_sync/in_bits - ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${rx_bridge}/gtreset_in - if {$asymmetric_mode} { - ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${tx_bridge}/gtreset_in - } - - foreach port {pll_and_datapath datapath} { - foreach rx_tx {rx tx} { - set bridge [expr {$rx_tx == "rx" ? $rx_bridge : $tx_bridge}] - create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_${rx_tx}_${port}_sync - ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_clk - ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_resetn - ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/gtreset_${rx_tx}_${port}_sync/in_bits - ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/${bridge}/reset_${rx_tx}_${port}_in - } - } - - set max_lanes [expr max($rx_num_lanes, $tx_num_lanes)] - set num_quads [expr int(ceil(1.0 * $max_lanes / 4))] - - ad_ip_instance xlconcat ${ip_name}/concat_powergood [list \ - NUM_PORTS $num_quads \ - ] - - ad_ip_instance util_reduced_logic ${ip_name}/and_powergood [list \ - C_SIZE $num_quads \ - ] - - for {set j 0} {$j < $num_quads} {incr j} { - ad_connect ${ip_name}/concat_powergood/In${j} ${ip_name}/gt_quad_base_${j}/gtpowergood - } - - ad_connect ${ip_name}/concat_powergood/dout ${ip_name}/and_powergood/Op1 - ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${rx_bridge}/gtpowergood - if {$asymmetric_mode} { - ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${tx_bridge}/gtpowergood - } - - for {set j 0} {$j < ${rx_num_lanes}} {incr j} { - set quad_index [expr int($j / 4)] - set ch_index [expr $j % 4] - ad_connect ${ip_name}/${rx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset - } - if {$asymmetric_mode} { - for {set j 0} {$j < ${rx_num_lanes}} {incr j} { - set quad_index [expr int($j / 4)] - set ch_index [expr $j % 4] - ad_connect ${ip_name}/${tx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset - } - } - ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone [list \ - NUM_PORTS ${rx_num_lanes} \ - ] - ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone [list \ - C_SIZE ${rx_num_lanes} \ - ] - for {set j 0} {$j < ${rx_num_lanes}} {incr j} { - set quad_index [expr int($j / 4)] - set ch_index [expr $j % 4] - ad_connect ${ip_name}/xlconcat_iloresetdone/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone - } - ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/and_iloresetdone/Op1 - ad_connect ${ip_name}/and_iloresetdone/Res ${ip_name}/${rx_bridge}/ilo_resetdone - if {$asymmetric_mode} { - ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone_tx [list \ - NUM_PORTS ${tx_num_lanes} \ - ] - ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone_tx [list \ - C_SIZE ${tx_num_lanes} \ - ] - for {set j 0} {$j < ${tx_num_lanes}} {incr j} { - set quad_index [expr int($j / 4)] - set ch_index [expr $j % 4] - ad_connect ${ip_name}/xlconcat_iloresetdone_tx/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone - } - ad_connect ${ip_name}/xlconcat_iloresetdone_tx/dout ${ip_name}/and_iloresetdone_tx/Op1 - ad_connect ${ip_name}/and_iloresetdone_tx/Res ${ip_name}/${tx_bridge}/ilo_resetdone - } - - for {set j 0} {$j < ${num_quads}} {incr j} { - ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk0_lcpllreset - ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk1_lcpllreset - } - - set num_cplllocks [expr 2 * ${num_quads}] - ad_ip_instance xlconcat ${ip_name}/concat_cplllock [list \ - NUM_PORTS ${num_cplllocks} \ - ] - ad_ip_instance util_reduced_logic ${ip_name}/and_cplllock [list \ - C_SIZE ${num_cplllocks} \ - ] - - for {set j 0} {$j < ${num_quads}} {incr j} { - set in_index_0 [expr $j * 2 + 0] - set in_index_1 [expr $j * 2 + 1] - ad_connect ${ip_name}/concat_cplllock/In${in_index_0} ${ip_name}/gt_quad_base_${j}/hsclk0_lcplllock - ad_connect ${ip_name}/concat_cplllock/In${in_index_1} ${ip_name}/gt_quad_base_${j}/hsclk1_lcplllock - } - - ad_connect ${ip_name}/concat_cplllock/dout ${ip_name}/and_cplllock/Op1 - ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${rx_bridge}/gt_lcpll_lock - if {$asymmetric_mode} { - ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${tx_bridge}/gt_lcpll_lock - } - - ad_ip_instance xlconcat ${ip_name}/concat_phystatus [list \ - NUM_PORTS ${rx_num_lanes} \ - ] - for {set j 0} {$j < ${rx_num_lanes}} {incr j} { - set quad_index [expr int($j / 4)] - set ch_index [expr $j % 4] - - ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus/In${j} - } - ad_connect ${ip_name}/concat_phystatus/dout ${ip_name}/${rx_bridge}/ch_phystatus_in - if {$asymmetric_mode} { - ad_ip_instance xlconcat ${ip_name}/concat_phystatus_tx [list \ - NUM_PORTS ${rx_num_lanes} \ - ] - for {set j 0} {$j < ${rx_num_lanes}} {incr j} { - set quad_index [expr int($j / 4)] - set ch_index [expr $j % 4] - - ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus_tx/In${j} - } - ad_connect ${ip_name}/concat_phystatus_tx/dout ${ip_name}/${tx_bridge}/ch_phystatus_in - } - - # Outputs - ad_connect ${ip_name}/and_powergood/Res ${ip_name}/gtpowergood - ad_connect ${ip_name}/${rx_bridge}/rx_resetdone_out ${ip_name}/rx_resetdone - ad_connect ${ip_name}/${tx_bridge}/tx_resetdone_out ${ip_name}/tx_resetdone -} - -# Parameter description: -# ip_name : The name of the created ip -# jesd_mode : Used physical layer encoder mode -# rx_num_lanes : Number of RX lanes -# tx_num_lanes : Number of TX lanes -# ref_clock : Frequency of reference clock in MHz used in 64B66B mode (LANE_RATE/66) or 8B10B mode (LANE_RATE/40) -# rx_lane_rate : Line rate of the Rx link ( e.g. MxFE to FPGA ) in GHz -# tx_lane_rate : Line rate of the Tx link ( e.g. FPGA to MxFE ) in GHz -# intf_cfg : Direction of the transceivers -# RXTX : Duplex mode -# RX : Rx link only -# TX : Tx link only -proc create_versal_phy { - {ip_name versal_phy} - {jesd_mode 64B66B} - {rx_num_lanes 4} - {tx_num_lanes 4} - {rx_lane_rate 24.75} - {tx_lane_rate 24.75} - {ref_clock 375} - {transceiver GTY} - {intf_cfg RXTX} -} { - - set clk_divider [expr { $jesd_mode == "64B66B" ? 66 : 40} ] - set datapath_width [expr { $jesd_mode == "64B66B" ? 64 : 32} ] - set internal_datapath_width [expr { $jesd_mode == "64B66B" ? 64 : 40} ] - set data_encoding [expr { $jesd_mode == "64B66B" ? "64B66B_ASYNC" : "8B10B"} ] - set link_mode [expr { $jesd_mode == "64B66B" ? 2 : 1} ] - set comma_mask [expr { $jesd_mode == "64B66B" ? "0000000000" : "1111111111"} ] - set comma_p_enable [expr { $jesd_mode == "64B66B" ? false : false} ] - set comma_m_enable [expr { $jesd_mode == "64B66B" ? false : false} ] - set num_quads [expr int(ceil(1.0 * max($rx_num_lanes, $tx_num_lanes) / 4))] - set asymmetric_mode [expr { [expr $rx_num_lanes != $tx_num_lanes] ? true : false } ] - # When asymmetric_mode is true it means that the number of lanes on the Rx side is different from the number of lanes on the Tx side - # The 'gt_bridge_ip' can only be configured with the same number of lanes so we need to instantiate two ips, one for the Rx and one for the Tx - # Both 'gt_bridge_ip' will still share the same quad - - set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / ${clk_divider}]] - set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / ${clk_divider}]] - - if {$intf_cfg == "RX"} { - set gt_direction "SIMPLEX_RX" - set no_lanes_property "CONFIG.IP_NO_OF_RX_LANES" - } elseif {$intf_cfg == "TX"} { - set gt_direction "SIMPLEX_TX" - set no_lanes_property "CONFIG.IP_NO_OF_TX_LANES" - } else { - set gt_direction "DUPLEX" - set no_lanes_property "CONFIG.IP_NO_OF_LANES" - } - - create_bd_cell -type hier ${ip_name} - - # Common interface - create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk - create_bd_pin -dir I ${ip_name}/s_axi_clk - create_bd_pin -dir I ${ip_name}/s_axi_resetn - if {$intf_cfg != "TX"} { - create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk - create_bd_pin -dir I ${ip_name}/en_char_align - } - if {$intf_cfg != "RX"} { - create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk - } - - ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0 - set rx_bridge gt_bridge_ip_0 - set tx_bridge gt_bridge_ip_0 - if {$asymmetric_mode} { - ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_1 - set tx_bridge gt_bridge_ip_1 - } - if {!$asymmetric_mode} { - set num_lanes [expr max($rx_num_lanes, $tx_num_lanes)] - set_property -dict [list \ - CONFIG.BYPASS_MODE {true} \ - CONFIG.IP_PRESET ${transceiver}-JESD204_${jesd_mode} \ - CONFIG.IP_GT_DIRECTION ${gt_direction} \ - ${no_lanes_property} ${num_lanes} \ - CONFIG.IP_LR0_SETTINGS [list \ - PRESET ${transceiver}-JESD204_${jesd_mode} \ - INTERNAL_PRESET JESD204_${jesd_mode} \ - GT_TYPE ${transceiver} \ - GT_DIRECTION $gt_direction \ - TX_LINE_RATE $tx_lane_rate \ - TX_PLL_TYPE LCPLL \ - TX_REFCLK_FREQUENCY $ref_clock \ - TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - TX_FRACN_ENABLED true \ - TX_FRACN_NUMERATOR 0 \ - TX_REFCLK_SOURCE R0 \ - TX_DATA_ENCODING $data_encoding \ - TX_USER_DATA_WIDTH $datapath_width \ - TX_INT_DATA_WIDTH $internal_datapath_width \ - TX_BUFFER_MODE 1 \ - TX_BUFFER_BYPASS_MODE Fast_Sync \ - TX_PIPM_ENABLE false \ - TX_OUTCLK_SOURCE TXPROGDIVCLK \ - TXPROGDIV_FREQ_ENABLE true \ - TXPROGDIV_FREQ_SOURCE LCPLL \ - TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ - TX_DIFF_SWING_EMPH_MODE CUSTOM \ - TX_64B66B_SCRAMBLER false \ - TX_64B66B_ENCODER false \ - TX_64B66B_CRC false \ - TX_RATE_GROUP A \ - RX_LINE_RATE $rx_lane_rate \ - RX_PLL_TYPE LCPLL \ - RX_REFCLK_FREQUENCY $ref_clock \ - RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - RX_FRACN_ENABLED true \ - RX_FRACN_NUMERATOR 0 \ - RX_REFCLK_SOURCE R0 \ - RX_DATA_DECODING $data_encoding \ - RX_USER_DATA_WIDTH $datapath_width \ - RX_INT_DATA_WIDTH $internal_datapath_width \ - RX_BUFFER_MODE 1 \ - RX_OUTCLK_SOURCE RXPROGDIVCLK \ - RXPROGDIV_FREQ_ENABLE true \ - RXPROGDIV_FREQ_SOURCE LCPLL \ - RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ - INS_LOSS_NYQ 12 \ - RX_EQ_MODE LPM \ - RX_COUPLING AC \ - RX_TERMINATION PROGRAMMABLE \ - RX_RATE_GROUP A \ - RX_TERMINATION_PROG_VALUE 800 \ - RX_PPM_OFFSET 0 \ - RX_64B66B_DESCRAMBLER false \ - RX_64B66B_DECODER false \ - RX_64B66B_CRC false \ - OOB_ENABLE false \ - RX_COMMA_ALIGN_WORD 1 \ - RX_COMMA_SHOW_REALIGN_ENABLE false \ - PCIE_ENABLE false \ - RX_COMMA_P_ENABLE $comma_p_enable \ - RX_COMMA_M_ENABLE $comma_m_enable \ - RX_COMMA_DOUBLE_ENABLE false \ - RX_COMMA_P_VAL 0101111100 \ - RX_COMMA_M_VAL 1010000011 \ - RX_COMMA_MASK $comma_mask \ - RX_SLIDE_MODE PCS \ - RX_SSC_PPM 0 \ - RX_CB_NUM_SEQ 0 \ - RX_CB_LEN_SEQ 1 \ - RX_CB_MAX_SKEW 1 \ - RX_CB_MAX_LEVEL 1 \ - RX_CB_MASK_0_0 false \ - RX_CB_VAL_0_0 00000000 \ - RX_CB_K_0_0 false \ - RX_CB_DISP_0_0 false \ - RX_CB_MASK_0_1 false \ - RX_CB_VAL_0_1 00000000 \ - RX_CB_K_0_1 false \ - RX_CB_DISP_0_1 false \ - RX_CB_MASK_0_2 false \ - RX_CB_VAL_0_2 00000000 \ - RX_CB_K_0_2 false \ - RX_CB_DISP_0_2 false \ - RX_CB_MASK_0_3 false \ - RX_CB_VAL_0_3 00000000 \ - RX_CB_K_0_3 false \ - RX_CB_DISP_0_3 false \ - RX_CB_MASK_1_0 false \ - RX_CB_VAL_1_0 00000000 \ - RX_CB_K_1_0 false \ - RX_CB_DISP_1_0 false \ - RX_CB_MASK_1_1 false \ - RX_CB_VAL_1_1 00000000 \ - RX_CB_K_1_1 false \ - RX_CB_DISP_1_1 false \ - RX_CB_MASK_1_2 false \ - RX_CB_VAL_1_2 00000000 \ - RX_CB_K_1_2 false \ - RX_CB_DISP_1_2 false \ - RX_CB_MASK_1_3 false \ - RX_CB_VAL_1_3 00000000 \ - RX_CB_K_1_3 false \ - RX_CB_DISP_1_3 false \ - RX_CC_NUM_SEQ 0 \ - RX_CC_LEN_SEQ 1 \ - RX_CC_PERIODICITY 5000 \ - RX_CC_KEEP_IDLE DISABLE \ - RX_CC_PRECEDENCE ENABLE \ - RX_CC_REPEAT_WAIT 0 \ - RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ - RX_CC_MASK_0_0 false \ - RX_CC_VAL_0_0 00000000 \ - RX_CC_K_0_0 false \ - RX_CC_DISP_0_0 false \ - RX_CC_MASK_0_1 false \ - RX_CC_VAL_0_1 00000000 \ - RX_CC_K_0_1 false \ - RX_CC_DISP_0_1 false \ - RX_CC_MASK_0_2 false \ - RX_CC_VAL_0_2 00000000 \ - RX_CC_K_0_2 false \ - RX_CC_DISP_0_2 false \ - RX_CC_MASK_0_3 false \ - RX_CC_VAL_0_3 00000000 \ - RX_CC_K_0_3 false \ - RX_CC_DISP_0_3 false \ - RX_CC_MASK_1_0 false \ - RX_CC_VAL_1_0 00000000 \ - RX_CC_K_1_0 false \ - RX_CC_DISP_1_0 false \ - RX_CC_MASK_1_1 false \ - RX_CC_VAL_1_1 00000000 \ - RX_CC_K_1_1 false \ - RX_CC_DISP_1_1 false \ - RX_CC_MASK_1_2 false \ - RX_CC_VAL_1_2 00000000 \ - RX_CC_K_1_2 false \ - RX_CC_DISP_1_2 false \ - RX_CC_MASK_1_3 false \ - RX_CC_VAL_1_3 00000000 \ - RX_CC_K_1_3 false \ - RX_CC_DISP_1_3 false \ - PCIE_USERCLK2_FREQ 250 \ - PCIE_USERCLK_FREQ 250 \ - RX_JTOL_FC 10 \ - RX_JTOL_LF_SLOPE -20 \ - RX_BUFFER_BYPASS_MODE Fast_Sync \ - RX_BUFFER_BYPASS_MODE_LANE MULTI \ - RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ - RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ - RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - RESET_SEQUENCE_INTERVAL 0 \ - RX_COMMA_PRESET NONE \ - RX_COMMA_VALID_ONLY 0 \ - ] \ - ] [get_bd_cells ${ip_name}/${rx_bridge}] - } else { - set_property -dict [list \ - CONFIG.BYPASS_MODE {true} \ - CONFIG.IP_PRESET ${transceiver}-JESD204_${jesd_mode} \ - CONFIG.IP_GT_DIRECTION {SIMPLEX_RX} \ - CONFIG.IP_NO_OF_RX_LANES ${rx_num_lanes} \ - CONFIG.IP_LR0_SETTINGS [list \ - PRESET ${transceiver}-JESD204_${jesd_mode} \ - INTERNAL_PRESET JESD204_${jesd_mode} \ - GT_TYPE ${transceiver} \ - GT_DIRECTION SIMPLEX_RX \ - TX_LINE_RATE $tx_lane_rate \ - TX_PLL_TYPE LCPLL \ - TX_REFCLK_FREQUENCY $ref_clock \ - TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - TX_FRACN_ENABLED true \ - TX_FRACN_NUMERATOR 0 \ - TX_REFCLK_SOURCE R0 \ - TX_DATA_ENCODING $data_encoding \ - TX_USER_DATA_WIDTH $datapath_width \ - TX_INT_DATA_WIDTH $internal_datapath_width \ - TX_BUFFER_MODE 1 \ - TX_BUFFER_BYPASS_MODE Fast_Sync \ - TX_PIPM_ENABLE false \ - TX_OUTCLK_SOURCE TXPROGDIVCLK \ - TXPROGDIV_FREQ_ENABLE true \ - TXPROGDIV_FREQ_SOURCE LCPLL \ - TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ - TX_DIFF_SWING_EMPH_MODE CUSTOM \ - TX_64B66B_SCRAMBLER false \ - TX_64B66B_ENCODER false \ - TX_64B66B_CRC false \ - TX_RATE_GROUP A \ - RX_LINE_RATE $rx_lane_rate \ - RX_PLL_TYPE LCPLL \ - RX_REFCLK_FREQUENCY $ref_clock \ - RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - RX_FRACN_ENABLED true \ - RX_FRACN_NUMERATOR 0 \ - RX_REFCLK_SOURCE R0 \ - RX_DATA_DECODING $data_encoding \ - RX_USER_DATA_WIDTH $datapath_width \ - RX_INT_DATA_WIDTH $internal_datapath_width \ - RX_BUFFER_MODE 1 \ - RX_OUTCLK_SOURCE RXPROGDIVCLK \ - RXPROGDIV_FREQ_ENABLE true \ - RXPROGDIV_FREQ_SOURCE LCPLL \ - RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ - INS_LOSS_NYQ 12 \ - RX_EQ_MODE LPM \ - RX_COUPLING AC \ - RX_TERMINATION PROGRAMMABLE \ - RX_RATE_GROUP A \ - RX_TERMINATION_PROG_VALUE 800 \ - RX_PPM_OFFSET 0 \ - RX_64B66B_DESCRAMBLER false \ - RX_64B66B_DECODER false \ - RX_64B66B_CRC false \ - OOB_ENABLE false \ - RX_COMMA_ALIGN_WORD 1 \ - RX_COMMA_SHOW_REALIGN_ENABLE false \ - PCIE_ENABLE false \ - RX_COMMA_P_ENABLE $comma_p_enable \ - RX_COMMA_M_ENABLE $comma_m_enable \ - RX_COMMA_DOUBLE_ENABLE false \ - RX_COMMA_P_VAL 0101111100 \ - RX_COMMA_M_VAL 1010000011 \ - RX_COMMA_MASK $comma_mask \ - RX_SLIDE_MODE PCS \ - RX_SSC_PPM 0 \ - RX_CB_NUM_SEQ 0 \ - RX_CB_LEN_SEQ 1 \ - RX_CB_MAX_SKEW 1 \ - RX_CB_MAX_LEVEL 1 \ - RX_CB_MASK_0_0 false \ - RX_CB_VAL_0_0 00000000 \ - RX_CB_K_0_0 false \ - RX_CB_DISP_0_0 false \ - RX_CB_MASK_0_1 false \ - RX_CB_VAL_0_1 00000000 \ - RX_CB_K_0_1 false \ - RX_CB_DISP_0_1 false \ - RX_CB_MASK_0_2 false \ - RX_CB_VAL_0_2 00000000 \ - RX_CB_K_0_2 false \ - RX_CB_DISP_0_2 false \ - RX_CB_MASK_0_3 false \ - RX_CB_VAL_0_3 00000000 \ - RX_CB_K_0_3 false \ - RX_CB_DISP_0_3 false \ - RX_CB_MASK_1_0 false \ - RX_CB_VAL_1_0 00000000 \ - RX_CB_K_1_0 false \ - RX_CB_DISP_1_0 false \ - RX_CB_MASK_1_1 false \ - RX_CB_VAL_1_1 00000000 \ - RX_CB_K_1_1 false \ - RX_CB_DISP_1_1 false \ - RX_CB_MASK_1_2 false \ - RX_CB_VAL_1_2 00000000 \ - RX_CB_K_1_2 false \ - RX_CB_DISP_1_2 false \ - RX_CB_MASK_1_3 false \ - RX_CB_VAL_1_3 00000000 \ - RX_CB_K_1_3 false \ - RX_CB_DISP_1_3 false \ - RX_CC_NUM_SEQ 0 \ - RX_CC_LEN_SEQ 1 \ - RX_CC_PERIODICITY 5000 \ - RX_CC_KEEP_IDLE DISABLE \ - RX_CC_PRECEDENCE ENABLE \ - RX_CC_REPEAT_WAIT 0 \ - RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ - RX_CC_MASK_0_0 false \ - RX_CC_VAL_0_0 00000000 \ - RX_CC_K_0_0 false \ - RX_CC_DISP_0_0 false \ - RX_CC_MASK_0_1 false \ - RX_CC_VAL_0_1 00000000 \ - RX_CC_K_0_1 false \ - RX_CC_DISP_0_1 false \ - RX_CC_MASK_0_2 false \ - RX_CC_VAL_0_2 00000000 \ - RX_CC_K_0_2 false \ - RX_CC_DISP_0_2 false \ - RX_CC_MASK_0_3 false \ - RX_CC_VAL_0_3 00000000 \ - RX_CC_K_0_3 false \ - RX_CC_DISP_0_3 false \ - RX_CC_MASK_1_0 false \ - RX_CC_VAL_1_0 00000000 \ - RX_CC_K_1_0 false \ - RX_CC_DISP_1_0 false \ - RX_CC_MASK_1_1 false \ - RX_CC_VAL_1_1 00000000 \ - RX_CC_K_1_1 false \ - RX_CC_DISP_1_1 false \ - RX_CC_MASK_1_2 false \ - RX_CC_VAL_1_2 00000000 \ - RX_CC_K_1_2 false \ - RX_CC_DISP_1_2 false \ - RX_CC_MASK_1_3 false \ - RX_CC_VAL_1_3 00000000 \ - RX_CC_K_1_3 false \ - RX_CC_DISP_1_3 false \ - PCIE_USERCLK2_FREQ 250 \ - PCIE_USERCLK_FREQ 250 \ - RX_JTOL_FC 10 \ - RX_JTOL_LF_SLOPE -20 \ - RX_BUFFER_BYPASS_MODE Fast_Sync \ - RX_BUFFER_BYPASS_MODE_LANE MULTI \ - RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ - RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ - RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - RESET_SEQUENCE_INTERVAL 0 \ - RX_COMMA_PRESET NONE \ - RX_COMMA_VALID_ONLY 0 \ - ] \ - ] [get_bd_cells ${ip_name}/${rx_bridge}] - - set_property -dict [list \ - CONFIG.BYPASS_MODE {true} \ - CONFIG.IP_PRESET ${transceiver}-JESD204_${jesd_mode} \ - CONFIG.IP_GT_DIRECTION {SIMPLEX_TX} \ - CONFIG.IP_NO_OF_TX_LANES ${tx_num_lanes} \ - CONFIG.IP_LR0_SETTINGS [list \ - PRESET ${transceiver}-JESD204_${jesd_mode} \ - INTERNAL_PRESET JESD204_${jesd_mode} \ - GT_TYPE ${transceiver} \ - GT_DIRECTION SIMPLEX_TX \ - TX_LINE_RATE $tx_lane_rate \ - TX_PLL_TYPE LCPLL \ - TX_REFCLK_FREQUENCY $ref_clock \ - TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - TX_FRACN_ENABLED true \ - TX_FRACN_NUMERATOR 0 \ - TX_REFCLK_SOURCE R0 \ - TX_DATA_ENCODING $data_encoding \ - TX_USER_DATA_WIDTH $datapath_width \ - TX_INT_DATA_WIDTH $internal_datapath_width \ - TX_BUFFER_MODE 1 \ - TX_BUFFER_BYPASS_MODE Fast_Sync \ - TX_PIPM_ENABLE false \ - TX_OUTCLK_SOURCE TXPROGDIVCLK \ - TXPROGDIV_FREQ_ENABLE true \ - TXPROGDIV_FREQ_SOURCE LCPLL \ - TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ - TX_DIFF_SWING_EMPH_MODE CUSTOM \ - TX_64B66B_SCRAMBLER false \ - TX_64B66B_ENCODER false \ - TX_64B66B_CRC false \ - TX_RATE_GROUP A \ - RX_LINE_RATE $rx_lane_rate \ - RX_PLL_TYPE LCPLL \ - RX_REFCLK_FREQUENCY $ref_clock \ - RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - RX_FRACN_ENABLED true \ - RX_FRACN_NUMERATOR 0 \ - RX_REFCLK_SOURCE R0 \ - RX_DATA_DECODING $data_encoding \ - RX_USER_DATA_WIDTH $datapath_width \ - RX_INT_DATA_WIDTH $internal_datapath_width \ - RX_BUFFER_MODE 1 \ - RX_OUTCLK_SOURCE RXPROGDIVCLK \ - RXPROGDIV_FREQ_ENABLE true \ - RXPROGDIV_FREQ_SOURCE LCPLL \ - RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ - INS_LOSS_NYQ 12 \ - RX_EQ_MODE LPM \ - RX_COUPLING AC \ - RX_TERMINATION PROGRAMMABLE \ - RX_RATE_GROUP A \ - RX_TERMINATION_PROG_VALUE 800 \ - RX_PPM_OFFSET 0 \ - RX_64B66B_DESCRAMBLER false \ - RX_64B66B_DECODER false \ - RX_64B66B_CRC false \ - OOB_ENABLE false \ - RX_COMMA_ALIGN_WORD 1 \ - RX_COMMA_SHOW_REALIGN_ENABLE false \ - PCIE_ENABLE false \ - RX_COMMA_P_ENABLE $comma_p_enable \ - RX_COMMA_M_ENABLE $comma_m_enable \ - RX_COMMA_DOUBLE_ENABLE false \ - RX_COMMA_P_VAL 0101111100 \ - RX_COMMA_M_VAL 1010000011 \ - RX_COMMA_MASK $comma_mask \ - RX_SLIDE_MODE PCS \ - RX_SSC_PPM 0 \ - RX_CB_NUM_SEQ 0 \ - RX_CB_LEN_SEQ 1 \ - RX_CB_MAX_SKEW 1 \ - RX_CB_MAX_LEVEL 1 \ - RX_CB_MASK_0_0 false \ - RX_CB_VAL_0_0 00000000 \ - RX_CB_K_0_0 false \ - RX_CB_DISP_0_0 false \ - RX_CB_MASK_0_1 false \ - RX_CB_VAL_0_1 00000000 \ - RX_CB_K_0_1 false \ - RX_CB_DISP_0_1 false \ - RX_CB_MASK_0_2 false \ - RX_CB_VAL_0_2 00000000 \ - RX_CB_K_0_2 false \ - RX_CB_DISP_0_2 false \ - RX_CB_MASK_0_3 false \ - RX_CB_VAL_0_3 00000000 \ - RX_CB_K_0_3 false \ - RX_CB_DISP_0_3 false \ - RX_CB_MASK_1_0 false \ - RX_CB_VAL_1_0 00000000 \ - RX_CB_K_1_0 false \ - RX_CB_DISP_1_0 false \ - RX_CB_MASK_1_1 false \ - RX_CB_VAL_1_1 00000000 \ - RX_CB_K_1_1 false \ - RX_CB_DISP_1_1 false \ - RX_CB_MASK_1_2 false \ - RX_CB_VAL_1_2 00000000 \ - RX_CB_K_1_2 false \ - RX_CB_DISP_1_2 false \ - RX_CB_MASK_1_3 false \ - RX_CB_VAL_1_3 00000000 \ - RX_CB_K_1_3 false \ - RX_CB_DISP_1_3 false \ - RX_CC_NUM_SEQ 0 \ - RX_CC_LEN_SEQ 1 \ - RX_CC_PERIODICITY 5000 \ - RX_CC_KEEP_IDLE DISABLE \ - RX_CC_PRECEDENCE ENABLE \ - RX_CC_REPEAT_WAIT 0 \ - RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ - RX_CC_MASK_0_0 false \ - RX_CC_VAL_0_0 00000000 \ - RX_CC_K_0_0 false \ - RX_CC_DISP_0_0 false \ - RX_CC_MASK_0_1 false \ - RX_CC_VAL_0_1 00000000 \ - RX_CC_K_0_1 false \ - RX_CC_DISP_0_1 false \ - RX_CC_MASK_0_2 false \ - RX_CC_VAL_0_2 00000000 \ - RX_CC_K_0_2 false \ - RX_CC_DISP_0_2 false \ - RX_CC_MASK_0_3 false \ - RX_CC_VAL_0_3 00000000 \ - RX_CC_K_0_3 false \ - RX_CC_DISP_0_3 false \ - RX_CC_MASK_1_0 false \ - RX_CC_VAL_1_0 00000000 \ - RX_CC_K_1_0 false \ - RX_CC_DISP_1_0 false \ - RX_CC_MASK_1_1 false \ - RX_CC_VAL_1_1 00000000 \ - RX_CC_K_1_1 false \ - RX_CC_DISP_1_1 false \ - RX_CC_MASK_1_2 false \ - RX_CC_VAL_1_2 00000000 \ - RX_CC_K_1_2 false \ - RX_CC_DISP_1_2 false \ - RX_CC_MASK_1_3 false \ - RX_CC_VAL_1_3 00000000 \ - RX_CC_K_1_3 false \ - RX_CC_DISP_1_3 false \ - PCIE_USERCLK2_FREQ 250 \ - PCIE_USERCLK_FREQ 250 \ - RX_JTOL_FC 10 \ - RX_JTOL_LF_SLOPE -20 \ - RX_BUFFER_BYPASS_MODE Fast_Sync \ - RX_BUFFER_BYPASS_MODE_LANE MULTI \ - RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ - RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ - RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - RESET_SEQUENCE_INTERVAL 0 \ - RX_COMMA_PRESET NONE \ - RX_COMMA_VALID_ONLY 0 \ - ] \ - ] [get_bd_cells ${ip_name}/${tx_bridge}] - } - - for {set j 0} {$j < $num_quads} {incr j} { - ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_${j} - set_property -dict [list \ - CONFIG.REG_CONF_INTF.VALUE_MODE {MANUAL} \ - CONFIG.REG_CONF_INTF {AXI_LITE} \ - ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] - if {!$asymmetric_mode} { - set_property -dict [list \ - CONFIG.REG_CONF_INTF.VALUE_MODE {MANUAL} \ - ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] - } else { - # When we have multiple protocols (different number of lanes on Rx and Tx) we have to manually set the protocols to pass design validation - set_property -dict [list \ - CONFIG.PROT1_LR0_SETTINGS.VALUE_MODE MANUAL \ - CONFIG.GT_TYPE.VALUE_MODE AUTO \ - CONFIG.PROT0_RX_MASTERCLK_SRC.VALUE_MODE MANUAL \ - CONFIG.PROT1_TX_MASTERCLK_SRC.VALUE_MODE MANUAL \ - CONFIG.PROT0_TX_MASTERCLK_SRC.VALUE_MODE MANUAL \ - CONFIG.PROT1_PRESET.VALUE_MODE MANUAL \ - CONFIG.PROT1_ENABLE.VALUE_MODE MANUAL \ - CONFIG.PROT0_PRESET.VALUE_MODE MANUAL \ - CONFIG.PROT0_GT_DIRECTION.VALUE_MODE MANUAL \ - CONFIG.TX0_LANE_SEL.VALUE_MODE AUTO \ - CONFIG.PROT0_NO_OF_LANES.VALUE_MODE MANUAL \ - CONFIG.PROT0_NO_OF_RX_LANES.VALUE_MODE MANUAL \ - CONFIG.PROT1_NO_OF_TX_LANES.VALUE_MODE MANUAL \ - CONFIG.PROT1_GT_DIRECTION.VALUE_MODE MANUAL \ - CONFIG.PROT0_LR0_SETTINGS.VALUE_MODE MANUAL \ - ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] - - set_property -dict [list \ - CONFIG.PROT0_GT_DIRECTION {SIMPLEX_RX} \ - CONFIG.PROT0_LR0_SETTINGS [list \ - PRESET ${transceiver}-JESD204_${jesd_mode} \ - INTERNAL_PRESET JESD204_${jesd_mode} \ - GT_TYPE ${transceiver} \ - GT_DIRECTION {SIMPLEX_RX} \ - TX_LINE_RATE $tx_lane_rate \ - TX_PLL_TYPE LCPLL \ - TX_REFCLK_FREQUENCY $ref_clock \ - TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - TX_FRACN_ENABLED true \ - TX_FRACN_NUMERATOR 0 \ - TX_REFCLK_SOURCE R0 \ - TX_DATA_ENCODING $data_encoding \ - TX_USER_DATA_WIDTH $datapath_width \ - TX_INT_DATA_WIDTH $internal_datapath_width \ - TX_BUFFER_MODE 1 \ - TX_BUFFER_BYPASS_MODE Fast_Sync \ - TX_PIPM_ENABLE false \ - TX_OUTCLK_SOURCE TXPROGDIVCLK \ - TXPROGDIV_FREQ_ENABLE true \ - TXPROGDIV_FREQ_SOURCE LCPLL \ - TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ - TX_DIFF_SWING_EMPH_MODE CUSTOM \ - TX_64B66B_SCRAMBLER false \ - TX_64B66B_ENCODER false \ - TX_64B66B_CRC false \ - TX_RATE_GROUP A \ - RX_LINE_RATE $rx_lane_rate \ - RX_PLL_TYPE LCPLL \ - RX_REFCLK_FREQUENCY $ref_clock \ - RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - RX_FRACN_ENABLED true \ - RX_FRACN_NUMERATOR 0 \ - RX_REFCLK_SOURCE R0 \ - RX_DATA_DECODING $data_encoding \ - RX_USER_DATA_WIDTH $datapath_width \ - RX_INT_DATA_WIDTH $internal_datapath_width \ - RX_BUFFER_MODE 1 \ - RX_OUTCLK_SOURCE RXPROGDIVCLK \ - RXPROGDIV_FREQ_ENABLE true \ - RXPROGDIV_FREQ_SOURCE LCPLL \ - RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ - INS_LOSS_NYQ 12 \ - RX_EQ_MODE LPM \ - RX_COUPLING AC \ - RX_TERMINATION PROGRAMMABLE \ - RX_RATE_GROUP A \ - RX_TERMINATION_PROG_VALUE 800 \ - RX_PPM_OFFSET 0 \ - RX_64B66B_DESCRAMBLER false \ - RX_64B66B_DECODER false \ - RX_64B66B_CRC false \ - OOB_ENABLE false \ - RX_COMMA_ALIGN_WORD 1 \ - RX_COMMA_SHOW_REALIGN_ENABLE false \ - PCIE_ENABLE false \ - RX_COMMA_P_ENABLE $comma_p_enable \ - RX_COMMA_M_ENABLE $comma_m_enable \ - RX_COMMA_DOUBLE_ENABLE false \ - RX_COMMA_P_VAL 0101111100 \ - RX_COMMA_M_VAL 1010000011 \ - RX_COMMA_MASK $comma_mask \ - RX_SLIDE_MODE PCS \ - RX_SSC_PPM 0 \ - RX_CB_NUM_SEQ 0 \ - RX_CB_LEN_SEQ 1 \ - RX_CB_MAX_SKEW 1 \ - RX_CB_MAX_LEVEL 1 \ - RX_CB_MASK_0_0 false \ - RX_CB_VAL_0_0 00000000 \ - RX_CB_K_0_0 false \ - RX_CB_DISP_0_0 false \ - RX_CB_MASK_0_1 false \ - RX_CB_VAL_0_1 00000000 \ - RX_CB_K_0_1 false \ - RX_CB_DISP_0_1 false \ - RX_CB_MASK_0_2 false \ - RX_CB_VAL_0_2 00000000 \ - RX_CB_K_0_2 false \ - RX_CB_DISP_0_2 false \ - RX_CB_MASK_0_3 false \ - RX_CB_VAL_0_3 00000000 \ - RX_CB_K_0_3 false \ - RX_CB_DISP_0_3 false \ - RX_CB_MASK_1_0 false \ - RX_CB_VAL_1_0 00000000 \ - RX_CB_K_1_0 false \ - RX_CB_DISP_1_0 false \ - RX_CB_MASK_1_1 false \ - RX_CB_VAL_1_1 00000000 \ - RX_CB_K_1_1 false \ - RX_CB_DISP_1_1 false \ - RX_CB_MASK_1_2 false \ - RX_CB_VAL_1_2 00000000 \ - RX_CB_K_1_2 false \ - RX_CB_DISP_1_2 false \ - RX_CB_MASK_1_3 false \ - RX_CB_VAL_1_3 00000000 \ - RX_CB_K_1_3 false \ - RX_CB_DISP_1_3 false \ - RX_CC_NUM_SEQ 0 \ - RX_CC_LEN_SEQ 1 \ - RX_CC_PERIODICITY 5000 \ - RX_CC_KEEP_IDLE DISABLE \ - RX_CC_PRECEDENCE ENABLE \ - RX_CC_REPEAT_WAIT 0 \ - RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ - RX_CC_MASK_0_0 false \ - RX_CC_VAL_0_0 00000000 \ - RX_CC_K_0_0 false \ - RX_CC_DISP_0_0 false \ - RX_CC_MASK_0_1 false \ - RX_CC_VAL_0_1 00000000 \ - RX_CC_K_0_1 false \ - RX_CC_DISP_0_1 false \ - RX_CC_MASK_0_2 false \ - RX_CC_VAL_0_2 00000000 \ - RX_CC_K_0_2 false \ - RX_CC_DISP_0_2 false \ - RX_CC_MASK_0_3 false \ - RX_CC_VAL_0_3 00000000 \ - RX_CC_K_0_3 false \ - RX_CC_DISP_0_3 false \ - RX_CC_MASK_1_0 false \ - RX_CC_VAL_1_0 00000000 \ - RX_CC_K_1_0 false \ - RX_CC_DISP_1_0 false \ - RX_CC_MASK_1_1 false \ - RX_CC_VAL_1_1 00000000 \ - RX_CC_K_1_1 false \ - RX_CC_DISP_1_1 false \ - RX_CC_MASK_1_2 false \ - RX_CC_VAL_1_2 00000000 \ - RX_CC_K_1_2 false \ - RX_CC_DISP_1_2 false \ - RX_CC_MASK_1_3 false \ - RX_CC_VAL_1_3 00000000 \ - RX_CC_K_1_3 false \ - RX_CC_DISP_1_3 false \ - PCIE_USERCLK2_FREQ 250 \ - PCIE_USERCLK_FREQ 250 \ - RX_JTOL_FC 10 \ - RX_JTOL_LF_SLOPE -20 \ - RX_BUFFER_BYPASS_MODE Fast_Sync \ - RX_BUFFER_BYPASS_MODE_LANE MULTI \ - RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ - RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ - RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - RESET_SEQUENCE_INTERVAL 0 \ - RX_COMMA_PRESET NONE \ - RX_COMMA_VALID_ONLY 0 \ - ] \ - CONFIG.PROT0_NO_OF_RX_LANES $rx_num_lanes \ - CONFIG.PROT0_PRESET ${transceiver}-JESD204_${jesd_mode} \ - CONFIG.PROT1_ENABLE {true} \ - CONFIG.PROT1_GT_DIRECTION {SIMPLEX_TX} \ - CONFIG.PROT1_LR0_SETTINGS [list \ - PRESET ${transceiver}-JESD204_${jesd_mode} \ - INTERNAL_PRESET JESD204_${jesd_mode} \ - GT_TYPE ${transceiver} \ - GT_DIRECTION {SIMPLEX_TX} \ - TX_LINE_RATE $tx_lane_rate \ - TX_PLL_TYPE LCPLL \ - TX_REFCLK_FREQUENCY $ref_clock \ - TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - TX_FRACN_ENABLED true \ - TX_FRACN_NUMERATOR 0 \ - TX_REFCLK_SOURCE R0 \ - TX_DATA_ENCODING $data_encoding \ - TX_USER_DATA_WIDTH $datapath_width \ - TX_INT_DATA_WIDTH $internal_datapath_width \ - TX_BUFFER_MODE 1 \ - TX_BUFFER_BYPASS_MODE Fast_Sync \ - TX_PIPM_ENABLE false \ - TX_OUTCLK_SOURCE TXPROGDIVCLK \ - TXPROGDIV_FREQ_ENABLE true \ - TXPROGDIV_FREQ_SOURCE LCPLL \ - TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ - TX_DIFF_SWING_EMPH_MODE CUSTOM \ - TX_64B66B_SCRAMBLER false \ - TX_64B66B_ENCODER false \ - TX_64B66B_CRC false \ - TX_RATE_GROUP A \ - RX_LINE_RATE $rx_lane_rate \ - RX_PLL_TYPE LCPLL \ - RX_REFCLK_FREQUENCY $ref_clock \ - RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - RX_FRACN_ENABLED true \ - RX_FRACN_NUMERATOR 0 \ - RX_REFCLK_SOURCE R0 \ - RX_DATA_DECODING $data_encoding \ - RX_USER_DATA_WIDTH $datapath_width \ - RX_INT_DATA_WIDTH $internal_datapath_width \ - RX_BUFFER_MODE 1 \ - RX_OUTCLK_SOURCE RXPROGDIVCLK \ - RXPROGDIV_FREQ_ENABLE true \ - RXPROGDIV_FREQ_SOURCE LCPLL \ - RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ - INS_LOSS_NYQ 12 \ - RX_EQ_MODE LPM \ - RX_COUPLING AC \ - RX_TERMINATION PROGRAMMABLE \ - RX_RATE_GROUP A \ - RX_TERMINATION_PROG_VALUE 800 \ - RX_PPM_OFFSET 0 \ - RX_64B66B_DESCRAMBLER false \ - RX_64B66B_DECODER false \ - RX_64B66B_CRC false \ - OOB_ENABLE false \ - RX_COMMA_ALIGN_WORD 1 \ - RX_COMMA_SHOW_REALIGN_ENABLE false \ - PCIE_ENABLE false \ - RX_COMMA_P_ENABLE $comma_p_enable \ - RX_COMMA_M_ENABLE $comma_m_enable \ - RX_COMMA_DOUBLE_ENABLE false \ - RX_COMMA_P_VAL 0101111100 \ - RX_COMMA_M_VAL 1010000011 \ - RX_COMMA_MASK $comma_mask \ - RX_SLIDE_MODE PCS \ - RX_SSC_PPM 0 \ - RX_CB_NUM_SEQ 0 \ - RX_CB_LEN_SEQ 1 \ - RX_CB_MAX_SKEW 1 \ - RX_CB_MAX_LEVEL 1 \ - RX_CB_MASK_0_0 false \ - RX_CB_VAL_0_0 00000000 \ - RX_CB_K_0_0 false \ - RX_CB_DISP_0_0 false \ - RX_CB_MASK_0_1 false \ - RX_CB_VAL_0_1 00000000 \ - RX_CB_K_0_1 false \ - RX_CB_DISP_0_1 false \ - RX_CB_MASK_0_2 false \ - RX_CB_VAL_0_2 00000000 \ - RX_CB_K_0_2 false \ - RX_CB_DISP_0_2 false \ - RX_CB_MASK_0_3 false \ - RX_CB_VAL_0_3 00000000 \ - RX_CB_K_0_3 false \ - RX_CB_DISP_0_3 false \ - RX_CB_MASK_1_0 false \ - RX_CB_VAL_1_0 00000000 \ - RX_CB_K_1_0 false \ - RX_CB_DISP_1_0 false \ - RX_CB_MASK_1_1 false \ - RX_CB_VAL_1_1 00000000 \ - RX_CB_K_1_1 false \ - RX_CB_DISP_1_1 false \ - RX_CB_MASK_1_2 false \ - RX_CB_VAL_1_2 00000000 \ - RX_CB_K_1_2 false \ - RX_CB_DISP_1_2 false \ - RX_CB_MASK_1_3 false \ - RX_CB_VAL_1_3 00000000 \ - RX_CB_K_1_3 false \ - RX_CB_DISP_1_3 false \ - RX_CC_NUM_SEQ 0 \ - RX_CC_LEN_SEQ 1 \ - RX_CC_PERIODICITY 5000 \ - RX_CC_KEEP_IDLE DISABLE \ - RX_CC_PRECEDENCE ENABLE \ - RX_CC_REPEAT_WAIT 0 \ - RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ - RX_CC_MASK_0_0 false \ - RX_CC_VAL_0_0 00000000 \ - RX_CC_K_0_0 false \ - RX_CC_DISP_0_0 false \ - RX_CC_MASK_0_1 false \ - RX_CC_VAL_0_1 00000000 \ - RX_CC_K_0_1 false \ - RX_CC_DISP_0_1 false \ - RX_CC_MASK_0_2 false \ - RX_CC_VAL_0_2 00000000 \ - RX_CC_K_0_2 false \ - RX_CC_DISP_0_2 false \ - RX_CC_MASK_0_3 false \ - RX_CC_VAL_0_3 00000000 \ - RX_CC_K_0_3 false \ - RX_CC_DISP_0_3 false \ - RX_CC_MASK_1_0 false \ - RX_CC_VAL_1_0 00000000 \ - RX_CC_K_1_0 false \ - RX_CC_DISP_1_0 false \ - RX_CC_MASK_1_1 false \ - RX_CC_VAL_1_1 00000000 \ - RX_CC_K_1_1 false \ - RX_CC_DISP_1_1 false \ - RX_CC_MASK_1_2 false \ - RX_CC_VAL_1_2 00000000 \ - RX_CC_K_1_2 false \ - RX_CC_DISP_1_2 false \ - RX_CC_MASK_1_3 false \ - RX_CC_VAL_1_3 00000000 \ - RX_CC_K_1_3 false \ - RX_CC_DISP_1_3 false \ - PCIE_USERCLK2_FREQ 250 \ - PCIE_USERCLK_FREQ 250 \ - RX_JTOL_FC 10 \ - RX_JTOL_LF_SLOPE -20 \ - RX_BUFFER_BYPASS_MODE Fast_Sync \ - RX_BUFFER_BYPASS_MODE_LANE MULTI \ - RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ - RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ - RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - RESET_SEQUENCE_INTERVAL 0 \ - RX_COMMA_PRESET NONE \ - RX_COMMA_VALID_ONLY 0 \ - ] \ - CONFIG.PROT1_NO_OF_TX_LANES $tx_num_lanes \ - CONFIG.PROT1_PRESET ${transceiver}-JESD204_${jesd_mode} \ - ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] - - for {set i 0} {$i < 4} {incr i} { - set_property -dict [list \ - CONFIG.TX${i}_LANE_SEL.VALUE_MODE MANUAL \ - CONFIG.RX${i}_LANE_SEL.VALUE_MODE MANUAL \ - ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] - } - } - - if {$intf_cfg != "TX"} { - # Share the link clock generated by the first quad - if {$j == 0} { - ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx - ad_connect ${ip_name}/gt_quad_base_0/ch0_rxoutclk ${ip_name}/bufg_gt_rx/outclk - ad_connect ${ip_name}/${rx_bridge}/rx_clr_out ${ip_name}/bufg_gt_rx/gt_bufgtclr - ad_connect ${ip_name}/${rx_bridge}/rxusrclk_out ${ip_name}/rxusrclk_out - ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/${rx_bridge}/gt_rxusrclk - } - create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_p - create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_n - ad_connect ${ip_name}/gt_quad_base_${j}/rxp ${ip_name}/rx_${j}_p - ad_connect ${ip_name}/gt_quad_base_${j}/rxn ${ip_name}/rx_${j}_n - } - if {$intf_cfg != "RX"} { - # Share the link clock generated by the first quad - if {$j == 0} { - ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx - ad_connect ${ip_name}/gt_quad_base_0/ch0_txoutclk ${ip_name}/bufg_gt_tx/outclk - ad_connect ${ip_name}/${tx_bridge}/tx_clr_out ${ip_name}/bufg_gt_tx/gt_bufgtclr - ad_connect ${ip_name}/${tx_bridge}/txusrclk_out ${ip_name}/txusrclk_out - ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/${tx_bridge}/gt_txusrclk - } - create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_p - create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_n - ad_connect ${ip_name}/gt_quad_base_${j}/txp ${ip_name}/tx_${j}_p - ad_connect ${ip_name}/gt_quad_base_${j}/txn ${ip_name}/tx_${j}_n - } - } - - if {$intf_cfg != "TX"} { - for {set j 0} {$j < $rx_num_lanes} {incr j} { - set quad_index [expr int($j / 4)] - set rx_index [expr $j % 4] - - ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_quad_base_${quad_index}/ch${rx_index}_rxusrclk - - ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} [list \ - LINK_MODE $link_mode \ - ] - ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/${rx_bridge}/GT_RX${j}_EXT - ad_connect ${ip_name}/${rx_bridge}/GT_RX${j} ${ip_name}/gt_quad_base_${quad_index}/RX${rx_index}_GT_IP_Interface - - create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j} - ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX - ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_rx/usrclk - ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align - - set_property CONFIG.RX${rx_index}_LANE_SEL {PROT0} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] - } - } - if {$intf_cfg != "RX"} { - for {set j 0} {$j < $tx_num_lanes} {incr j} { - set quad_index [expr int($j / 4)] - set tx_index [expr $j % 4] - - ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_quad_base_${quad_index}/ch${tx_index}_txusrclk - - ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} [list \ - LINK_MODE $link_mode \ - ] - ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/${tx_bridge}/GT_TX${j}_EXT - ad_connect ${ip_name}/${tx_bridge}/GT_TX${j} ${ip_name}/gt_quad_base_${quad_index}/TX${tx_index}_GT_IP_Interface - - create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j} - ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX - ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_tx/usrclk - - if {!$asymmetric_mode} { - set_property CONFIG.TX${tx_index}_LANE_SEL {PROT0} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] - } else { - set_property CONFIG.TX${tx_index}_LANE_SEL {PROT1} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] - } - } - } - - # Map unused quad lanes as unconnected - set max_num_of_lanes [expr $num_quads * 4] - for {set j $rx_num_lanes} {$j < $max_num_of_lanes} {incr j} { - set quad_index [expr $j / 4] - set lane_index [expr $j % 4] - set_property CONFIG.RX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] - } - for {set j $tx_num_lanes} {$j < $max_num_of_lanes} {incr j} { - set quad_index [expr $j / 4] - set lane_index [expr $j % 4] - set_property CONFIG.TX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] - } - - # Clocks - ad_connect ${ip_name}/s_axi_clk ${ip_name}/${rx_bridge}/apb3clk - if {$asymmetric_mode} { - ad_connect ${ip_name}/s_axi_clk ${ip_name}/${tx_bridge}/apb3clk - } - for {set j 0} {$j < $num_quads} {incr j} { - ad_connect ${ip_name}/GT_REFCLK ${ip_name}/gt_quad_base_${j}/GT_REFCLK0 - ad_connect ${ip_name}/s_axi_clk ${ip_name}/gt_quad_base_${j}/s_axi_lite_clk - ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gt_quad_base_${j}/s_axi_lite_resetn - } - - # Instantiate reset helper logic - create_reset_logic $ip_name $rx_num_lanes $tx_num_lanes -} diff --git a/projects/ad9084_ebz/vck190/Makefile b/projects/ad9084_ebz/vck190/Makefile index 23c3c73d63a..3356a10ba88 100755 --- a/projects/ad9084_ebz/vck190/Makefile +++ b/projects/ad9084_ebz/vck190/Makefile @@ -6,7 +6,6 @@ PROJECT_NAME := ad9084_ebz_vck190 -M_DEPS += ../common/versal_transceiver.tcl M_DEPS += ../common/versal_hsci_phy.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/xilinx/dacfifo_bd.tcl @@ -15,6 +14,7 @@ M_DEPS += ../../common/vmk180/vmk180_system_bd.tcl M_DEPS += ../../common/vck190/vck190_system_constr.xdc M_DEPS += ../../common/vck190/vck190_system_bd.tcl M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_bd.tcl +M_DEPS += ../../../library/xilinx/scripts/versal_xcvr_subsystem.tcl M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/common/ad_iobuf.v diff --git a/projects/ad9084_ebz/vck190/system_project.tcl b/projects/ad9084_ebz/vck190/system_project.tcl index f6623ffd102..59274998c11 100755 --- a/projects/ad9084_ebz/vck190/system_project.tcl +++ b/projects/ad9084_ebz/vck190/system_project.tcl @@ -78,7 +78,7 @@ adi_project_files ad9084_ebz_vck190 [list \ "system_constr.xdc" \ "timing_constr.tcl" \ "../common/versal_hsci_phy.tcl" \ - "../common/versal_transceiver.tcl" \ + "$ad_hdl_dir/library/xilinx/scripts/versal_xcvr_subsystem.tcl" \ "$ad_hdl_dir/library/common/ad_3w_spi.v" \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc" ] diff --git a/projects/ad9084_ebz/vck190/timing_constr.tcl b/projects/ad9084_ebz/vck190/timing_constr.tcl index 58ea6fef0ae..fd36e7836c5 100755 --- a/projects/ad9084_ebz/vck190/timing_constr.tcl +++ b/projects/ad9084_ebz/vck190/timing_constr.tcl @@ -9,11 +9,11 @@ # Maximum values for Link clock: # 204B - 15.5 Gbps /40 = 387.5MHz # 204C - 24.75 Gbps /66 = 375MHz -set jesd_mode [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] INTERNAL_PRESET] +set jesd_mode [dict get [dict get [get_property QUAD0_PROT0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/xcvr/inst]] LR0_SETTINGS] INTERNAL_PRESET] set link_mode [expr {$jesd_mode=="JESD204_64B66B" ? 2:1}] -set rx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] RX_LINE_RATE] -set tx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] TX_LINE_RATE] +set rx_lane_rate [dict get [dict get [get_property QUAD0_PROT0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/xcvr/inst]] LR0_SETTINGS] RX_LINE_RATE] +set tx_lane_rate [dict get [dict get [get_property QUAD0_PROT1_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/xcvr/inst]] LR0_SETTINGS] TX_LINE_RATE] set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] diff --git a/projects/ad9084_ebz/vpk180/Makefile b/projects/ad9084_ebz/vpk180/Makefile index 30c02fb36e4..0bff4061677 100755 --- a/projects/ad9084_ebz/vpk180/Makefile +++ b/projects/ad9084_ebz/vpk180/Makefile @@ -6,7 +6,6 @@ PROJECT_NAME := ad9084_ebz_vpk180 -M_DEPS += ../common/versal_transceiver.tcl M_DEPS += ../common/versal_hsci_phy.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/xilinx/dacfifo_bd.tcl @@ -14,6 +13,7 @@ M_DEPS += ../../common/xilinx/adcfifo_bd.tcl M_DEPS += ../../common/vpk180/vpk180_system_constr.xdc M_DEPS += ../../common/vpk180/vpk180_system_bd.tcl M_DEPS += ../../ad9084_ebz/common/ad9084_ebz_bd.tcl +M_DEPS += ../../../library/xilinx/scripts/versal_xcvr_subsystem.tcl M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/common/ad_iobuf.v diff --git a/projects/ad9084_ebz/vpk180/system_project.tcl b/projects/ad9084_ebz/vpk180/system_project.tcl index b2d8e8785ef..9cd339386bc 100755 --- a/projects/ad9084_ebz/vpk180/system_project.tcl +++ b/projects/ad9084_ebz/vpk180/system_project.tcl @@ -78,7 +78,7 @@ adi_project_files ad9084_ebz_vpk180 [list \ "system_constr.xdc" \ "timing_constr.tcl" \ "../common/versal_hsci_phy.tcl" \ - "../common/versal_transceiver.tcl" \ + "$ad_hdl_dir/library/xilinx/scripts/versal_xcvr_subsystem.tcl" \ "$ad_hdl_dir/library/common/ad_3w_spi.v" \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vpk180/vpk180_system_constr.xdc" ] diff --git a/projects/ad9084_ebz/vpk180/timing_constr.tcl b/projects/ad9084_ebz/vpk180/timing_constr.tcl index 58ea6fef0ae..7fe95b59178 100755 --- a/projects/ad9084_ebz/vpk180/timing_constr.tcl +++ b/projects/ad9084_ebz/vpk180/timing_constr.tcl @@ -9,11 +9,11 @@ # Maximum values for Link clock: # 204B - 15.5 Gbps /40 = 387.5MHz # 204C - 24.75 Gbps /66 = 375MHz -set jesd_mode [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] INTERNAL_PRESET] +set jesd_mode [dict get [dict get [get_property QUAD0_PROT0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/xcvr/inst]] LR0_SETTINGS] INTERNAL_PRESET] set link_mode [expr {$jesd_mode=="JESD204_64B66B" ? 2:1}] -set rx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] RX_LINE_RATE] -set tx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] TX_LINE_RATE] +set rx_lane_rate [dict get [dict get [get_property QUAD0_PROT0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/xcvr/inst]] LR0_SETTINGS] RX_LINE_RATE] +set tx_lane_rate [dict get [dict get [get_property QUAD0_PROT1_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/xcvr/inst]] LR0_SETTINGS] TX_LINE_RATE] set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] @@ -35,7 +35,7 @@ set tx_device_clk_period [expr 1000/$tx_device_clk] # Set reference clock to same frequency as the link clock, # this will ease the XCVR out clocks propagation calculation. # TODO: this restricts RX_LANE_RATE=TX_LANE_RATE -create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p[0]] +create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p] # device clock create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clk_m2c_p[0]] From 948e1513711826021227556ce4c93f84f1f41188 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Tue, 30 Sep 2025 17:58:01 +0300 Subject: [PATCH 12/15] library: xilinx: scripts: versal_xcvr_subsystem: Remove unused source Signed-off-by: Bogdan Luncan --- library/xilinx/scripts/versal_xcvr_subsystem.tcl | 2 -- 1 file changed, 2 deletions(-) diff --git a/library/xilinx/scripts/versal_xcvr_subsystem.tcl b/library/xilinx/scripts/versal_xcvr_subsystem.tcl index 3fa4e612f85..fcbf0ec30e8 100644 --- a/library/xilinx/scripts/versal_xcvr_subsystem.tcl +++ b/library/xilinx/scripts/versal_xcvr_subsystem.tcl @@ -3,8 +3,6 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source ../../../projects/scripts/adi_board.tcl - # Parameter description: # ip_name : The name of the created ip # jesd_mode : Used physical layer encoder mode From a8bb1b141fdfb69e3359967c9ca233c2f465e192 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Wed, 1 Oct 2025 15:08:44 +0300 Subject: [PATCH 13/15] projects: ad9084_ebz: versal: Fix AION cs line Signed-off-by: Bogdan Luncan --- projects/ad9084_ebz/vck190/system_top.v | 4 ++-- projects/ad9084_ebz/vpk180/system_top.v | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/projects/ad9084_ebz/vck190/system_top.v b/projects/ad9084_ebz/vck190/system_top.v index 42baae8e419..25bea424cf2 100755 --- a/projects/ad9084_ebz/vck190/system_top.v +++ b/projects/ad9084_ebz/vck190/system_top.v @@ -262,9 +262,9 @@ module system_top #( .O (tx_device_clk)); // spi - assign spi2_cs[1:0] = spi_csn[1:0]; - assign spi2_cs[4] = spi_csn[2]; assign spi2_sclk = spi_clk; + assign spi2_cs[1:0] = spi_csn[1:0]; + assign spi2_cs[4] = spi_csn[2]; ad_3w_spi #( .NUM_OF_SLAVES(3) diff --git a/projects/ad9084_ebz/vpk180/system_top.v b/projects/ad9084_ebz/vpk180/system_top.v index 4c01e13a8e1..37f35b08a15 100755 --- a/projects/ad9084_ebz/vpk180/system_top.v +++ b/projects/ad9084_ebz/vpk180/system_top.v @@ -282,8 +282,9 @@ module system_top #( .O (tx_device_clk)); // spi - assign spi2_cs[5:0] = spi_csn[5:0]; assign spi2_sclk = spi_clk; + assign spi2_cs[1:0] = spi_csn[1:0]; + assign spi2_cs[4] = spi_csn[2]; ad_3w_spi #( .NUM_OF_SLAVES(3) From 9719b71b78350a66b17e4876a3247f34f67f347a Mon Sep 17 00:00:00 2001 From: Filip Gherman Date: Tue, 14 Oct 2025 13:56:10 +0300 Subject: [PATCH 14/15] projects: ad9084_ebz: vcu118: Fix AION CS line Signed-off-by: Filip Gherman --- projects/ad9084_ebz/vcu118/system_top.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/ad9084_ebz/vcu118/system_top.v b/projects/ad9084_ebz/vcu118/system_top.v index 189ef4cc34a..3012b2a071e 100755 --- a/projects/ad9084_ebz/vcu118/system_top.v +++ b/projects/ad9084_ebz/vcu118/system_top.v @@ -315,7 +315,7 @@ module system_top #( ad_3w_spi #( .NUM_OF_SLAVES(3) ) i_spi ( - .spi_csn (spi_csn[2:0]), + .spi_csn ({spi_csn[4], spi_csn[1:0]}), .spi_clk (spi_clk), .spi_mosi (spi_sdio), .spi_miso (spi_sdo), From afa347c8d5efe02c66b7bf4c0e4e84c4c36ba8cc Mon Sep 17 00:00:00 2001 From: Filip Gherman Date: Tue, 30 Sep 2025 20:36:32 +0300 Subject: [PATCH 15/15] projects: ad9084_ebz: vcu118: Add support for single-link mode Signed-off-by: Filip Gherman --- projects/ad9084_ebz/common/ad9084_ebz_bd.tcl | 66 +++++++++++++------ projects/ad9084_ebz/vcu118/system_project.tcl | 6 +- projects/ad9084_ebz/vcu118/system_top.v | 6 +- 3 files changed, 52 insertions(+), 26 deletions(-) diff --git a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl index 030b3d0e011..d5a9b390c69 100755 --- a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl +++ b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl @@ -491,7 +491,7 @@ ad_ip_parameter axi_apollo_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096 ad_ip_parameter axi_apollo_rx_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_data_width if {$ADI_PHY_SEL} { - ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_data_width + ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(1024, $adc_data_width)] } else { # Versal limitation ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_data_width)] @@ -592,7 +592,7 @@ ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_apollo_tx_dma CONFIG.CYCLIC 1 ad_ip_parameter axi_apollo_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096 if {$ADI_PHY_SEL} { - ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC $dac_data_width + ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(1024, $dac_data_width)] } else { # Versal limitation ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_data_width)] @@ -797,16 +797,24 @@ if {$ASYMMETRIC_A_B_MODE} { } } else { set max_lane_map {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23} - # set lane_map {} - - # for {set i 0} {$i < $RX_NUM_LINKS} {incr i} { - # for {set j 0} {$j < $RX_JESD_L} {incr j} { - # set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j] - # lappend lane_map [lindex $max_lane_map $cur_lane] - # } - # } + set lane_map {} + + for {set i 0} {$i < $RX_NUM_LINKS} {incr i} { + for {set j 0} {$j < $RX_JESD_L} {incr j} { + set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j] + lappend lane_map [lindex $max_lane_map $cur_lane] + } + } + + for {set i 0} {$i < $RX_NUM_LINKS} {incr i} { + for {set j $RX_JESD_L} {$j < $MAX_RX_LANES_PER_LINK} {incr j} { + set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j] + lappend lane_map [lindex $max_lane_map $cur_lane] + } + } + if {$ADI_PHY_SEL} { - ad_xcvrcon util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd $max_lane_map {} rx_device_clk $MAX_RX_LANES + ad_xcvrcon util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd $lane_map {} rx_device_clk $MAX_RX_LANES create_bd_port -dir I rx_sysref_12 create_bd_port -dir O rx_sync_12 } @@ -828,16 +836,34 @@ if {$ASYMMETRIC_A_B_MODE} { } } else { set max_lane_map {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23} - # set lane_map {} - - # for {set i 0} {$i < $TX_NUM_LINKS} {incr i} { - # for {set j 0} {$j < $TX_JESD_L} {incr j} { - # set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j] - # lappend lane_map [lindex $max_lane_map $cur_lane] - # } - # } + set lane_map {} + + for {set i 0} {$i < $TX_NUM_LINKS} {incr i} { + for {set j 0} {$j < $TX_JESD_L} {incr j} { + set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j] + lappend lane_map [lindex $max_lane_map $cur_lane] + } + } + + for {set i 0} {$i < $TX_NUM_LINKS} {incr i} { + for {set j $TX_JESD_L} {$j < $MAX_TX_LANES_PER_LINK} {incr j} { + set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j] + lappend lane_map [lindex $max_lane_map $cur_lane] + } + } + if {$ADI_PHY_SEL} { - ad_xcvrcon util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd $max_lane_map {} tx_device_clk $MAX_TX_LANES + ad_xcvrcon util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd $lane_map {} tx_device_clk $MAX_TX_LANES + + if {$TX_JESD_L == 8} { + delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_8] + delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_12] + connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_8] [get_bd_intf_pins util_apollo_xcvr/up_cm_12] + connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_12] [get_bd_intf_pins util_apollo_xcvr/up_cm_16] + } elseif {$TX_JESD_L == 4} { + delete_bd_objs [get_bd_intf_nets axi_apollo_tx_xcvr_up_cm_4] + connect_bd_intf_net [get_bd_intf_pins axi_apollo_tx_xcvr/up_cm_4] [get_bd_intf_pins util_apollo_xcvr/up_cm_12] + } create_bd_port -dir I tx_sysref_12 create_bd_port -dir I tx_sync_12 } diff --git a/projects/ad9084_ebz/vcu118/system_project.tcl b/projects/ad9084_ebz/vcu118/system_project.tcl index 4c761cea8c3..24eb3659a3d 100755 --- a/projects/ad9084_ebz/vcu118/system_project.tcl +++ b/projects/ad9084_ebz/vcu118/system_project.tcl @@ -48,15 +48,15 @@ adi_project ad9084_ebz_vcu118 0 [list \ RX_JESD_L [get_env_param RX_JESD_L 8 ] \ RX_JESD_S [get_env_param RX_JESD_S 1 ] \ RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 2 ] \ TX_JESD_M [get_env_param TX_JESD_M 4 ] \ TX_JESD_L [get_env_param TX_JESD_L 8 ] \ TX_JESD_S [get_env_param TX_JESD_S 1 ] \ TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 2 ] \ RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \ TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 32 ] \ - ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 1 ] \ + ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0 ] \ RX_B_LANE_RATE [get_env_param RX_B_LANE_RATE 20.625 ] \ TX_B_LANE_RATE [get_env_param TX_B_LANE_RATE 20.625 ] \ RX_B_JESD_M [get_env_param RX_B_JESD_M 4 ] \ diff --git a/projects/ad9084_ebz/vcu118/system_top.v b/projects/ad9084_ebz/vcu118/system_top.v index 3012b2a071e..18e3a890a24 100755 --- a/projects/ad9084_ebz/vcu118/system_top.v +++ b/projects/ad9084_ebz/vcu118/system_top.v @@ -36,9 +36,9 @@ `timescale 1ns/100ps module system_top #( - parameter TX_NUM_LINKS = 1, - parameter RX_NUM_LINKS = 1, - parameter ASYMMETRIC_A_B_MODE = 1 + parameter TX_NUM_LINKS = 2, + parameter RX_NUM_LINKS = 2, + parameter ASYMMETRIC_A_B_MODE = 0 ) ( input sys_rst, input sys_clk_p,