projects: ad9084_ebz: Initial design#1901

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bluncan wants to merge 16 commits intomainfrom

dev_apollo_pr

Commits on Oct 31, 2025

projects: ad9084_fmca_ebz: Initial commit

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ad9084_ebz/common: Use on source

gastmaier
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fix: ad9084_ebz/common: Invalid hsci clock with ADI_PHY 1

gastmaier
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apollo: spi: Set 4 wire spi through parameters

gastmaier
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FilipG24
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ad9084_ebz/vcu118: Fix spi2 by adding a clear muxing logic between 3w/4w and unused slave devices

Filip.Gherman
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projects: ad9084_ebz: Change spi to 3 wire

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projects: ad9084_ebz: common: ad9084_ebz_bd.tcl: Migrate to inline utility cores

bluncan
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projects: ad9084_ebz: versal: Update constraints to read the lane rate automatically

bluncan
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projects: ad9084_ebz: Add readme file

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projects: ad9084_ebz: fm87: system_project: Remove unused parameters from description

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projects: ad9084_ebz: versal: Update to the new Transceiver Subsystem

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library: xilinx: scripts: versal_xcvr_subsystem: Remove unused source

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projects: ad9084_ebz: versal: Fix AION cs line

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projects: ad9084_ebz: vcu118: Fix AION CS line
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projects: ad9084_ebz: vcu118: Add support for single-link mode
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projects: ad9084_ebz: vcu118: Improve timing for the single-link mode
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projects: ad9084_ebz: Initial design#1901

projects: ad9084_ebz: Initial design#1901
bluncan wants to merge 16 commits intomainfrom
dev_apollo_pr

Commits on Oct 31, 2025

projects: ad9084_fmca_ebz: Initial commit

ad9084_ebz/common: Use on source

fix: ad9084_ebz/common: Invalid hsci clock with ADI_PHY 1

apollo: spi: Set 4 wire spi through parameters

ad9084_ebz/vcu118: Fix spi2 by adding a clear muxing logic between 3w/4w and unused slave devices

projects: ad9084_ebz: Change spi to 3 wire

projects: ad9084_ebz: common: ad9084_ebz_bd.tcl: Migrate to inline utility cores

projects: ad9084_ebz: versal: Update constraints to read the lane rate automatically

projects: ad9084_ebz: Add readme file

projects: ad9084_ebz: fm87: system_project: Remove unused parameters from description

projects: ad9084_ebz: versal: Update to the new Transceiver Subsystem

library: xilinx: scripts: versal_xcvr_subsystem: Remove unused source

projects: ad9084_ebz: versal: Fix AION cs line

projects: ad9084_ebz: vcu118: Fix AION CS line

projects: ad9084_ebz: vcu118: Add support for single-link mode

projects: ad9084_ebz: vcu118: Improve timing for the single-link mode

projects: ad9084_ebz: Initial design#1901bluncan wants to merge 16 commits intomainanalogdevicesinc/hdl:mainfrom dev_apollo_pranalogdevicesinc/hdl:dev_apollo_prCopy head branch name to clipboard

Commits

Commits on Oct 31, 2025

projects: ad9084_ebz: Initial design#1901
bluncan wants to merge 16 commits intomainfrom
dev_apollo_pr