From 8672223b116984d7a05eb53dc3f05d0c6bc2d3cc Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Wed, 13 Aug 2025 16:33:31 +0300 Subject: [PATCH] projects/cn0577: Remove ADAQ2387x from CN0577 - docs/projects/cn0577: Removed the ADAQ2387X supported boards from the CN0577 documentation, because now they have a separate documentation page - projects/cn0577: Update parameters' details - projects/cn0577: Add clarification in comments Signed-off-by: Iulia Moldovan - docs/projects/cn0577: Fix doc to reflect actual supported parts - projects/cn0577: Remove ADC_RES related info Signed-off-by: Stanca Pop --- .../cn0577/cn0577_zed_block_diagram.svg | 14 +++++------ docs/projects/cn0577/index.rst | 15 +++-------- projects/cn0577/README.md | 7 ------ projects/cn0577/common/cn0577_bd.tcl | 16 ++++++------ projects/cn0577/zed/README.md | 25 ++----------------- projects/cn0577/zed/system_bd.tcl | 3 +-- projects/cn0577/zed/system_constr.xdc | 4 +-- projects/cn0577/zed/system_project.tcl | 9 +------ 8 files changed, 24 insertions(+), 69 deletions(-) diff --git a/docs/projects/cn0577/cn0577_zed_block_diagram.svg b/docs/projects/cn0577/cn0577_zed_block_diagram.svg index ea31a5e7849..129453e1692 100644 --- a/docs/projects/cn0577/cn0577_zed_block_diagram.svg +++ b/docs/projects/cn0577/cn0577_zed_block_diagram.svg @@ -847,16 +847,16 @@ inkscape:pageopacity="0.0" inkscape:pageshadow="2" inkscape:zoom="1.4142136" - inkscape:cx="235.82011" - inkscape:cy="278.60006" + inkscape:cx="220.97086" + inkscape:cy="278.95362" inkscape:document-units="px" inkscape:current-layer="layer1" showgrid="false" units="px" - inkscape:window-width="1680" - inkscape:window-height="979" - inkscape:window-x="-8" - inkscape:window-y="-8" + inkscape:window-width="1920" + inkscape:window-height="1112" + inkscape:window-x="197" + inkscape:window-y="1342" inkscape:window-maximized="1" showguides="true" inkscape:pagecheckerboard="0" @@ -2037,7 +2037,7 @@ sodipodi:role="line" id="tspan2399-9-2-7-4" x="292.12854" - y="695.64124">16/18 + y="695.64124">18 `__ diff --git a/projects/cn0577/README.md b/projects/cn0577/README.md index 125b6fa4ca4..6a9adfacb34 100644 --- a/projects/cn0577/README.md +++ b/projects/cn0577/README.md @@ -2,9 +2,6 @@ - Evaluation board product page: - [EVAL-CN0577](https://www.analog.com/cn0577) - - [EVAL-ADAQ23878](https://analog.com/eval-adaq23878) - - [EVAL-ADAQ23876](https://analog.com/eval-adaq23876) - - [EVAL-ADAQ23875](https://analog.com/eval-adaq23875) - System documentation: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577 - HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/cn0577/index.html - Evaluation board VADJ: 2.5V @@ -14,10 +11,6 @@ | Part name | Description | |-----------------------------------------|-----------------------------------------------------------| | [LTC2387-18](https://www.analog.com/LTC2387-18) | 18-Bit, 15 MSPS, SAR ADC | -| [LTC2387-16](https://www.analog.com/LTC2387-16) | 16-Bit, 15 MSPS, SAR ADC | -| [ADAQ23878](https://www.analog.com/ADAQ23878) | 18-Bit, 15 MSPS, μModule Data Acquisition Solution | -| [ADAQ23876](https://www.analog.com/ADAQ23876) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution | -| [ADAQ23875](https://www.analog.com/ADAQ23875) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution | ## Building the project diff --git a/projects/cn0577/common/cn0577_bd.tcl b/projects/cn0577/common/cn0577_bd.tcl index b1fe8d24c89..34c982d4464 100644 --- a/projects/cn0577/common/cn0577_bd.tcl +++ b/projects/cn0577/common/cn0577_bd.tcl @@ -6,12 +6,7 @@ # env params set TWOLANES $ad_project_params(TWOLANES); # two-lane mode (1) or one-lane mode (0); default two-lane -set ADC_RES $ad_project_params(ADC_RES); # ADC resolution; default 18 bits -set OUT_RES [expr {$ADC_RES == 16 ? 16 : 32}] -set CLK_GATE_WIDTH [expr {($TWOLANES == 0 && $ADC_RES == 18) ? 9 : \ - ($TWOLANES == 0 && $ADC_RES == 16) ? 8 : \ - ($TWOLANES == 1 && $ADC_RES == 18) ? 5 : \ - 4}] +set CLK_GATE_WIDTH [expr {($TWOLANES == 0) ? 9 : 5}] # ltc2387 i/o @@ -29,8 +24,8 @@ create_bd_port -dir O clk_gate # adc peripheral ad_ip_instance axi_ltc2387 axi_ltc2387 -ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES $ADC_RES -ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES $OUT_RES +ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES 18 +ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES 32 ad_ip_parameter axi_ltc2387 CONFIG.TWOLANES $TWOLANES ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 27 @@ -38,8 +33,11 @@ ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 27 ad_ip_instance axi_pwm_gen axi_pwm_gen ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 2 +# pwm0 - cnv ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1 +# period 8 when 120MHz clock (120MHz/8=15MSPS) ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 8 +# pwm1 - clk_gate ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_WIDTH $CLK_GATE_WIDTH ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_PERIOD 8 ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_OFFSET 0 @@ -54,7 +52,7 @@ ad_ip_parameter axi_ltc2387_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC $OUT_RES +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC 32 ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_DEST 64 # connections diff --git a/projects/cn0577/zed/README.md b/projects/cn0577/zed/README.md index 04ab8cd9802..39fd833e085 100644 --- a/projects/cn0577/zed/README.md +++ b/projects/cn0577/zed/README.md @@ -18,9 +18,6 @@ The overwritable parameters from the environment are: - TWOLANES: whether to use two lanes or one lane mode; - 1 - two-lane mode used (default) - 0 - one-lane mode used -- ADC_RES: the resolution of the ADC input data; - - 18 - the resolution is 18 bits (default) - - 16 - the resolution is 16 bits ### Example configurations @@ -29,8 +26,7 @@ The overwritable parameters from the environment are: This specific command is equivalent to running `make` only: ``` -make TWOLANES=1 \ -ADC_RES=18 +make TWOLANES=1 ``` Corresponding device tree: [zynq-zed-adv7511-cn0577.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-cn0577.dts) @@ -38,22 +34,5 @@ Corresponding device tree: [zynq-zed-adv7511-cn0577.dts](https://github.com/anal #### One lane, 18-bit resolution ``` -make TWOLANES=0 \ -ADC_RES=18 -``` - -#### Two lanes, 16-bit resolution - -``` -make TWOLANES=1 \ -ADC_RES=16 -``` - -Corresponding device tree: [zynq-zed-adv7511-adaq23875.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq23875.dts) - -#### One lane, 16-bit resolution - -``` -make TWOLANES=0 \ -ADC_RES=16 +make TWOLANES=0 ``` diff --git a/projects/cn0577/zed/system_bd.tcl b/projects/cn0577/zed/system_bd.tcl index a5a019dc41f..78f90cf6e75 100644 --- a/projects/cn0577/zed/system_bd.tcl +++ b/projects/cn0577/zed/system_bd.tcl @@ -12,7 +12,6 @@ ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 -set sys_cstring "TWOLANES=$ad_project_params(TWOLANES) \ -ADC_RES=$ad_project_params(ADC_RES)" +set sys_cstring "TWOLANES=$ad_project_params(TWOLANES)" sysid_gen_sys_init_file $sys_cstring diff --git a/projects/cn0577/zed/system_constr.xdc b/projects/cn0577/zed/system_constr.xdc index 54dd7634c16..bbd069c043f 100644 --- a/projects/cn0577/zed/system_constr.xdc +++ b/projects/cn0577/zed/system_constr.xdc @@ -34,10 +34,10 @@ set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports twolanes_cnt # 120MHz clock set clk_period 8.333 -# differential propagation delay for ref_clk +# differential propagation delay for ref_clk (LVDS_CLK coming from ADN4661, tPHLD) set tref_early 0.3 set tref_late 1.5 -# differential propagation delay for virt_clk +# differential propagation delay for virt_clk (the clock that enters ADG3241 has propagation delay until it exits it and goes to SN47LVC2G74; see ADG data sheet Propagation Delay A to B) set tvirt_early 0 set tvirt_late 0.225 # data delay diff --git a/projects/cn0577/zed/system_project.tcl b/projects/cn0577/zed/system_project.tcl index 3c6fbee9469..d4e9e2ef852 100644 --- a/projects/cn0577/zed/system_project.tcl +++ b/projects/cn0577/zed/system_project.tcl @@ -11,16 +11,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # TWOLANES: parameter describing the number of lanes # - 1: in two-lane mode (default) # - 0: in one-lane mode -# -# ADC_RES: parameter describing the ADC input resolution -# - 18: 18 bits (default) -# - 16: 16 bits -# -# in one-lane mode (TWOLANES=0), only the 18-bit resolution is supported! (ADC_RES=16) adi_project cn0577_zed 0 [list \ - TWOLANES [get_env_param TWOLANES 1 ] \ - ADC_RES [get_env_param ADC_RES 18 ] \ + TWOLANES [get_env_param TWOLANES 1 ] ] adi_project_files cn0577_zed [list \