util_axis_fifo_asym: Updated testbench parameterization and documentation according to HDL changes (#230)

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

Author: IstvanZsSzekely

docs/testbenches/ip_based/util_axis_fifo_asym/index.rst

@@ -42,8 +42,8 @@ The following parameters of this project that can be configured:
    Options: Power of 2, min 8, max 1024
 -  OUTPUT_WIDTH: output data width
    Options: Power of 2, min 8, max 1024
--  FIFO_LIMITED: specifies if the FIFO size can be reduced
-   Options: 0 for reduced, 1 for not reduced
+-  REDUCED_FIFO: specifies if the FIFO size can be reduced
+   Options: 1 for reduced, 0 for not reduced
 -  ADDRESS_WIDTH: address width
    Options: (0 to 4) + log2(width_ratio)
 -  INPUT_CLK: input clock period in ns
@@ -71,7 +71,7 @@ The following configuration files are available:
      - random
    * - OUTPUT_WIDTH
      - random
-   * - FIFO_LIMITED
+   * - REDUCED_FIFO
      - random
    * - ADDRESS_WIDTH
      - random

testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl

@@ -17,10 +17,10 @@ set random_width [expr int(8*pow(2, int(7.0*rand()+1)))]
 set OUTPUT_WIDTH $random_width
 set ad_project_params(OUTPUT_WIDTH) $OUTPUT_WIDTH
 
-set fifo_limited [expr int(rand()*2)]
-set ad_project_params(FIFO_LIMITED) $fifo_limited
+set reduced_fifo [expr int(rand()*2)]
+set ad_project_params(REDUCED_FIFO) $reduced_fifo
 
-if {$fifo_limited} {
+if {$reduced_fifo} {
     if {$INPUT_WIDTH > $OUTPUT_WIDTH} {
         set RATIO $INPUT_WIDTH/$OUTPUT_WIDTH
     } else {

testbenches/ip/util_axis_fifo_asym/system_bd.tcl

@@ -40,7 +40,7 @@ set TKEEP_EN $ad_project_params(TKEEP_EN)
 set TLAST_EN $ad_project_params(TLAST_EN)
 set INPUT_WIDTH $ad_project_params(INPUT_WIDTH)
 set OUTPUT_WIDTH $ad_project_params(OUTPUT_WIDTH)
-set FIFO_LIMITED $ad_project_params(FIFO_LIMITED)
+set REDUCED_FIFO $ad_project_params(REDUCED_FIFO)
 set ADDRESS_WIDTH $ad_project_params(ADDRESS_WIDTH)
 set INPUT_CLK $ad_project_params(INPUT_CLK)
 set OUTPUT_CLK $ad_project_params(OUTPUT_CLK)
@@ -86,8 +86,7 @@ ad_ip_instance util_axis_fifo_asym util_axis_fifo_asym_DUT [list \
   ALMOST_FULL_THRESHOLD 0 \
   TLAST_EN $TLAST_EN \
   TKEEP_EN $TKEEP_EN \
-  FIFO_LIMITED $FIFO_LIMITED \
-  ADDRESS_WIDTH_PERSPECTIVE 0 \
+  REDUCED_FIFO $REDUCED_FIFO \
 ]
 
 ad_connect input_clk util_axis_fifo_asym_DUT/s_axis_aclk