vivado gives opaque error messages: "ERROR: [Synth 8-5809] Error generated from encrypted envelope."

[dsw]

I have spent hours on this with ChatGPT, so I am not posting this error because I am lazy. There has got to be a way to get better error messages out of the build process than this followed only by a file and a line number. How do I get Vivado to tell me the actual error message so that I can debug it?

ERROR: [Synth 8-5809] Error generated from encrypted envelope.

[ChrisKjellqvist]

I've modified my synth scripts to build using the unencrypted version of my source files. Just switch the read_verilog line in the synth script to read from your unencrypted source directory and not from src_post_enc_dir and it'll give you sensible error messages.

[dsw]

Can you please give exact instructions on exactly what to change? Can you just send a .diff file or just make this the default and push it to the repo? Your scripts and makefiles are so convoluted.

…

On Wed, Sep 3, 2025 at 8:16 PM Chris Kjellqvist ***@***.***> wrote: *ChrisKjellqvist* left a comment (aws/aws-fpga#745) <#745 (comment)> I've modified my synth scripts to build using the unencrypted version of my source files. Just switch the read_verilog line in the synth script to read from your unencrypted source directory and not from src_post_enc_dir and it'll give you sensible error messages. — Reply to this email directly, view it on GitHub <#745 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAAL6XGELCL7BDW2AQWWQND3Q6VKJAVCNFSM6AAAAACFSPZH7CVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZTENJRGYZTIMRSGU> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[ChrisKjellqvist]

I don't work for AWS - I just use it, but this is my .tcl. I would guess that they use an encrypted envelope because when you send a .dcp up to the AWS systems to put it on the F2 instance, you're leaking information of your designs (e.g., module names, wire names) which could be proprietary. This is just my guess.

#---- User would replace this section -----

# Reading the .sv and .v files, as proper designs would not require reading
# .vh, nor .inc files
read_verilog -sv [glob ~/<YOUR_CL_DIRECTORY>/design/*v]

This code snippet replaces this part of the existing synth script.

[dsw]

To get error messages out of the build, comment out all of these lines below at the end of hdk/cl/examples/CL_TEMPLATE/build/scripts/encrypt.tcl

Without doing this, we just get opaque error messages. Recommendation to Amazon F2 team:

(1) People programming in Verilog / System Verilog perhaps could be expected to know about xvlog, but even if you use xvlog, it does not report all errors.

(2) So you really might want to put a suggestion in the documentation here https://github.com/aws/aws-fpga/blob/f2/hdk/README.md to comment-out the below lines to get error messages.

exec chmod +w {*}[glob ${src_post_enc_dir}/*]                                   
                                                                                
# encrypt .v/.sv/.vh/inc as verilog files                                       
encrypt -k ${HDK_SHELL_DIR}/build/scripts/vivado_keyfile.txt -lang verilog [glo\
b -nocomplain -- ${src_post_enc_dir}/*.{v,sv,vh,inc}]                           
                                                                                
# encrypt *vhdl files                                                           
encrypt -k ${HDK_SHELL_DIR}/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -q\
uiet [ glob -nocomplain -- ${src_post_enc_dir}/*.vhd? ]                         

[czfpga]

Hi DSW,

Thank you for your feedback. Our team is aware of this issue and is actively working on a solution, which will be released soon. We appreciate your patience and will keep you updated on the progress.