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perf/x86/intel: Add PMU support for ArrowLake-H
JIRA: https://issues.redhat.com/browse/RHEL-20094 upstream ======== commit d3fe6f0 Author: Dapeng Mi <dapeng1.mi@linux.intel.com> Date: Tue Aug 20 07:38:53 2024 +0000 description =========== ArrowLake-H contains 3 different uarchs, LionCove, Skymont and Crestmont. It is different with previous hybrid processors which only contains two kinds of uarchs. This patch adds PMU support for ArrowLake-H processor, adds ARL-H specific events which supports the 3 kinds of uarchs, such as td_retiring_arl_h, and extends some existed format attributes like offcore_rsp to make them be available to support ARL-H as well. Althrough these format attributes like offcore_rsp have been extended to support ARL-H, they can still support the regular hybrid platforms with 2 kinds of uarchs since the helper hybrid_format_is_visible() would filter PMU types and only show the format attribute for available PMUs. Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> Link: https://lkml.kernel.org/r/20240820073853.1974746-5-dapeng1.mi@linux.intel.com Signed-off-by: Michael Petlan <mpetlan@redhat.com>
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‎arch/x86/events/intel/core.c‎

Lines changed: 102 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4598,6 +4598,28 @@ static inline bool erratum_hsw11(struct perf_event *event)
45984598
X86_CONFIG(.event=0xc0, .umask=0x01);
45994599
}
46004600

4601+
static struct event_constraint *
4602+
arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4603+
struct perf_event *event)
4604+
{
4605+
struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4606+
4607+
if (pmu->pmu_type == hybrid_tiny)
4608+
return cmt_get_event_constraints(cpuc, idx, event);
4609+
4610+
return mtl_get_event_constraints(cpuc, idx, event);
4611+
}
4612+
4613+
static int arl_h_hw_config(struct perf_event *event)
4614+
{
4615+
struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4616+
4617+
if (pmu->pmu_type == hybrid_tiny)
4618+
return intel_pmu_hw_config(event);
4619+
4620+
return adl_hw_config(event);
4621+
}
4622+
46014623
/*
46024624
* The HSW11 requires a period larger than 100 which is the same as the BDM11.
46034625
* A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
@@ -5980,6 +6002,37 @@ static struct attribute *lnl_hybrid_events_attrs[] = {
59806002
NULL
59816003
};
59826004

6005+
/* The event string must be in PMU IDX order. */
6006+
EVENT_ATTR_STR_HYBRID(topdown-retiring,
6007+
td_retiring_arl_h,
6008+
"event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0",
6009+
hybrid_big_small_tiny);
6010+
EVENT_ATTR_STR_HYBRID(topdown-bad-spec,
6011+
td_bad_spec_arl_h,
6012+
"event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0",
6013+
hybrid_big_small_tiny);
6014+
EVENT_ATTR_STR_HYBRID(topdown-fe-bound,
6015+
td_fe_bound_arl_h,
6016+
"event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0",
6017+
hybrid_big_small_tiny);
6018+
EVENT_ATTR_STR_HYBRID(topdown-be-bound,
6019+
td_be_bound_arl_h,
6020+
"event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0",
6021+
hybrid_big_small_tiny);
6022+
6023+
static struct attribute *arl_h_hybrid_events_attrs[] = {
6024+
EVENT_PTR(slots_adl),
6025+
EVENT_PTR(td_retiring_arl_h),
6026+
EVENT_PTR(td_bad_spec_arl_h),
6027+
EVENT_PTR(td_fe_bound_arl_h),
6028+
EVENT_PTR(td_be_bound_arl_h),
6029+
EVENT_PTR(td_heavy_ops_adl),
6030+
EVENT_PTR(td_br_mis_adl),
6031+
EVENT_PTR(td_fetch_lat_adl),
6032+
EVENT_PTR(td_mem_bound_adl),
6033+
NULL,
6034+
};
6035+
59836036
/* Must be in IDX order */
59846037
EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
59856038
EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
@@ -5998,6 +6051,21 @@ static struct attribute *mtl_hybrid_mem_attrs[] = {
59986051
NULL
59996052
};
60006053

6054+
EVENT_ATTR_STR_HYBRID(mem-loads,
6055+
mem_ld_arl_h,
6056+
"event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3",
6057+
hybrid_big_small_tiny);
6058+
EVENT_ATTR_STR_HYBRID(mem-stores,
6059+
mem_st_arl_h,
6060+
"event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6",
6061+
hybrid_big_small_tiny);
6062+
6063+
static struct attribute *arl_h_hybrid_mem_attrs[] = {
6064+
EVENT_PTR(mem_ld_arl_h),
6065+
EVENT_PTR(mem_st_arl_h),
6066+
NULL,
6067+
};
6068+
60016069
EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
60026070
EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
60036071
EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
@@ -6021,8 +6089,8 @@ static struct attribute *adl_hybrid_tsx_attrs[] = {
60216089

60226090
FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
60236091
FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
6024-
FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small);
6025-
FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small);
6092+
FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
6093+
FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny);
60266094
FORMAT_ATTR_HYBRID(frontend, hybrid_big);
60276095

60286096
#define ADL_HYBRID_RTM_FORMAT_ATTR \
@@ -6045,7 +6113,7 @@ static struct attribute *adl_hybrid_extra_attr[] = {
60456113
NULL
60466114
};
60476115

6048-
FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small);
6116+
FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny);
60496117

60506118
static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
60516119
ADL_HYBRID_RTM_FORMAT_ATTR,
@@ -7128,6 +7196,37 @@ __init int intel_pmu_init(void)
71287196
name = "lunarlake_hybrid";
71297197
break;
71307198

7199+
case INTEL_ARROWLAKE_H:
7200+
intel_pmu_init_hybrid(hybrid_big_small_tiny);
7201+
7202+
x86_pmu.pebs_latency_data = arl_h_latency_data;
7203+
x86_pmu.get_event_constraints = arl_h_get_event_constraints;
7204+
x86_pmu.hw_config = arl_h_hw_config;
7205+
7206+
td_attr = arl_h_hybrid_events_attrs;
7207+
mem_attr = arl_h_hybrid_mem_attrs;
7208+
tsx_attr = adl_hybrid_tsx_attrs;
7209+
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7210+
mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7211+
7212+
/* Initialize big core specific PerfMon capabilities. */
7213+
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7214+
intel_pmu_init_lnc(&pmu->pmu);
7215+
7216+
/* Initialize Atom core specific PerfMon capabilities. */
7217+
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7218+
intel_pmu_init_skt(&pmu->pmu);
7219+
7220+
/* Initialize Lower Power Atom specific PerfMon capabilities. */
7221+
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
7222+
intel_pmu_init_grt(&pmu->pmu);
7223+
pmu->extra_regs = intel_cmt_extra_regs;
7224+
7225+
intel_pmu_pebs_data_source_arl_h();
7226+
pr_cont("ArrowLake-H Hybrid events, ");
7227+
name = "arrowlake_h_hybrid";
7228+
break;
7229+
71317230
default:
71327231
switch (x86_pmu.version) {
71337232
case 1:

‎arch/x86/events/intel/ds.c‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,17 @@ void __init intel_pmu_pebs_data_source_mtl(void)
176176
__intel_pmu_pebs_data_source_cmt(data_source);
177177
}
178178

179+
void __init intel_pmu_pebs_data_source_arl_h(void)
180+
{
181+
u64 *data_source;
182+
183+
intel_pmu_pebs_data_source_lnl();
184+
185+
data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX].pebs_data_source;
186+
memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
187+
__intel_pmu_pebs_data_source_cmt(data_source);
188+
}
189+
179190
void __init intel_pmu_pebs_data_source_cmt(void)
180191
{
181192
__intel_pmu_pebs_data_source_cmt(pebs_data_source);
@@ -387,6 +398,16 @@ u64 lnl_latency_data(struct perf_event *event, u64 status)
387398
return lnc_latency_data(event, status);
388399
}
389400

401+
u64 arl_h_latency_data(struct perf_event *event, u64 status)
402+
{
403+
struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
404+
405+
if (pmu->pmu_type == hybrid_tiny)
406+
return cmt_latency_data(event, status);
407+
408+
return lnl_latency_data(event, status);
409+
}
410+
390411
static u64 load_latency_data(struct perf_event *event, u64 status)
391412
{
392413
union intel_x86_pebs_dse dse;

‎arch/x86/events/perf_event.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1592,6 +1592,8 @@ u64 cmt_latency_data(struct perf_event *event, u64 status);
15921592

15931593
u64 lnl_latency_data(struct perf_event *event, u64 status);
15941594

1595+
u64 arl_h_latency_data(struct perf_event *event, u64 status);
1596+
15951597
extern struct event_constraint intel_core2_pebs_event_constraints[];
15961598

15971599
extern struct event_constraint intel_atom_pebs_event_constraints[];
@@ -1711,6 +1713,8 @@ void intel_pmu_pebs_data_source_grt(void);
17111713

17121714
void intel_pmu_pebs_data_source_mtl(void);
17131715

1716+
void intel_pmu_pebs_data_source_arl_h(void);
1717+
17141718
void intel_pmu_pebs_data_source_cmt(void);
17151719

17161720
void intel_pmu_pebs_data_source_lnl(void);

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