Add regEnN

Author: kleinreact

clash-prelude/src/Clash/Explicit/Signal.hs

@@ -237,6 +237,7 @@ module Clash.Explicit.Signal
   , register
   , regMaybe
   , regEn
+  , regEnN
   , mux
   , apWhen
     -- * Simulation and testbench functions
@@ -301,7 +302,8 @@ import           Data.Maybe                     (isJust)
 import           GHC.TypeLits                   (type (<=))
 
 import           Clash.Annotations.Primitive    (hasBlackBox)
-import           Clash.Promoted.Nat             (SNat(..), snatToNum)
+import           Clash.Promoted.Nat
+  (SNat(..), SNatLE(..), compareSNat, leToPlus, predSNat, snatToNum)
 import           Clash.Signal.Bundle
   (Bundle (..), EmptyTuple(..), TaggedEmptyTuple(..), vecBundle#)
 import           Clash.Signal.BiSignal
@@ -760,6 +762,35 @@ regEn = \clk rst gen initial en i ->
   register# clk rst (andEnable gen en) initial initial i
 {-# INLINE regEn #-}
 
+-- | A simple queuing FIFO that pushes data through whenever the
+-- enable input line is high. Hence, with every new input the output
+-- at the end of the queue gets updated. Technically, this is nothing
+-- else than a chain of 'regEn's.
+regEnN ::
+  forall dom a n.
+  (KnownDomain dom, NFDataX a) =>
+  Clock dom ->
+  -- ^ Clock
+  Reset dom ->
+  -- ^ Reset, 'regEnN' outputs the reset value when the reset value is active
+  Enable dom ->
+  -- ^ Global enable
+  SNat n ->
+  -- ^ size of FIFO / number of stored elements
+  a ->
+  -- ^ initial content of the FIFO
+  Signal dom Bool ->
+  -- ^ "push next input" indicator
+  Signal dom a ->
+  -- ^ input stream
+  Signal dom a
+  -- ^ final FIFO element
+regEnN clk rst gen n@SNat initial en = case compareSNat n (SNat @0) of
+  SNatLE -> id
+  SNatGT -> regEn clk rst gen initial en
+          . leToPlus @1 @n (regEnN clk rst gen (predSNat n) initial en)
+{-# INLINE regEnN #-}
+
 -- * Simulation functions
 
 -- | Same as 'simulate', but with the reset line asserted for /n/ cycles. Similar

clash-prelude/src/Clash/Signal.hs

@@ -201,6 +201,7 @@ module Clash.Signal
   , register
   , regMaybe
   , regEn
+  , regEnN
   , mux
   , apWhen
     -- * Simulation and testbench functions
@@ -1202,6 +1203,34 @@ regEn = \initial en i ->
     i
 {-# INLINE regEn #-}
 
+-- | A simple queuing FIFO that pushes data through whenever the
+-- enable input line is high. Hence, with every new input the output
+-- at the end of the queue gets updated. Technically, this is nothing
+-- else than a chain of 'regEn's.
+regEnN ::
+  forall dom a n.
+  (HiddenClockResetEnable dom, NFDataX a) =>
+  SNat n ->
+  -- ^ size of FIFO / number of stored elements
+  a ->
+  -- ^ initial content of the FIFO
+  Signal dom Bool ->
+  -- ^ "push next input" indicator
+  Signal dom a ->
+  -- ^ input stream
+  Signal dom a
+  -- ^ final FIFO element
+regEnN = \sn initial en i ->
+  E.regEnN
+    (fromLabel @(HiddenClockName dom))
+    (fromLabel @(HiddenResetName dom))
+    (fromLabel @(HiddenEnableName dom))
+    sn
+    initial
+    en
+    i
+{-# INLINE regEnN #-}
+
 -- * Signal -> List conversion
 
 -- | Get an infinite list of samples from a 'Signal'