Add tests for #1033

Author: martijnbastiaan

tests/shouldfail/TopEntity/T1033.hs

@@ -0,0 +1,20 @@
+module T1033 where
+
+import Clash.Explicit.Prelude
+import Clash.Prelude (HiddenClock, hasClock)
+import qualified Prelude as P
+
+{-# ANN topEntity
+  (Synthesize
+    { t_name   = "top"
+    , t_inputs = [ PortName "wrong"]
+    , t_output = PortName "theOutput"
+    }
+  )#-}
+topEntity
+  :: (Clock System, Reset System, Enable System)
+  -> Signal System Int
+  -> Signal System Int
+topEntity (clk, rst, en) i =
+  register clk rst en 0 i
+

tests/shouldwork/TopEntity/T1033.hs

@@ -0,0 +1,64 @@
+module T1033 where
+
+import Clash.Explicit.Prelude
+import Clash.Prelude (HiddenClock, hasClock)
+import Data.List
+import System.Environment
+import System.FilePath
+import qualified Prelude as P
+
+{-# ANN topEntity
+  (Synthesize
+    { t_name   = "top"
+    , t_inputs =
+        [ PortName "theHiddenClock"
+        , PortProduct "en_int" [PortName "theEnable", PortName "a"]
+        , PortProduct "int_int_rst" [PortName "b", PortProduct "int_rst" []]
+        ]
+    , t_output = PortName "theOutput"
+    }
+  )#-}
+topEntity
+  :: ( dom ~ System       -- Check whether Clash skips eq constraints
+     , HiddenClock dom )   -- Hidden* consists of some construct and a
+                           -- KnownDomain. We don't want them to split off.
+  => (Enable dom, Signal dom Int)
+  -- ^ We do want Enable/Signal to be split
+  -> (Signal dom Int, (Signal dom Int, Reset dom))
+  -- ^ And we want to do that recursively
+  -> Signal dom Int
+topEntity (en, a) (b, (c, rst)) =
+  register hasClock rst en 0 (a + b + c)
+
+assertIn :: String -> String -> IO ()
+assertIn needle haystack
+  | needle `isInfixOf` haystack = return ()
+  | otherwise                   = P.error $ P.concat [ "Expected:\n\n  ", needle
+                                                     , "\n\nIn:\n\n", haystack ]
+
+-- VHDL test
+main :: FilePath -> IO ()
+main topFile = do
+  content <- readFile topFile
+
+  assertIn "theHiddenClock" content
+  assertIn "en_int_theEnable" content
+  assertIn "en_int_a" content
+  assertIn "int_int_rst_b" content
+  assertIn "int_int_rst_int_rst_0" content
+  assertIn "int_int_rst_int_rst_1" content
+
+mainVHDL :: IO ()
+mainVHDL = do
+  [topFile] <- getArgs
+  main (replaceFileName topFile "top/top.vhdl")
+
+mainVerilog :: IO ()
+mainVerilog = do
+  [topFile] <- getArgs
+  main (replaceFileName topFile "top/top.v")
+
+mainSystemVerilog :: IO ()
+mainSystemVerilog = do
+  [topFile] <- getArgs
+  main (replaceFileName topFile "top/top.sv")

testsuite/Main.hs

@@ -95,6 +95,7 @@ runClashTest = defaultMain $ clashTestRoot
       , runFailingTest ("tests" </> "shouldfail" </> "InvalidPrimitive") [VHDL] ["-itests/shouldfail/InvalidPrimitive"] "InvalidPrimitive" (Just "InvalidPrimitive.json")
       -- Disabled, due to it eating gigabytes of memory:
       -- , runFailingTest ("tests" </> "shouldfail") allTargets [] "RecursivePoly" (Just "??")
+      , runFailingTest ("tests" </> "shouldfail" </> "TopEntity") allTargets [] "T1033" (Just "PortProduct \"wrong\" []")
       ]
     , clashTestGroup "shouldwork"
       [ clashTestGroup "AutoReg"
@@ -382,6 +383,8 @@ runClashTest = defaultMain $ clashTestRoot
         , outputTest ("tests" </> "shouldwork" </> "TopEntity") [Verilog] [] [] "PortNamesWithRTree" "main"
         , runTest "TopEntHOArg" def{entities=Entities ["f", "g"], topEntity=TopEntity "f", hdlSim=False}
         , runTest "T701" def {hdlSim=False,entities=Entities ["mynot", ""]}
+        , runTest "T1033" def {hdlSim=False,entities=Entities ["top", ""], topEntity=TopEntity "top"}
+        , outputTest ("tests" </> "shouldwork" </> "TopEntity") allTargets [] [] "T1033" "main"
         ]
       , clashTestGroup "Unit"
         [ runTest "Imap" def