Merge pull request #3027 from clash-lang/fix_3024

Don't inline function bodies with Synthesize ANN

Author: christiaanb

changelog/2025-10-01T09_36_27+02_00_fix_3024

@@ -0,0 +1 @@
+FIXED: Clash will no longer ignore Synthesize annotations when the function is used in an argument position [#3024](https://github.com/clash-lang/clash-compiler/issues/3024)

clash-lib/src/Clash/Normalize/Transformations/Specialize.hs

@@ -475,11 +475,18 @@ specialize' (TransformContext is0 _) e (Var f, args, ticks) specArgIn = do
                       --    g         | g
                       --    !f and !g | f_g
                       --
+                      -- Finally, we must make sure we do not inline the bodies
+                      -- of functions with a Synthesize annotation, as that would
+                      -- duplicate Clash compiler work. See also issue #3024
                       gTmM <- fmap (UniqMap.lookup g) $ Lens.use bindings
+                      let gBody = if g `elemVarSet` topEnts then
+                                    Nothing
+                                  else
+                                    fmap bindingTerm gTmM
                       return
                         ( specializeName (inl, varName f) (bindingSpec <$> gTmM, varName g)
                         , preferNoInline inl (maybe noUserInline bindingSpec gTmM)
-                        , maybe specArg (Left . (`mkApps` gArgs) . bindingTerm) gTmM
+                        , maybe specArg (Left . (`mkApps` gArgs)) gBody
                         )
                     else return (varName f, inl, specArg)
                 _ -> return (varName f, inl, specArg)

tests/Main.hs

@@ -907,6 +907,7 @@ runClashTest = defaultMain
         , outputTest "Simple" def
         , outputTest "T1771" def
         , runTest "Product" def
+        , outputTest "T3024" def{hdlTargets=[VHDL], hdlLoad = [], hdlSim = []}
         ]
       , clashTestGroup "Testbench"
         [ runTest "TB" def{clashFlags=["-fclash-inline-limit=0"]}

tests/shouldwork/SynthesisAttributes/T3024.hs

@@ -0,0 +1,38 @@
+{-# LANGUAGE  CPP #-}
+module T3024 where
+
+import qualified Prelude as P
+
+import qualified Data.List as List
+import System.Environment (getArgs)
+import System.FilePath ((</>), takeDirectory)
+
+import Clash.Prelude
+import Clash.Annotations.TopEntity
+
+f :: Unsigned 8 -> Unsigned 8
+f x = x + 1
+{-# ANN f (Synthesize {t_name = "f", t_inputs = [PortName "x"], t_output = PortName "y"}) #-}
+{-# CLASH_OPAQUE f #-}
+
+g :: (Unsigned 8 -> Unsigned 8) -> Unsigned 8 -> Unsigned 8
+g h x = (h x + h (x * 8))
+{-# CLASH_OPAQUE g #-}
+
+q :: Unsigned 8 -> Unsigned 8
+q = g f
+{-# ANN q (Synthesize {t_name = "q", t_inputs = [PortName "a"], t_output = PortName "b"}) #-}
+{-# CLASH_OPAQUE q #-}
+
+assertIn :: String -> String -> IO ()
+assertIn needle haystack
+  | List.isInfixOf needle haystack = pure ()
+  | otherwise = P.error $ mconcat
+      [ "Expected:\n\n  ", needle, "\n\nIn:\n\n", haystack]
+
+mainVHDL :: IO ()
+mainVHDL = do
+  [topDir] <- getArgs
+  content <- readFile (topDir </> show 'q </> "T3024_q_g_f.vhdl")
+
+  assertIn "entity f.f" content