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backend cleanup & more documentation
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‎clash-testbench/clash-testbench.cabal‎

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Original file line numberDiff line numberDiff line change
@@ -40,11 +40,9 @@ library
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Clash.Testbench.Output
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Clash.Testbench.Simulate
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Clash.Testbench.Generate
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other-modules:
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Clash.Testbench.Internal.ID
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Clash.Testbench.Internal.Signal
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Clash.Testbench.Internal.Monad
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Clash.Testbench.Internal.Auto
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build-depends:
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base,
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mtl,

‎clash-testbench/src/Clash/Testbench/Generate.hs‎

Lines changed: 105 additions & 80 deletions
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@@ -1,8 +1,16 @@
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{-|
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Copyright: (C) 2023 Google Inc.
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License: BSD2 (see the file LICENSE)
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Maintainer: QBayLogic B.V. <devops@qbaylogic.com>
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Use generators to create signal data.
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-}
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module Clash.Testbench.Generate where
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import Hedgehog
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import Hedgehog.Gen
5-
import Control.Monad.State.Lazy (liftIO, get)
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import Control.Monad.State.Lazy (liftIO)
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import Data.IORef (newIORef, readIORef, writeIORef)
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import Clash.Prelude (KnownDomain(..), BitPack(..), NFDataX)
@@ -12,92 +20,21 @@ import Clash.Testbench.Internal.ID
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import Clash.Testbench.Internal.Signal hiding (TBSignal, TBClock, TBReset, TBEnable)
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import Clash.Testbench.Internal.Monad
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matchIOGen ::
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(NFDataX i, BitPack i, KnownDomain dom, Eq o, Show o) =>
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TBSignal dom o -> Gen (i, o) -> TB (TBSignal dom i)
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matchIOGen expectedOutput gen = do
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ST{..} <- get
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vRef <- liftIO $ newIORef undefined
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simStepCache <- liftIO (readIORef simStepRef >>= newIORef)
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mind SomeSignal $ IOInput
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{ signalId = NoID
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, signalCurVal = do
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v <- readIORef simStepRef
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v' <- readIORef simStepCache
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if v == v'
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then readIORef vRef
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else do
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(i, o) <- sample gen
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signalExpect expectedOutput $ Expectation (v + 1, verify o)
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writeIORef vRef i
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writeIORef simStepCache v
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return i
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, signalPrint = Nothing
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}
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where
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verify x y
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| x == y = Nothing
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| otherwise = Just $ "Expected " <> show x <> " but the output is " <> show y
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matchIOGenN ::
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(NFDataX i, BitPack i, KnownDomain dom, Eq o, Show o) =>
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TBSignal dom o -> Gen [(i, o)] -> TB (TBSignal dom i)
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matchIOGenN expectedOutput gen = do
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ST{..} <- get
52-
53-
vRef <- liftIO $ newIORef []
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simStepCache <- liftIO (readIORef simStepRef >>= newIORef)
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mind SomeSignal $ IOInput
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{ signalId = NoID
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, signalCurVal = do
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v <- readIORef simStepRef
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v' <- readIORef simStepCache
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if v == v'
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then readIORef vRef >>= \case
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(i, _) : _ -> return i
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[] -> do
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(i, o) : xr <- sample gen
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writeIORef vRef ((i, o) : xr)
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return i
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else do
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writeIORef simStepCache v
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readIORef vRef >>= \case
72-
_ : (i, o) : xr -> do
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writeIORef vRef ((i, o) : xr)
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signalExpect expectedOutput $ Expectation (v, verify o)
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return i
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_ -> do
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(i, o) : xr <- sample gen
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writeIORef vRef ((i, o) : xr)
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signalExpect expectedOutput $ Expectation (v, verify o)
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return i
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, signalPrint = Nothing
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}
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where
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verify x y
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| x == y = Nothing
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| otherwise = Just $ "Expected '" <> show x <> "' but the output is '" <> show y <> "'"
87-
88-
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-- | Use a generator to create new signal data at every simulation
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-- step.
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generate ::
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forall dom a.
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(NFDataX a, BitPack a, KnownDomain dom) =>
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a -> Gen a -> TB (TBSignal dom a)
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generate def gen = do
93-
ST{..} <- get
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TBDomain{..} <- tbDomain @dom
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vRef <- liftIO $ newIORef def
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simStepCache <- liftIO (readIORef simStepRef >>= newIORef)
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mind SomeSignal IOInput
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{ signalId = NoID
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, signalCurVal = do
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, signalCurVal = const $ do
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v <- readIORef simStepRef
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v' <- readIORef simStepCache
10340

@@ -111,18 +48,23 @@ generate def gen = do
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, signalPrint = Nothing
11249
}
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-- | Extended version of 'generate', which allows to generate a finite
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-- sequence of data values, where one value is consumed per simulation
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-- step. The generator is repeatedly called after all steps of a
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-- generation has been consumed.
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generateN ::
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forall dom a.
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(NFDataX a, BitPack a, KnownDomain dom) =>
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a -> Gen [a] -> TB (TBSignal dom a)
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generateN def gen = do
118-
ST{..} <- get
60+
TBDomain{..} <- tbDomain @dom
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12062
vRef <- liftIO $ newIORef [def]
12163
simStepCache <- liftIO (readIORef simStepRef >>= newIORef)
12264

123-
mindSignal IOInput
65+
mind SomeSignal IOInput
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{ signalId = NoID
125-
, signalCurVal = do
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, signalCurVal = const $ do
12668
v <- readIORef simStepRef
12769
v' <- readIORef simStepCache
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@@ -147,3 +89,86 @@ generateN def gen = do
14789
, signalPrint = Nothing
14890
, ..
14991
}
92+
93+
-- | Use an input/output generator to describe an IO relation that
94+
-- specifies valid behavior. The satisfaction of this relation is
95+
-- automatically checked during simulation.
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matchIOGen ::
97+
forall dom i o.
98+
(NFDataX i, BitPack i, KnownDomain dom, Eq o, Show o) =>
99+
TBSignal dom o -> Gen (i, o) -> TB (TBSignal dom i)
100+
matchIOGen expectedOutput gen = do
101+
TBDomain{..} <- tbDomain @dom
102+
103+
vRef <- liftIO $ newIORef undefined
104+
simStepCache <- liftIO (readIORef simStepRef >>= newIORef)
105+
106+
mind SomeSignal $ IOInput
107+
{ signalId = NoID
108+
, signalCurVal = const $ do
109+
global <- readIORef simStepRef
110+
local <- readIORef simStepCache
111+
112+
if local == global
113+
then readIORef vRef
114+
else do
115+
(i, o) <- sample gen
116+
signalExpect expectedOutput $ Expectation (global + 1, verify o)
117+
118+
writeIORef vRef i
119+
writeIORef simStepCache global
120+
return i
121+
, signalPrint = Nothing
122+
}
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where
124+
verify x y
125+
| x == y = Nothing
126+
| otherwise = Just $ "Expected " <> show x <> " but the output is " <> show y
127+
128+
-- | Extended version of 'matchIOGen', which allows to specify valid
129+
-- IO behavior over a finite amount of simulation steps. The generator
130+
-- is repeatedly called after all steps of a generation have been
131+
-- verified.
132+
matchIOGenN ::
133+
forall dom i o.
134+
(NFDataX i, BitPack i, KnownDomain dom, Eq o, Show o, Show i) =>
135+
TBSignal dom o -> Gen [(i, o)] -> TB (TBSignal dom i)
136+
matchIOGenN expectedOutput gen = do
137+
TBDomain{..} <- tbDomain @dom
138+
139+
vRef <- liftIO $ newIORef []
140+
simStepCache <- liftIO (readIORef simStepRef >>= newIORef)
141+
142+
mind SomeSignal $ IOInput
143+
{ signalId = NoID
144+
, signalCurVal = const $ do
145+
global <- readIORef simStepRef
146+
local <- readIORef simStepCache
147+
148+
if local == global
149+
then readIORef vRef >>= \case
150+
(i, _) : _ -> return i
151+
[] -> do
152+
(i, o) : xr <- sample gen
153+
writeIORef vRef ((i, o) : xr)
154+
Prelude.print $ (i, o) : xr
155+
return i
156+
else do
157+
writeIORef simStepCache global
158+
readIORef vRef >>= \case
159+
_ : (i, o) : xr -> do
160+
writeIORef vRef ((i, o) : xr)
161+
signalExpect expectedOutput $ Expectation (global + 1, verify o)
162+
return i
163+
_ -> do
164+
(i, o) : xr <- sample gen
165+
Prelude.print $ (i, o) : xr
166+
writeIORef vRef ((i, o) : xr)
167+
signalExpect expectedOutput $ Expectation (global + 1, verify o)
168+
return i
169+
, signalPrint = Nothing
170+
}
171+
where
172+
verify x y
173+
| x == y = Nothing
174+
| otherwise = Just $ "Expected '" <> show x <> "' but the output is '" <> show y <> "'"

‎clash-testbench/src/Clash/Testbench/Input.hs‎

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,8 @@ Copyright: (C) 2023 Google Inc.
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License: BSD2 (see the file LICENSE)
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Maintainer: QBayLogic B.V. <devops@qbaylogic.com>
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6-
Input sources for simulating 'TB' defined testbenches.
6+
Input sources for simulating 'Clash.Testbench.Simulate.TB' defined
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test benches.
78
-}
89
module Clash.Testbench.Input
910
( fromList
@@ -21,31 +22,32 @@ import Clash.Testbench.Internal.Signal hiding (TBSignal)
2122
import Clash.Testbench.Internal.Monad
2223
import Clash.Testbench.Internal.ID
2324

24-
-- | Generates input that is taken from a finite or infinite list. If
25-
-- the list is finite and the number of simulation steps exceeds the
26-
-- length of the list, then the value of the first argument is
27-
-- used instead.
28-
fromList
29-
:: (KnownDomain dom, BitPack a, NFDataX a) => a -> [a] -> TB (TBSignal dom a)
25+
-- | Creates an input signal whose values are taken from a finite or
26+
-- infinite list. If the list is finite and the number of simulation
27+
-- steps exceeds the length of the list, then the value of the first
28+
-- argument is used repeatedly.
29+
fromList :: forall dom a.
30+
(KnownDomain dom, BitPack a, NFDataX a, Show a) =>
31+
a -> [a] -> TB (TBSignal dom a)
3032
fromList x xs = do
31-
ST{..} <- get
33+
TBDomain{..} <- tbDomain @dom
3234

3335
listRef <- liftIO $ newIORef $ x : xs
3436
simStepCache <- liftIO (readIORef simStepRef >>= newIORef)
3537

36-
mindSignal $ IOInput
38+
mind SomeSignal $ IOInput
3739
{ signalId = NoID
3840
, signalPrint = Nothing
39-
, signalCurVal = do
41+
, signalCurVal = const $ do
4042
(r, rs) <- fromMaybe (x, []) . uncons <$> readIORef listRef
41-
v <- readIORef simStepRef
42-
v' <- readIORef simStepCache
43+
global <- readIORef simStepRef
44+
local <- readIORef simStepCache
4345

44-
if v == v'
46+
if local == global
4547
then return r
4648
else do
4749
writeIORef listRef rs
48-
writeIORef simStepCache v
50+
writeIORef simStepCache global
4951
return $ case rs of
5052
[] -> x
5153
y:_ -> y

‎clash-testbench/src/Clash/Testbench/Internal/Auto.hs‎

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