Remove unused KnownDomains from tests/

Author: leonschoorl

tests/shouldfail/Verification/NonTemporal.hs

@@ -17,7 +17,7 @@ import           Clash.XException                (hwSeqX)
 
 assertCvResult
   :: forall n dom
-   . (Bounded n, Enum n, Eq n, NFDataX n, KnownDomain dom)
+   . (Bounded n, Enum n, Eq n, NFDataX n)
   => Clock dom -> Reset dom -> Enable dom
   -> n
   -> Signal dom AssertionResult

tests/shouldfail/Verification/Temporal.hs

@@ -17,7 +17,7 @@ import           Clash.XException                (hwSeqX)
 
 assertCvResult
   :: forall n dom
-   . (Bounded n, Enum n, Eq n, NFDataX n, KnownDomain dom)
+   . (Bounded n, Enum n, Eq n, NFDataX n)
   => Clock dom -> Reset dom -> Enable dom
   -> n
   -> Signal dom AssertionResult

tests/shouldwork/Cores/Xilinx/DcFifo/Lfsr.hs

@@ -23,7 +23,6 @@ orNothing True a = Just a
 orNothing False _ = Nothing
 
 lfsrF ::
-  KnownDomain dom =>
   Clock dom -> Reset dom -> Enable dom ->
   BitVector 16 ->
   Signal dom Bit
@@ -41,7 +40,6 @@ lfsrF clk rst ena seed = msb <$> r
 {-# CLASH_OPAQUE lfsrF #-}
 
 fifoSampler ::
-  KnownDomain dom =>
   Clock dom -> Reset dom -> Enable dom ->
   -- | Stall circuit? For this test case, this signal comes from 'lfsrF'
   Signal dom Stall ->
@@ -67,8 +65,7 @@ fifoSampler clk rst ena stalls inps =
 -- intermittently based on stall input.
 fifoDriver ::
   forall a dom depth .
-  ( KnownDomain dom
-  , NFDataX a
+  ( NFDataX a
   , Enum a
   , Num a
   ) =>
@@ -141,8 +138,7 @@ mkTestBench cFifo = done
 
 fifoVerifier ::
   forall a dom .
-  ( KnownDomain dom
-  , Ord a
+  ( Ord a
   , Num a
   , NFDataX a
   , ShowX a

tests/shouldwork/Cores/Xilinx/Floating.hs

@@ -54,8 +54,7 @@ floatVerifierShowsPrec _ (FloatVerifier x)
 
 playSampleRom
   :: forall n a dom
-   . ( KnownDomain dom
-     , KnownNat n
+   . ( KnownNat n
      , BitPack a
      , 1 <= n
      )

tests/shouldwork/Cores/Xilinx/XpmCdcHandshakeTypes.hs

@@ -20,42 +20,40 @@ data State = WaitForDeassert | WaitForAssert deriving (Generic, NFDataX)
 -- | Transfer 1, 2, 3, ... to destination domain
 srcFsm ::
   forall a src .
-  ( KnownDomain src
-  , Num a
+  ( Num a
   , NFDataX a
   ) =>
   Clock src ->
   Signal src Bool ->
   Signal src (a, Bool)
-srcFsm clk = mealy clk noReset enableGen go (0, WaitForDeassert)
+srcFsm clk = mealy clk rst enableGen go (0, WaitForDeassert)
  where
   go (n, WaitForDeassert) True  = ((n,     WaitForDeassert), (n,     False))
   go (n, WaitForDeassert) False = ((n + 1, WaitForAssert),   (n + 1, True))
   go (n, WaitForAssert)   False = ((n,     WaitForAssert),   (n,     True))
   go (n, WaitForAssert)   True  = ((n,     WaitForDeassert), (n,     False))
+  rst = provideKnownDomainFrom clk noReset
 {-# NOINLINE srcFsm #-}
 
 -- | Receives data from source domain
 dstFsm ::
   forall a dst .
-  KnownDomain dst =>
   Clock dst ->
   Signal dst (Bool, a) ->
   Signal dst (Bool, Maybe a)
-dstFsm clk = mealy clk noReset enableGen go WaitForAssert
+dstFsm clk = mealy clk rst enableGen go WaitForAssert
  where
   go WaitForAssert   (False, _) = (WaitForAssert,   (False, Nothing))
   go WaitForAssert   (True,  n) = (WaitForDeassert, (True,  Just n))
   go WaitForDeassert (True,  _) = (WaitForDeassert, (True,  Nothing))
   go WaitForDeassert (False, _) = (WaitForAssert,   (False, Nothing))
+  rst = provideKnownDomainFrom clk noReset
 {-# NOINLINE dstFsm #-}
 
 -- | Composition of 'srcFsm' and 'dstFsm'
 top ::
   forall a srcStages dstStages src dst .
-  ( KnownDomain src
-  , KnownDomain dst
-  , Num a
+  ( Num a
   , NFDataX a
   , BitPack a
   , 1 <= BitSize a, BitSize a <= 1024

tests/shouldwork/Shadowing/T990.hs

@@ -25,11 +25,11 @@ instance Arrow (SignalA dom) where
     (SA f) &&& (SA g) = SA $ f &&& g >>> bundle
 
 
-alwaysEnable :: (WithSingleDomain dom a, KnownDomain dom) => (HiddenEnable dom => a) -> a
+alwaysEnable :: (WithSingleDomain dom a) => (HiddenEnable dom => a) -> a
 alwaysEnable a = exposeEnable a enableGen
 
 alwaysDelayA ::
-    (KnownDomain dom, HiddenClock dom, NFDataX a) =>
+    (HiddenClock dom, NFDataX a) =>
     a -> SignalA dom a a
 alwaysDelayA a = SA $ alwaysEnable $ delay a
 

tests/shouldwork/Signal/Compression.hs

@@ -57,7 +57,6 @@ expectedOutput clkB rstB = outputVerifierR clkB rstB 1 $
 outputVerifierR
   :: forall l a testDom circuitDom
    . ( KnownNat l
-     , KnownDomain testDom
      , KnownDomain circuitDom
      , Eq a
      , ShowX a )
@@ -76,7 +75,7 @@ outputVerifierR
   -- ^ True if all samples are verified
 outputVerifierR clk rst iR samples i0 =
     let t1    = snatToNum (clockPeriod @circuitDom)
-        t2    = snatToNum (clockPeriod @testDom)
+        t2    = provideKnownDomainFrom clk $ snatToNum (clockPeriod @testDom)
         i1    = veryUnsafeSynchronizer (Left t1) (Left t2) i0
         en    = toEnable (pure True)
         (s,o) = unbundle (genT iR <$> register clk rst en 0 s <*> unsafeFromReset rst)

tests/shouldwork/Signal/DualBlockRamDefinitions.hs

@@ -12,7 +12,7 @@ createDomain vSystem{vName="A", vPeriod=hzToPeriod 20e6} -- fast
 createDomain vSystem{vName="B", vPeriod=hzToPeriod 10e6} -- slow
 createDomain vSystem{vName="C", vPeriod=hzToPeriod 7e6} -- slower
 
-tdpRam :: (KnownDomain domA, KnownDomain domB) => TdpRam domA domB
+tdpRam :: TdpRam domA domB
 tdpRam = trueDualPortBlockRam
 
 {- Testvectors

tests/shouldwork/Signal/DynamicClocks.hs

@@ -16,7 +16,7 @@ import Clash.Explicit.Testbench
 createDomain vSystem{vName="Static", vPeriod=1000}
 createDomain vSystem{vName="Dynamic", vPeriod=1000}
 
-counter :: KnownDomain dom => Clock dom -> Reset dom -> Enable dom -> Signal dom Int
+counter :: Clock dom -> Reset dom -> Enable dom -> Signal dom Int
 counter clk rst ena = let counter0 = register clk rst ena 0 (counter0 + 1) in counter0
 -- See: https://github.com/clash-lang/clash-compiler/pull/2511
 {-# CLASH_OPAQUE counter #-}

tests/shouldwork/Signal/Ram/RWMulti.hs

@@ -29,9 +29,7 @@ createDomain vSystem{vName="P50", vPeriod=50000}
 
 ram
   :: forall wdom rdom
-   . ( KnownDomain rdom
-     , KnownDomain wdom)
-  => Clock wdom
+   . Clock wdom
   -> Clock rdom
   -> Signal wdom (Unsigned 4)
   -> Signal rdom (Unsigned 4)
@@ -42,9 +40,7 @@ ram wClk rClk wrD = asyncRamPow2 wClk rClk enableGen rd wrM
 
 tbOutput
   :: forall wdom rdom
-   . ( KnownDomain rdom
-     , KnownDomain wdom)
-  => (  Clock wdom
+   . (  Clock wdom
       -> Clock rdom
       -> Signal wdom (Unsigned 4)
       -> Signal rdom (Unsigned 4))
@@ -54,13 +50,14 @@ tbOutput
 tbOutput top wClk rClk = output
  where
   wrD = delay wClk enableGen 0 $ wrD + 1
-  output = ignoreFor rClk noReset enableGen d1 0 $ top wClk rClk wrD
+  output = ignoreFor rClk rst enableGen d1 0 $ top wClk rClk wrD
+  rst = provideKnownDomainFrom rClk noReset
 {-# INLINE tbOutput #-}
 
 tb
   :: forall wdom rdom n
-   . ( KnownDomain rdom
-     , KnownDomain wdom
+   . ( KnownDomain wdom
+     , KnownDomain rdom
      , KnownNat n
      , 1 <= n)
   => (  Clock wdom