dpll: zl3073x: Add support to get/set esync on pins

jira KERNEL-318
Rebuild_History Non-Buildable kernel-6.12.0-124.20.1.el10_1
commit-author Ivan Vecera <ivecera@redhat.com>
commit 634ca2c

Add support to get/set embedded sync for both input and output pins.
The DPLL is able to lock on input reference when the embedded sync
frequency is 1 PPS and pulse width 25%. The esync on outputs are more
versatille and theoretically supports any esync frequency that divides
current output frequency but for now support the same that supported on
input pins (1 PPS & 25% pulse).

Note that for the output pins the esync divisor shares the same register
used for N-divided signal formats. Due to this the esync cannot be
enabled on outputs configured with one of the N-divided signal formats.

	Reviewed-by: Jiri Pirko <jiri@nvidia.com>
	Tested-by: Prathosh Satish <prathosh.satish@microchip.com>
Co-developed-by: Prathosh Satish <Prathosh.Satish@microchip.com>
	Signed-off-by: Prathosh Satish <Prathosh.Satish@microchip.com>
	Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Link: https://patch.msgid.link/20250715144633.149156-2-ivecera@redhat.com
	Signed-off-by: Paolo Abeni <pabeni@redhat.com>

(cherry picked from commit 634ca2c)
	Signed-off-by: Jonathan Maple <jmaple@ciq.com>

Author: PlaidCat