hal: Fix for Zephyr's recent upgrade to CMSIS 6

A handful of source files were still using an old version of CMSIS and would no longer build after the recent upgrade to CMSIS 6 introduced in zephyrproject-rtos/zephyr#90063

Signed-off-by: Egill Sigurdur <egill@egill.xyz>

Author: egilll

gd32a50x/standard_peripheral/source/gd32a50x_misc.c

@@ -84,7 +84,7 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
         temp_pre=2U;
         temp_sub=0x2U;
     }
-    /* get the temp_priority to fill the NVIC->IP register */
+    /* get the temp_priority to fill the NVIC->IPR register */
     temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
     temp_priority |= (uint32_t)nvic_irq_sub_priority &((uint32_t)0x0FU >> (0x4U - temp_sub));
     temp_priority = temp_priority << 0x04U;

gd32e10x/standard_peripheral/source/gd32e10x_misc.c

@@ -97,11 +97,11 @@ void nvic_irq_enable(uint8_t nvic_irq,
         break;
     }
 
-    /* get the temp_priority to fill the NVIC->IP register */
+    /* get the temp_priority to fill the NVIC->IPR register */
     temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
     temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
     temp_priority = temp_priority << 0x04U;
-    NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
+    NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
 
     /* enable the selected IRQ */
     NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);

gd32e50x/standard_peripheral/source/gd32e50x_misc.c

@@ -87,7 +87,7 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
         temp_pre=2U;
         temp_sub=0x2U;
     }
-    /* get the temp_priority to fill the NVIC->IP register */
+    /* get the temp_priority to fill the NVIC->IPR register */
     temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
     temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
     temp_priority = temp_priority << 0x04U;

gd32f3x0/standard_peripheral/source/gd32f3x0_misc.c

@@ -97,11 +97,11 @@ void nvic_irq_enable(uint8_t nvic_irq,
         break;
     }
 
-    /* get the temp_priority to fill the NVIC->IP register */
+    /* get the temp_priority to fill the NVIC->IPR register */
     temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
     temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
     temp_priority = temp_priority << 0x04U;
-    NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
+    NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
 
     /* enable the selected IRQ */
     NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);

gd32f403/standard_peripheral/source/gd32f403_misc.c

@@ -86,11 +86,11 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
         temp_pre=2U;
         temp_sub=0x2U;
     }
-    /* get the temp_priority to fill the NVIC->IP register */
+    /* get the temp_priority to fill the NVIC->IPR register */
     temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
     temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
     temp_priority = temp_priority << 0x04U;
-    NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
+    NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
     /* enable the selected IRQ */
     NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
 }

gd32f4xx/standard_peripheral/source/gd32f4xx_misc.c

@@ -86,11 +86,11 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
         temp_pre = 2U;
         temp_sub = 0x2U;
     }
-    /* get the temp_priority to fill the NVIC->IP register */
+    /* get the temp_priority to fill the NVIC->IPR register */
     temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
     temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub));
     temp_priority = temp_priority << 0x04U;
-    NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
+    NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
     /* enable the selected IRQ */
     NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
 }