FAST Framework for OpenTSN

[mngr0]

Good Morning,

I am a student of the University of Bologna, currently enrolled in the Computer science master degree, and I am currently working to my master thesis.

We would like to replicate the test-bench you did in this paper ( https://link.springer.com/article/10.1007/s42045-020-00029-8 ),

How can we obtain the FAST framework and the hardware?
We would like to use a NetLeap Board, which has a different Zynq, is it possible to port the project?

Kind Regards,

Marco Negrini

[line-wind]

How can we obtain the FAST framework and the hardware?

you can find the source code of FAST framework here. but we haven't uploaded the source code of hardware part for now. As for the hardware, unforunfortunately , it is not available to researchers abroad at present. But if you need, we will provide it on Amazon.

is it possible to port the project?

Theoritically yes. you may meet some platform-related problems. But we are happy to provide helps.

[Winters123]

How can we obtain the FAST framework and the hardware?

I'm not sure why you are interested in FAST framework for implementing OpenTSN 3.0. Because OpenTSN is a sort of independent opensource project. Unless you want to change some of the fundamental designs in OpenTSN, you don't necessarily have to work with FAST. Could you give me some hints about what you are planning to do? maybe we can give you some suggestions.

Cheers,

[GMunari]

How can we obtain the FAST framework and the hardware?

you can find the source code of FAST framework here. but we haven't uploaded the source code of hardware part for now. As for the hardware, unforunfortunately , it is not available to researchers abroad at present. But if you need, we will provide it on Amazon.

is it possible to port the project?

Theoritically yes. you may meet some platform-related problems. But we are happy to provide helps.

Dear Sir,
I am the reference Senior Researcher for Marco Negrini's above mentioned project.

With Marco we are interested in testing and implementing your core in one or more boards that we already own. We have and Xilinx Zynq development boards and Intel Cyclone V SoC ones. Our project concerns only scientific research, no commercial purposes.

For this purposes we are kindly asking you:

• Firstly, How is it possible to port the project if the FAST_OS sources are not provided? Is there a manner to overcome this issue, for example configurating it in relation to the referenced board (i.e. number of ports, connections, etc.)
• Secondly, Is there a one port endpoint core version? Maybe this one would be easier to port to other boards.
• Thirdly, if porting to other boards was not so easy to do, as we have already faced some issues trying to port to other Zynq-based boards, could you provided us all details for purchasing the OpenBoxS4 (i.e. prices, delivery times, payment process and method and so on).

We look forward to hearing from you soon.

Yours faithfully,

Guido Munari
Senior Reasercher in FPGA/HW/SW Engineering

[Winters123]

Firstly, How is it possible to port the project if the FAST_OS sources are not provided? Is there a manner to overcome this issue, for example configurating it in relation to the referenced board (i.e. number of ports, connections, etc.)

Like I said, OpenTSN3.0 is an independent project. You can use only the code in this project to implement the TSN switch or NIC. There is no need to have FAST_OS if implementing OpenTSN is all you need.

Currently we provide two versions (here) in OpenTSN3.0 (NIC & Switch). For the NIC version, there are two ports: One port connecting the NIC to the TSN network side while the other port connecting to the host (we haven't implemented DMA&PCIe yet); For the Switch version, OpenTSN has 4 ports which have equal functions.

The demo now is implemented using Intel Arria10 (10AX048H2F34E2SG) evaluation board. And you can synthesis & implement the code using Makefile with Quartus.

But if you don't have the specific FPGAs/boards, things will get a bit of tricky as you need to:

1. configure the pins by hand;
2. set up constraints (porbobly write your own xdc files if you are using Xilinx boards)
3. add the source code & ip cores into the proj;

On the other hand, we are migrating OpenTSN 3.0 onto OpenBoxS4 (which has a Zynq-7020 SoC), and preparing to push OpenBoxS4 conf onto Amazon so that you can download all the configurations. We'll let you know once its done. But one thing worth noting is that you need to have at least two 1G ports to get OpenTSN running.

OpenBoxS4 is currently only avaluble in China. And we honestly don't have any idea how it is possible to ship it to Italy. But we can ask if you want.

Cheers,

[mngr0]

Thanks to your last commit ( 11e1aa5 ) we are now able to synthesize the project.

But if you don't have the specific FPGAs/boards

We have some board on which we can port OpenTSN. We were confused by the different version of OpenTSN that are available on github. But now we can see that there is no need for FastOS nor the OpenBOX.

TSN is made of many different 802.1Qxx standards, which of them do you implement in OpenTSN?

Kind Regards,

Marco Negrini

[line-wind]

TSN is made of many different 802.1Qxx standards, which of them do you implement in OpenTSN?

At present, OpenTSN 3.0 supports 802.1AS, 802.1Qbv, 802.1Qcc, 802.1Qch. We will add 802.1Qci, Qbu, 802.1 CB in soon.

[GMunari]

TSN is made of many different 802.1Qxx standards, which of them do you implement in OpenTSN?

At present, OpenTSN 3.0 supports 802.1AS, 802.1Qbv, 802.1Qcc, 802.1Qch. We will add 802.1Qci, Qbu, 802.1 CB in soon.

As per your reply, it seems that OpenTSN 3.0 currently does not support 802.1Qav for forwarding and queue management.

Therefore, how queues are currently managed? Have you implemented another solution for avoiding queues starvation?

Best regards,

Guido Munari

[line-wind]

As per your reply, it seems that OpenTSN 3.0 currently does not support 802.1Qav for forwarding and queue management.

We implement Qbv or Qch for forwarding and queue manegement, and implement CBS(credit-based shaper) in NIC software to limit RC(rate-control traffic) rate.

how queues are currently managed?

OpenTSN switch supports 8 queues. Three queues can be configurated into ST(scheduled traffic) queues. The other 5 queues are used to store RC traffic, BE (best effort) traffic, PTP traffic etc. TAS(time-aware shaper) mechanism described in Qbv is used to shpaer ST trassfic. CBS described in Qav is used to limit RC traffic rate. After the shpers, strict priority scheduling mechanism is used to schedule all the queues.