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option matrix
| Configuration Category | ARChitect config name | Compiler Driver (MCC) | Corresponding gcc flags | Debugger Driver (mdb) | 600ARC | 700 | ARCEM | ARCv2HS | Notes | |
|---|---|---|---|---|---|---|---|---|---|---|
| Processor Family |
| |ARC600 |-a6 (arc600) |-mcpu=arc600 |-a6 (arc600) | X | | | |
| |ARC700 |-a7 (arc700) |-mcpu=arc700 |-a7 (arc700) | | X | | |
| |ARCv2EM |-av2em (-arcv2em) | -mcpu=arcem | -av2em (-arcv2em) | | | X | |
| |ARCv2HS |-av2hs (-arcv2hs) | -mcpu=archs | -av2hs (-arcv2hs) | | | | X |
ARC 600 Core Versions | | | | | | | | | | | |Version1 |-core1 | N.A. | -core1 |X | | | | Initial version | |Version 2 |-core2 | N.A. | -core2 |X | | | | Zeroed BCR Region 0xc0 | |Version 3 |-core3 | N.A. | -core3 |X | | | | LD/ST Queue changes | |Version 4 |-core4 | N.A. | -core4 |X | | | | SYNC instruction | |Version 5 |-core5 | N.A. | -core5 |X | | | | ARC600_BUILD BCR | |Version 6 |-core6 | N.A. | -core6 |X | | | | Misaligned LD/ST traps. ARC 700 Core Versions | | | | | | | | | | | |Version 1 |-core1 | N.A. | -core1 | |X | | | Initial version | |Version 2 |-core2 | N.A. | -core2 | |X | | | Zeroed BCR Region 0xc0 | |Version 3 |-core3 | N.A. | -core3 | |X | | | MXP Debug Architecture | |Version 4 |-core4 | N.A. | -core4 | |X | | | SWAPE, LLOCK,SCOND instr ARCv2EM Core Versions | | | | | | | | | | | |Version 0 |-core0 | Not supported | -core0 | | | X | | EM 1.0 (Initial version) | |Version 1 |-core1 | N.A. | -core1 | | | X | | EM 1.1 (Default version) ARCv2HS Core Versions | | | | | | | | | | | |Version 0 |-core0 | Not supported | -core0 | | | | X | HS 1.0 (Initial version) | |Version 1 |-core1 | N.A. | | | | | | Shift ISA Extension |shift_option | | | | | | | | | | |Option 1 |-Xsa (-Xshift_assist) | N.A. | -Xsa (-Xshift_assist) | | | | | | |Option 2 |-Xbs (-Xbarrel_shifter)| N.A. | -Xbs (-Xbarrel_shifter) | | | | | | |Option 3 |-Xsa -Xbs | -mbarrel-shifter | -Xsa -Xbs |X |X | X |X |Default for ARC600, ARC700, ARC HS and ARC EM Code Density Extension |code_density_option | |-Xcd (-Xcode_density ) | -mcode-density | -Xcd (-Xcode_density ) | | | X | X |Default for HS, EM Bitscan ISA Extension |bitscan_option | |-Xnorm | -mnorm | -Xnorm |X |X | X | X |Default for HS SWAP ISA Extension |swap_option | |-Xswap | -mswap | -Xswap |X |X | X | X |Default for HS DIV_REM ISA option |div_rem_option | |-Xdiv_rem | -mdiv-rem | -Xdiv_rem | | | X | X | radix2 is default for EM and HS Multiply ISA Option |mpy_option | | | -mmpy-option={0-9} | | | | X | | |wlh1 |Option 1 |-Xmpy16 | -mmpy-option=1/-mmpy16 | -Xmpy16 |X | | X | | |wlh2 |Option 2 |-Xmpy | -mmpy-option=2/-mmpy | -Xmpy | |X | X | X | -Xmpy16 is implied by -X |wlh1, wlh2, wlh3, wlh|MPY cycles |-Xmpy_cycles=1,2,3,4,5 | -mmpy-option={3-6} | -Xmpy_cycles=1,2,3,4,5 | |X | X | | -Xmpy is implied if spec |wlh7 |Option 7 |-Xmac | -mmpy-option=7 | | | | | X | -Xmac implies -Xmpy and |wlh8 |Option 8 |-Xmacd | -mmpy-option=8 | | | | | X | -Xmacd implies -Xmac |wlh9 |Option 9 |-Xqmpyh | -mmpy-option=9 | | | | | X | -Xqmpyh implies -Xmacd | |A600 MPY |-Xmult32 | | -Xmult32 |X | | | | | |A600 MPY cycles |-Xmult32_cycles=N | -mulcost={1,2,3,4,5} | -Xmult32_cycles=N |X | | X | | -Xmult32 is implied if s 64-bit Load and Store |ll64 | |-Xll64 | -mll64 | -Xll64 | | | | X | LDD/STD Unaligned Memory access| | |-XUnaligned | N.A. | -XUnaligned | | | | X | Unaligned memory accesse Atomic Option |atomic_option | |-Xatomic | -matomic | -Xatomic | | | | |Default Extended Arithmetic Ins| | |-Xea | -mEA | -Xea |X |X | | | Xlib MetaWare Opt | | | | | | | | | | | |ARC600 |-Xlib | N.A | -Xlib |X | | | | Expansion: -Xmult32 -Xno | |ARC601 |-Xlib | N.A | -Xlib |X | | | | Expansion: -Xbs -Xmult32 | |ARC700 |-Xlib | N.A. | -Xlib | |X | | | Expansion: -Xmpy (-Xnorm | |ARCv2EM |-Xlib | N.A. | -Xlib | | | X | | Expansion: -Xbs -Xmpy -X | |ARCv2HS |-Xlib | N.A. | -Xlib | | | | X | Expansion: -Xmpy -Xll64 Endianness | | | | | | | | | | | |Big |-HB | -mbig-endian | N/A |X |X | X | X | MDB reads endianess from | |Little |-HL | -mlittle-endian | N/A |X |X | X | X | PC Width |pc_size | |-Hpc_width=16,20,24,28,| N.A. | -pc_width=16,20,24,28,32|X |X | X | | for HS, fixed pc_width=3 Loop Counter Width |lpc_size | |-Hlpc_width=0,8,12,16,2| N.A. | -lpc_width=8,12,16,20,24|X |X | X | | for HS, fixed lpc_width= Address size |addr_size | |N/A | N.A. | -addr_size=16,20,24,32 | | | X | | for HS, fixed addr_size= Number of Interrupts |number_of_interrupts | |N/A | N.A. | -interrupts=1..240 |X |X | X | X | For 600,700 only 8,16,24 Interrupt Vector Base |invbase_preset | |N/A | N.A. | -interrupt_base=addr |X |X | X | X | fast Interrupts |irq_option | |N/A | N.A. | -firq | | | X | X | External Interrupts |external_interrupts | |N/A | N.A. | -ext_interrupts=1..240 | | | X | X | Number of priority leve|number_of_levels | |N/A | N.A. | -interrupt_priorities=1.|.16 | | X | X | Number of Registers |ngf_num_regs | | | | | | | X | | | | 16| |N.A. | N/A |X |X | X | X | MDB reads -rf16 info fro | | 32|Default | Default | N/A |X |X | X | X | MCC assumes 32 registers Number of Register Bank|ngf_num_banks | | | N.A. | -rgf_num_banks=1,2,3,4 | | | X | X | EM - 2 register banks, H Number of banked regist|ngf_banked_regs | |-Hrgf_banked_regs=N | N.A. | -rgf_banked_regs=4,8,16,|32 | | X | | For HS it is 32 (or 16 w Actionpoints |num_actionpoints | | | | | | | | | Timer 0 | | |-Xtimer0 | N.A. | -Xtimer0 |X |X | X | X | Timer 1 | | |-Xtimer1 | N.A. | -Xtimer1 |X |X | X | X | DCCM Size |dccm_size | |N/A | N.A. | -dccm_size=size |X |X | X | X | User linker map file to DCCM Base Address |dccm_base | |N/A | N.A. | -dccm_base=addr |X |X | X | X | ICCM Size |iccm0_size | |N/A | N.A. | -iccm_size=size, -iccm0_|X |X | X | X | |iccm1_size | | | | -iccm1_size=size | | | | | ICCM Base Address |iccm0_base | |N/A | N.A. | -iccm_base=addr, -iccm0_|X |X | X | X | |iccm1_base | | | | -iccm1_base=addr | | | | | Data Cache | | |N/A | | -dcache=csz,lsz,w,attrib|X |X | X | X | |dc_size | | |-param l1-cache-size | csz is 512 to 32k | | | | | csz=cache size |dc_bsize | | |-param l1-cache-line-size | elsz is 8,16,32,64,128,2|56 | | | | lsz=line size |c_ways | | | N.A. | w is 1,2,4 | | | | | w=ways | | | | | attrib is a or o | | | | | attrib is optional,rando Instruction Cache | | |N/A | N.A. | -icache=csz,lsz,w,attrib|X |X | X | X | Same format as -dcache |ic_size | | | N.A. | csz is 512 to 32k | | | | | csz=cache size |ic_bsize | | | N.A. | lsz is 8,16,32,64,128,25|6 | | | | lsz=line size |ic_ways | | | N.A. | w is 1,2,4 | | | | | w=ways | | | | | attrib is a or o | | | | | attrib is optional,rando Instruction Fetch Queue|ifqueue_size | | | | | | | X | X | |ifqueue_burst_size | | | | | | | X | X | DSP Dual 16x16 MAC | | |-Xxmac_d16 | | -Xxmac_d16 |X |X | | | Adds instructions MULDW, DSP 24x24 MAC | | |-Xxmac_24 | | -Xxmac_24 |X |X | | | Adds instructions MULT, DSP 32x16 MPY | | |-Xmul32x16 | -mmul32x16 | -Xmul32x16 |X |X | | | Adds Instructions MULULW DSP Dual Floating Point|32x16 MUL/MAC | |-Xdmulpf | | -Xdmulpf |X | | | | Adds instructions DMULPF DSP XY memory | | |-Xxy | -mxy | -Xxy |X |X | | | | |XY size |-Xxysize=size | N.A. | -Xxysize=size |X |X | | | | |XY banks |-Xxybanks=banks | N.A. | -Xxybanks=banks |X |X | | | | |XY base X |-Xxylsbasex=addr | N.A. | -Xxylsbasex=addr |X |X | | | | |XY base Y |-Xxylsbasey=addr | N.A. | -Xxylsbasey=addr |X |X | | | FPX (floating pt.) | | | | | | | | | | | |Single |-Xspfp | -mspfp | -Xspfp |X |X | X | | Also -Xspfp_compact, -Xs | |Double |-Xdpfp | -mdpfp | -Xdpfp |X |X | X | | Also -Xdpfp_compact, -Xd eFPX (new fp unit) | | | | | | | | | X | No support in compiler/d SIMD Unit | | |-Xsimd | -msimd | -Xsimd | |X | | | Time Stamp Counter | | |-Xrtsc | N.A. | -Xrtsc | |X | | | RTSC instruction Stack Boundary Check | | |N/A | N.A. | -Xstack_check | |X | | | Memory Management Unit | | | | | | | | | | | |Version 2 |N/A | N.A. | -mmu | |X | | | | |Version3 |N/A | N.A. | -mmuv3 | |X | | | Provides more configurab | | | | | -prop=mmu_pagesize=NNN | |X | | | Set the page size in byt | | | | | -prop=jtlb_ways=WWW | |X | | | change the number of way | | | | | -prop=mmu_osm=N | |X | | | Set the OSM bit, N=1 or FPU (IEEE fp) | | | | | | | | | | |Single | | | -mfpu=fpus | | | | X | X | |Single with DIV/SQRT | | | -mfpu=fpus_dis | | | | X | X | |Single with fused ops | | | -mfpu=fpus_fma | | | | X | X | |Single all extensions | | | -mfpu=fpus_all | | | | X | X | |Double | | | -mfpu=fpud | | | | | X | |Double with DIV/SQRT | | | -mfpu=fpud_dis | | | | | X | |Double with fused ops | | | -mfpu=fpud_fma | | | | | X | |Double all extensions | | | -mfpu=fpud_all | | | | | X | |Double assist insns | | | -mfpu=fpuda | | | | X | |