diff --git a/vendor/ch32v307/core/core_riscv.c b/vendor/ch32v307/core/core_riscv.c
index 2086aab..f3dc594 100644
--- a/vendor/ch32v307/core/core_riscv.c
+++ b/vendor/ch32v307/core/core_riscv.c
@@ -174,35 +174,6 @@ void __set_MISA(uint32_t value)
   __ASM volatile ("csrw misa, %0" : : "r" (value) );
 }
 
-/*********************************************************************
- * @fn      __get_MIE
- *
- * @brief   Return the Machine Interrupt Enable Register
- *
- * @return  mie value
- */
-uint32_t __get_MIE(void)
-{
-  uint32_t result;
-
-  __ASM volatile ( "csrr %0," "mie" : "=r" (result) );
-  return (result);
-}
-
-/*********************************************************************
- * @fn      __set_MISA
- *
- * @brief   Set the Machine ISA Register
- *
- * @param   value  - set mie value
- *
- * @return  none
- */
-void __set_MIE(uint32_t value)
-{
-  __ASM volatile ("csrw mie, %0" : : "r" (value) );
-}
-
 /*********************************************************************
  * @fn      __get_MTVEC
  *
@@ -233,7 +204,7 @@ void __set_MTVEC(uint32_t value)
 }
 
 /*********************************************************************
- * @fn      __get_MTVEC
+ * @fn      __get_MSCRATCH
  *
  * @brief   Return the Machine Seratch Register
  *
@@ -248,7 +219,7 @@ uint32_t __get_MSCRATCH(void)
 }
 
 /*********************************************************************
- * @fn      __set_MTVEC
+ * @fn      __set_MSCRATCH
  *
  * @brief   Set the Machine Seratch Register
  *
@@ -342,141 +313,6 @@ void __set_MTVAL(uint32_t value)
   __ASM volatile ("csrw mtval, %0" : : "r" (value) );
 }
 
-/*********************************************************************
- * @fn      __get_MIP
- *
- * @brief   Return the Machine Interrupt Pending Register
- *
- * @return  mip value
- */
-uint32_t __get_MIP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ( "csrr %0," "mip" : "=r" (result) );
-  return (result);
-}
-
-/*********************************************************************
- * @fn      __set_MIP
- *
- * @brief   Set the Machine Interrupt Pending Register
- *
- * @return  mip value
- */
-void __set_MIP(uint32_t value)
-{
-  __ASM volatile ("csrw mip, %0" : : "r" (value) );
-}
-
-/*********************************************************************
- * @fn      __get_MCYCLE
- *
- * @brief   Return Lower 32 bits of Cycle counter
- *
- * @return  mcycle value
- */
-uint32_t __get_MCYCLE(void)
-{
-  uint32_t result;
-
-  __ASM volatile ( "csrr %0," "mcycle" : "=r" (result) );
-  return (result);
-}
-
-/*********************************************************************
- * @fn      __set_MCYCLE
- *
- * @brief   Set Lower 32 bits of Cycle counter
- *
- * @return  mcycle value
- */
-void __set_MCYCLE(uint32_t value)
-{
-  __ASM volatile ("csrw mcycle, %0" : : "r" (value) );
-}
-
-/*********************************************************************
- * @fn      __get_MCYCLEH
- *
- * @brief   Return Upper 32 bits of Cycle counter
- *
- * @return  mcycleh value
- */
-uint32_t __get_MCYCLEH(void)
-{
-  uint32_t result;
-
-  __ASM volatile ( "csrr %0," "mcycleh" : "=r" (result) );
-  return (result);
-}
-
-/*********************************************************************
- * @fn      __set_MCYCLEH
- *
- * @brief   Set Upper 32 bits of Cycle counter
- *
- * @return  mcycleh value
- */
-void __set_MCYCLEH(uint32_t value)
-{
-  __ASM volatile ("csrw mcycleh, %0" : : "r" (value) );
-}
-
-/*********************************************************************
- * @fn      __get_MINSTRET
- *
- * @brief   Return Lower 32 bits of Instructions-retired counter
- *
- * @return  mcause value
- */
-uint32_t __get_MINSTRET(void)
-{
-  uint32_t result;
-
-  __ASM volatile ( "csrr %0," "minstret" : "=r" (result) );
-  return (result);
-}
-
-/*********************************************************************
- * @fn      __set_MINSTRET
- *
- * @brief   Set Lower 32 bits of Instructions-retired counter
- *
- * @return  minstret value
- */
-void __set_MINSTRET(uint32_t value)
-{
-  __ASM volatile ("csrw minstret, %0" : : "r" (value) );
-}
-
-/*********************************************************************
- * @fn      __get_MINSTRETH
- *
- * @brief   Return Upper 32 bits of Instructions-retired counter
- *
- * @return  minstreth value
- */
-uint32_t __get_MINSTRETH(void)
-{
-  uint32_t result;
-
-  __ASM volatile ( "csrr %0," "minstreth" : "=r" (result) );
-  return (result);
-}
-
-/*********************************************************************
- * @fn      __set_MINSTRETH
- *
- * @brief   Set Upper 32 bits of Instructions-retired counter
- *
- * @return  minstreth value
- */
-void __set_MINSTRETH(uint32_t value)
-{
-  __ASM volatile ("csrw minstreth, %0" : : "r" (value) );
-}
-
 /*********************************************************************
  * @fn      __get_MVENDORID
  *
@@ -548,7 +384,7 @@ uint32_t __get_SP(void)
 {
   uint32_t result;
 
-  asm volatile ( "mv %0," "sp" : "=r"(result) : );
+  __ASM volatile ( "mv %0," "sp" : "=r"(result) : );
   return (result);
 }
 
diff --git a/vendor/ch32v307/core/core_riscv.h b/vendor/ch32v307/core/core_riscv.h
index 6efa45d..71da503 100644
--- a/vendor/ch32v307/core/core_riscv.h
+++ b/vendor/ch32v307/core/core_riscv.h
@@ -10,6 +10,10 @@
 #ifndef __CORE_RISCV_H__
 #define __CORE_RISCV_H__
 
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
 /* IO definitions */
 #ifdef __cplusplus
   #define     __I     volatile                /* defines 'read only' permissions */
@@ -60,7 +64,7 @@ typedef int32_t  s32;
 typedef int16_t s16;
 typedef int8_t  s8;
 
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
 
 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
 
@@ -76,7 +80,7 @@ typedef struct{
   __IO uint32_t RESERVED;
   __IO uint32_t CFGR;
   __I  uint32_t GISR;
-  uint8_t VTFIDR[4];
+  __IO uint8_t VTFIDR[4];
   uint8_t RESERVED0[12];
   __IO uint32_t VTFADDR[4];
   uint8_t RESERVED1[0x90];
@@ -346,8 +350,6 @@ extern uint32_t __get_MSTATUS(void);
 extern void __set_MSTATUS(uint32_t value);
 extern uint32_t __get_MISA(void);
 extern void __set_MISA(uint32_t value);
-extern uint32_t __get_MIE(void);
-extern void __set_MIE(uint32_t value);
 extern uint32_t __get_MTVEC(void);
 extern void __set_MTVEC(uint32_t value);
 extern uint32_t __get_MSCRATCH(void);
@@ -358,22 +360,15 @@ extern uint32_t __get_MCAUSE(void);
 extern void __set_MCAUSE(uint32_t value);
 extern uint32_t __get_MTVAL(void);
 extern void __set_MTVAL(uint32_t value);
-extern uint32_t __get_MIP(void);
-extern void __set_MIP(uint32_t value);
-extern uint32_t __get_MCYCLE(void);
-extern void __set_MCYCLE(uint32_t value);
-extern uint32_t __get_MCYCLEH(void);
-extern void __set_MCYCLEH(uint32_t value);
-extern uint32_t __get_MINSTRET(void);
-extern void __set_MINSTRET(uint32_t value);
-extern uint32_t __get_MINSTRETH(void);
-extern void __set_MINSTRETH(uint32_t value);
 extern uint32_t __get_MVENDORID(void);
 extern uint32_t __get_MARCHID(void);
 extern uint32_t __get_MIMPID(void);
 extern uint32_t __get_MHARTID(void);
 extern uint32_t __get_SP(void);
 
+#ifdef __cplusplus
+}
+#endif
 
 #endif
 
diff --git a/vendor/ch32v307/debug/debug.c b/vendor/ch32v307/debug/debug.c
index f7c96d6..1d40423 100644
--- a/vendor/ch32v307/debug/debug.c
+++ b/vendor/ch32v307/debug/debug.c
@@ -4,12 +4,77 @@
 * Version            : V1.0.0
 * Date               : 2021/06/06
 * Description        : This file contains all the functions prototypes for UART
-*                      Printf.
+*                      Printf , Delay functions.
 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
 * SPDX-License-Identifier: Apache-2.0
 *******************************************************************************/
 #include "debug.h"
 
+static uint8_t  p_us = 0;
+static uint16_t p_ms = 0;
+
+/*********************************************************************
+ * @fn      Delay_Init
+ *
+ * @brief   Initializes Delay Funcation.
+ *
+ * @return  none
+ */
+void Delay_Init(void)
+{
+    p_us = SystemCoreClock / 8000000;
+    p_ms = (uint16_t)p_us * 1000;
+}
+
+/*********************************************************************
+ * @fn      Delay_Us
+ *
+ * @brief   Microsecond Delay Time.
+ *
+ * @param   n - Microsecond number.
+ *
+ * @return  None
+ */
+void Delay_Us(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->SR &= ~(1 << 0);
+    i = (uint32_t)n * p_us;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1 << 4);
+    SysTick->CTLR |= (1 << 5) | (1 << 0);
+
+    while((SysTick->SR & (1 << 0)) != (1 << 0))
+        ;
+    SysTick->CTLR &= ~(1 << 0);
+}
+
+/*********************************************************************
+ * @fn      Delay_Ms
+ *
+ * @brief   Millisecond Delay Time.
+ *
+ * @param   n - Millisecond number.
+ *
+ * @return  None
+ */
+void Delay_Ms(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->SR &= ~(1 << 0);
+    i = (uint32_t)n * p_ms;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1 << 4);
+    SysTick->CTLR |= (1 << 5) | (1 << 0);
+
+    while((SysTick->SR & (1 << 0)) != (1 << 0))
+        ;
+    SysTick->CTLR &= ~(1 << 0);
+}
 
 /*********************************************************************
  * @fn      USART_Printf_Init
@@ -44,17 +109,12 @@ void USART_Printf_Init(uint32_t baudrate)
 
 #elif(DEBUG == DEBUG_UART3)
     RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
 
-    /* Remap */
-    GPIO_PinRemapConfig(GPIO_FullRemap_USART3, ENABLE);
-
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-    GPIO_Init(GPIOD, &GPIO_InitStructure);
-
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
 
 #endif
 
@@ -111,4 +171,26 @@ __attribute__((used)) int _write(int fd, char *buf, int size)
     return size;
 }
 
+/*********************************************************************
+ * @fn      _sbrk
+ *
+ * @brief   Change the spatial position of data segment.
+ *
+ * @return  size: Data length
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+    extern char _end[];
+    extern char _heap_end[];
+    static char *curbrk = _end;
+
+    if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+    return NULL - 1;
+
+    curbrk += incr;
+    return curbrk - incr;
+}
+
+void _fini(){}
+void _init(){}
 
diff --git a/vendor/ch32v307/debug/debug.h b/vendor/ch32v307/debug/debug.h
index d67688b..6c9751d 100644
--- a/vendor/ch32v307/debug/debug.h
+++ b/vendor/ch32v307/debug/debug.h
@@ -4,13 +4,17 @@
 * Version            : V1.0.0
 * Date               : 2021/06/06
 * Description        : This file contains all the functions prototypes for UART
-*                      Printf.
+*                      Printf , Delay functions.
 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
 * SPDX-License-Identifier: Apache-2.0
 *******************************************************************************/
 #ifndef __DEBUG_H
 #define __DEBUG_H
 
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
 #include "stdio.h"
 #include "ch32v30x.h"
 
@@ -26,8 +30,16 @@
 //#define DEBUG   DEBUG_UART3
 #endif
 
+
+void Delay_Init(void);
+void Delay_Us (uint32_t n);
+void Delay_Ms (uint32_t n);
 void USART_Printf_Init(uint32_t baudrate);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif 
 
 
diff --git a/vendor/ch32v307/ld/link.ld b/vendor/ch32v307/ld/link.ld
index 9b9dc08..f8d6023 100644
--- a/vendor/ch32v307/ld/link.ld
+++ b/vendor/ch32v307/ld/link.ld
@@ -1,12 +1,28 @@
 ENTRY( _start )
 
-__stack_size = 4096;
+__stack_size = 2048;
 
 PROVIDE( _stack_size = __stack_size );
 
 
 MEMORY
 {
+/* CH32V30x_D8C - CH32V305RB-CH32V305FB
+   CH32V30x_D8 - CH32V303CB-CH32V303RB
+*/
+/*
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+*/
+    
+/* CH32V30x_D8C - CH32V307VC-CH32V307WC-CH32V307RC
+   CH32V30x_D8 - CH32V303VC-CH32V303RC
+   FLASH + RAM supports the following configuration
+   FLASH-192K + RAM-128K
+   FLASH-224K + RAM-96K
+   FLASH-256K + RAM-64K  
+   FLASH-288K + RAM-32K  
+*/
 	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K
 	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
 }
@@ -37,8 +53,6 @@ SECTIONS
 		*(.text.*)
 		*(.rodata)
 		*(.rodata*)
-		*(.glue_7)
-		*(.glue_7t)
 		*(.gnu.linkonce.t.*)
 		. = ALIGN(4);
 	} >FLASH AT>FLASH 
@@ -167,3 +181,4 @@ SECTIONS
 
 
 
+
diff --git a/vendor/ch32v307/peripheral/inc/ch32v30x.h b/vendor/ch32v307/peripheral/inc/ch32v30x.h
index 1dfeb57..c5accc4 100644
--- a/vendor/ch32v307/peripheral/inc/ch32v30x.h
+++ b/vendor/ch32v307/peripheral/inc/ch32v30x.h
@@ -14,8 +14,11 @@
  extern "C" {
 #endif 
 
-//#define CH32V30x_D8              /* CH32V303 */
-#define CH32V30x_D8C             /* CH32V307-CH32V305 */
+#if !defined(CH32V30x_D8) && !defined(CH32V30x_D8C)
+//#define CH32V30x_D8              /* CH32V303x */
+#define CH32V30x_D8C             /* CH32V307x-CH32V305x */
+
+#endif
   
 #define __MPU_PRESENT             0 /* Other CH32 devices does not provide an MPU */
 #define __Vendor_SysTickConfig    0 /* Set to 1 if different SysTick Config is used */	 
@@ -121,9 +124,8 @@ typedef enum IRQn
   DMA2_Channel10_IRQn         = 102,     /* DMA2 Channel 10 global Interrupt                     */
   DMA2_Channel11_IRQn         = 103,     /* DMA2 Channel 11 global Interrupt                     */
 
-#endif
-
-#ifdef CH32V30x_D8C
+#elif defined  (CH32V30x_D8C)
+  USBWakeUp_IRQn              = 58,      /* USB Device WakeUp from suspend through EXTI Line Interrupt */
   TIM8_BRK_IRQn               = 59,      /* TIM8 Break Interrupt                                 */
   TIM8_UP_IRQn                = 60,      /* TIM8 Update Interrupt                                */
   TIM8_TRG_COM_IRQn           = 61,      /* TIM8 Trigger and Commutation Interrupt               */
@@ -615,7 +617,9 @@ typedef struct
   __IO uint16_t I2SCFGR;
   uint16_t  RESERVED7;
   __IO uint16_t I2SPR;
-  uint16_t  RESERVED8;  
+  uint16_t  RESERVED8;
+  __IO uint16_t HSCR;
+  uint16_t  RESERVED9;
 } SPI_TypeDef;
 
 /* TIM */
diff --git a/vendor/ch32v307/peripheral/inc/ch32v30x_dbgmcu.h b/vendor/ch32v307/peripheral/inc/ch32v30x_dbgmcu.h
index f762309..38733f8 100644
--- a/vendor/ch32v307/peripheral/inc/ch32v30x_dbgmcu.h
+++ b/vendor/ch32v307/peripheral/inc/ch32v30x_dbgmcu.h
@@ -17,9 +17,31 @@
 
 #include "ch32v30x.h"
 
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00000400)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00000800)
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00002000)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00004000)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00008000)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00010000)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00020000)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00040000)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00080000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x00100000)
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x00200000)
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x00400000)
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x00800000)
 
 uint32_t DBGMCU_GetREVID(void);
 uint32_t DBGMCU_GetDEVID(void);
+uint32_t __get_DEBUG_CR(void);
+void __set_DEBUG_CR(uint32_t value);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
 
 #ifdef __cplusplus
 }
diff --git a/vendor/ch32v307/peripheral/inc/ch32v30x_eth.h b/vendor/ch32v307/peripheral/inc/ch32v30x_eth.h
index e67a2fc..6ee7684 100644
--- a/vendor/ch32v307/peripheral/inc/ch32v30x_eth.h
+++ b/vendor/ch32v307/peripheral/inc/ch32v30x_eth.h
@@ -186,7 +186,7 @@ typedef struct {
 #define _eth_delay_    ETH_Delay       /* Default _eth_delay_ function with less precise timing */
 
 /* definition for Ethernet frame */
-#define ETH_MAX_PACKET_SIZE    1520    /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_MAX_PACKET_SIZE    1536    /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
 #define ETH_HEADER               14    /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
 #define ETH_CRC                   4    /* Ethernet CRC */
 #define ETH_EXTRA                 2    /* Extra bytes in some cases */
@@ -198,7 +198,7 @@ typedef struct {
 /* ETH DMA structure definition */
 typedef struct
 {
-  uint32_t   Status;                /* Status */
+  uint32_t   volatile Status;       /* Status */
   uint32_t   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
   uint32_t   Buffer1Addr;           /* Buffer1 address pointer */
   uint32_t   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
@@ -317,10 +317,15 @@ typedef struct
 #define PHY_ConfigDelay                 ((uint32_t)0x00FFFFFF)
 
 /* PHY basic register */
-#define PHY_BCR                          0          /*PHY tranceiver Basic Control Register */
-#define PHY_BSR                          1          /*PHY tranceiver Basic Status Register */
+#define PHY_BCR                          0x0           /*PHY transceiver Basic Control Register */
+#define PHY_BSR                          0x01          /*PHY transceiver Basic Status Register*/
+#define PHY_ANAR                         0x04          /* Auto-Negotiation Advertisement Register */
+#define PHY_ANLPAR                       0x05          /* Auto-Negotiation Link Partner Base  Page Ability Register*/
+#define PHY_ANER                         0x06          /* Auto-Negotiation Expansion Register */
 #define PHY_BMCR                         PHY_BCR
 #define PHY_BMSR                         PHY_BSR
+#define PHY_STATUS                       0x10
+#define PHY_MDIX                         0x1E
 
 /* Bit or field definition for PHY basic control register */
 #define PHY_Reset                       ((uint16_t)0x8000)      /* PHY Reset */
diff --git a/vendor/ch32v307/peripheral/inc/ch32v30x_flash.h b/vendor/ch32v307/peripheral/inc/ch32v30x_flash.h
index 37c0e34..3c431c6 100644
--- a/vendor/ch32v307/peripheral/inc/ch32v30x_flash.h
+++ b/vendor/ch32v307/peripheral/inc/ch32v30x_flash.h
@@ -85,18 +85,16 @@ typedef enum
 /* FLASH_Flags */	
 #define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /* FLASH Busy flag */
 #define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /* FLASH End of Operation flag */
-#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /* FLASH Program error flag */
 #define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /* FLASH Write protected error flag */
 #define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /* FLASH Option Byte error flag */
 
 #define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /* FLASH BANK1 Busy flag*/
 #define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /* FLASH BANK1 End of Operation flag */
-#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /* FLASH BANK1 Program error flag */
 #define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /* FLASH BANK1 Write protected error flag */
 
-/* FLASH_Enhance_CLK */
-#define FLASH_Enhance_SYSTEM_HALF      ((uint32_t)0x00000000)   /* FLASH Enhance Clock = SYSTEM */
-#define FLASH_Enhance_SYSTEM           ((uint32_t)0x02000000)   /* Enhance_CLK = SYSTEM/2 */ 
+/* FLASH_Access_CLK */
+#define FLASH_Access_SYSTEM_HALF      ((uint32_t)0x00000000)   /* FLASH Access Clock = SYSTEM/2 */
+#define FLASH_Access_SYSTEM           ((uint32_t)0x02000000)   /* FLASH Access Clock = SYSTEM */
  
  
 /*Functions used for all devices*/
@@ -125,7 +123,8 @@ void FLASH_ErasePage_Fast(uint32_t Page_Address);
 void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
 void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address);
 void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf);
-void FLASH_Enhance_Mode(uint32_t FLASH_Enhance_CLK, FunctionalState NewState);
+void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
+void FLASH_Enhance_Mode(FunctionalState NewState);
 
 /* New function used for all devices */
 void FLASH_UnlockBank1(void);
diff --git a/vendor/ch32v307/peripheral/inc/ch32v30x_opa.h b/vendor/ch32v307/peripheral/inc/ch32v30x_opa.h
index 4fd5f01..bf747b8 100644
--- a/vendor/ch32v307/peripheral/inc/ch32v30x_opa.h
+++ b/vendor/ch32v307/peripheral/inc/ch32v30x_opa.h
@@ -45,11 +45,11 @@ typedef enum
    CHN1
 }OPA_NSEL_TypeDef;
 
-/* OPA Mode enumeration */
+/* OPA out channel enumeration */
 typedef enum
 {
-   OUT_IO_ADC=0,
-   OUT_IO
+   OUT_IO_OUT0=0,
+   OUT_IO_OUT1
 }OPA_Mode_TypeDef;
 
 /* OPA Init Structure definition */
diff --git a/vendor/ch32v307/peripheral/inc/ch32v30x_pwr.h b/vendor/ch32v307/peripheral/inc/ch32v30x_pwr.h
index 3fc9329..1f1985b 100644
--- a/vendor/ch32v307/peripheral/inc/ch32v30x_pwr.h
+++ b/vendor/ch32v307/peripheral/inc/ch32v30x_pwr.h
@@ -54,7 +54,7 @@ void PWR_EnterSTANDBYMode_RAM(void);
 void PWR_EnterSTANDBYMode_RAM_LV(void);
 void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
 void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
-
+void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
 
 #ifdef __cplusplus
 }
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_adc.c b/vendor/ch32v307/peripheral/src/ch32v30x_adc.c
index 8ea6201..64e6a68 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_adc.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_adc.c
@@ -1102,7 +1102,7 @@ s32 TempSensor_Volt_To_Temper(s32 Value)
     Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF);
     Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF);
 
-    Temper = Refer_Temper + ((Value - Refer_Volt) * 10 + (k >> 1)) / k;
+    Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k;
 
     return Temper;
 }
@@ -1157,13 +1157,13 @@ int16_t Get_CalibrationValue(ADC_TypeDef *ADCx)
 
     for(i = 0; i < 10; i++)
     {
-        for(j = 0; j < 10; j++)
+        for(j = 0; j < 9; j++)
         {
             if(buf[j] > buf[j + 1])
             {
                 t = buf[j];
                 buf[j] = buf[j + 1];
-                buf[j] = t;
+                buf[j + 1] = t;
             }
         }
     }
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_crc.c b/vendor/ch32v307/peripheral/src/ch32v30x_crc.c
index 328703e..3ae9236 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_crc.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_crc.c
@@ -68,7 +68,7 @@ uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
  */
 uint32_t CRC_GetCRC(void)
 {
-    return (CRC->IDATAR);
+    return (CRC->DATAR);
 }
 
 /*********************************************************************
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_dbgmcu.c b/vendor/ch32v307/peripheral/src/ch32v30x_dbgmcu.c
index 87b286f..2d3d0ed 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_dbgmcu.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_dbgmcu.c
@@ -9,7 +9,7 @@
 ****************************************************************************************/
 #include "ch32v30x_dbgmcu.h"
 
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+#define IDCODE_DEVID_MASK    ((uint32_t)0x0000FFFF)
 
 /*********************************************************************
  * @fn      DBGMCU_GetREVID
@@ -34,3 +34,68 @@ uint32_t DBGMCU_GetDEVID(void)
 {
     return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
 }
+
+/*********************************************************************
+ * @fn      __get_DEBUG_CR
+ *
+ * @brief   Return the DEBUGE Control Register
+ *
+ * @return  DEBUGE Control value
+ */
+uint32_t __get_DEBUG_CR(void)
+{
+    uint32_t result;
+
+    __asm volatile("csrr %0,""0x7C0" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_DEBUG_CR
+ *
+ * @brief   Set the DEBUGE Control Register
+ *
+ * @param   value  - set DEBUGE Control value
+ *
+ * @return  none
+ */
+void __set_DEBUG_CR(uint32_t value)
+{
+    __asm volatile("csrw 0x7C0, %0" : : "r"(value));
+}
+
+
+/*********************************************************************
+ * @fn      DBGMCU_Config
+ *
+ * @brief   Configures the specified peripheral and low power mode behavior
+ *        when the MCU under Debug mode.
+ *
+ * @param   DBGMCU_Periph - specifies the peripheral and low power mode.
+ *            DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
+ *            DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
+ *            DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
+ *            DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+    uint32_t val;
+
+    if(NewState != DISABLE)
+    {
+        __set_DEBUG_CR(DBGMCU_Periph);
+    }
+    else
+    {
+        val = __get_DEBUG_CR();
+        val &= ~(uint32_t)DBGMCU_Periph;
+        __set_DEBUG_CR(val);
+    }
+
+}
+
+
+
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_eth.c b/vendor/ch32v307/peripheral/src/ch32v30x_eth.c
index c56a186..8a3db04 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_eth.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_eth.c
@@ -10,8 +10,6 @@
 #include "ch32v30x_eth.h"
 #include "ch32v30x_rcc.h"
 
-#include <inttypes.h>
-
 ETH_DMADESCTypeDef *DMATxDescToSet;
 ETH_DMADESCTypeDef *DMARxDescToGet;
 ETH_DMADESCTypeDef *DMAPTPTxDescToSet;
@@ -1287,7 +1285,6 @@ FlagStatus ETH_GetSoftwareResetStatus(void)
     {
         bitstatus = RESET;
     }
-    printf("ETH->DMABMR is:%08" PRIx32 "\n", ETH->DMABMR);
 
     return bitstatus;
 }
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_flash.c b/vendor/ch32v307/peripheral/src/ch32v30x_flash.c
index 8a5baa4..141bc95 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_flash.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_flash.c
@@ -11,15 +11,15 @@
 
 /* Flash Control Register bits */
 #define CR_PG_Set                  ((uint32_t)0x00000001)
-#define CR_PG_Reset                ((uint32_t)0x00001FFE)
+#define CR_PG_Reset                ((uint32_t)0xFFFFFFFE)
 #define CR_PER_Set                 ((uint32_t)0x00000002)
-#define CR_PER_Reset               ((uint32_t)0x00001FFD)
+#define CR_PER_Reset               ((uint32_t)0xFFFFFFFD)
 #define CR_MER_Set                 ((uint32_t)0x00000004)
-#define CR_MER_Reset               ((uint32_t)0x00001FFB)
+#define CR_MER_Reset               ((uint32_t)0xFFFFFFFB)
 #define CR_OPTPG_Set               ((uint32_t)0x00000010)
-#define CR_OPTPG_Reset             ((uint32_t)0x00001FEF)
+#define CR_OPTPG_Reset             ((uint32_t)0xFFFFFFEF)
 #define CR_OPTER_Set               ((uint32_t)0x00000020)
-#define CR_OPTER_Reset             ((uint32_t)0x00001FDF)
+#define CR_OPTER_Reset             ((uint32_t)0xFFFFFFDF)
 #define CR_STRT_Set                ((uint32_t)0x00000040)
 #define CR_LOCK_Set                ((uint32_t)0x00000080)
 #define CR_FAST_LOCK_Set           ((uint32_t)0x00008000)
@@ -628,7 +628,6 @@ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
  *
  * @param   FLASH_FLAG - specifies the FLASH flag to check.
  *            FLASH_FLAG_BSY - FLASH Busy flag
- *            FLASH_FLAG_PGERR - FLASH Program error flag
  *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
  *            FLASH_FLAG_EOP - FLASH End of Operation flag
  *            FLASH_FLAG_OPTERR - FLASH Option Byte error flag
@@ -670,7 +669,6 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
  * @brief   Clears the FLASH's pending flags.
  *
  * @param   FLASH_FLAG - specifies the FLASH flags to clear.
- *            FLASH_FLAG_PGERR - FLASH Program error flag
  *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
  *            FLASH_FLAG_EOP - FLASH End of Operation flag
  *
@@ -699,20 +697,13 @@ FLASH_Status FLASH_GetStatus(void)
     }
     else
     {
-        if((FLASH->STATR & FLASH_FLAG_PGERR) != 0)
+        if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0)
         {
-            flashstatus = FLASH_ERROR_PG;
+            flashstatus = FLASH_ERROR_WRP;
         }
         else
         {
-            if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0)
-            {
-                flashstatus = FLASH_ERROR_WRP;
-            }
-            else
-            {
-                flashstatus = FLASH_COMPLETE;
-            }
+            flashstatus = FLASH_COMPLETE;
         }
     }
     return flashstatus;
@@ -736,20 +727,13 @@ FLASH_Status FLASH_GetBank1Status(void)
     }
     else
     {
-        if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0)
+        if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0)
         {
-            flashstatus = FLASH_ERROR_PG;
+            flashstatus = FLASH_ERROR_WRP;
         }
         else
         {
-            if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0)
-            {
-                flashstatus = FLASH_ERROR_WRP;
-            }
-            else
-            {
-                flashstatus = FLASH_COMPLETE;
-            }
+            flashstatus = FLASH_COMPLETE;
         }
     }
     return flashstatus;
@@ -939,23 +923,35 @@ void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf)
     FLASH->CTLR &= ~CR_PAGE_PG;
 }
 
+/*********************************************************************
+ * @fn      FLASH_Access_Clock_Cfg
+ *
+ * @brief   Config FLASH Access Clock(Need to unlock )
+ *
+ * @param   FLASH_Access_CLK -
+ *            FLASH_Access_SYSTEM_HALF - System clock/2
+ *            FLASH_Access_SYSTEM - System clock
+ *
+ * @return  none
+ */
+void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK)
+{
+    FLASH->CTLR &= ~(1 << 25);
+    FLASH->CTLR |= FLASH_Access_CLK;
+}
+
 /*********************************************************************
  * @fn      FLASH_Enhance_Mode
  *
  * @brief   Read FLASH Enhance Mode
  *
- * @param   FLASH_Enhance_CLK -
- *            FLASH_Enhance_SYSTEM_HALF - System clock/2
- *            FLASH_Enhance_SYSTEM - System clock
+ * @param
  *          Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
  *
  * @return  none
  */
-void FLASH_Enhance_Mode(uint32_t FLASH_Enhance_CLK, FunctionalState NewState)
+void FLASH_Enhance_Mode(FunctionalState NewState)
 {
-    FLASH->CTLR &= ~(1 << 25);
-    FLASH->CTLR |= FLASH_Enhance_CLK;
-
     if(NewState)
     {
         FLASH->CTLR |= (1 << 24);
@@ -966,3 +962,4 @@ void FLASH_Enhance_Mode(uint32_t FLASH_Enhance_CLK, FunctionalState NewState)
         FLASH->CTLR |= (1 << 22);
     }
 }
+
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_i2c.c b/vendor/ch32v307/peripheral/src/ch32v30x_i2c.c
index 17da0e4..a472cca 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_i2c.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_i2c.c
@@ -770,7 +770,7 @@ ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
 {
     uint32_t    lastevent = 0;
     uint32_t    flag1 = 0, flag2 = 0;
-    ErrorStatus status = ERROR;
+    ErrorStatus status = NoREADY;
 
     flag1 = I2Cx->STAR1;
     flag2 = I2Cx->STAR2;
@@ -780,11 +780,11 @@ ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
 
     if((lastevent & I2C_EVENT) == I2C_EVENT)
     {
-        status = SUCCESS;
+        status = READY;
     }
     else
     {
-        status = ERROR;
+        status = NoREADY;
     }
 
     return status;
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_opa.c b/vendor/ch32v307/peripheral/src/ch32v30x_opa.c
index f157794..e1dab67 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_opa.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_opa.c
@@ -55,7 +55,7 @@ void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
  */
 void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
 {
-    OPA_InitStruct->Mode = OUT_IO;
+    OPA_InitStruct->Mode = OUT_IO_OUT1;
     OPA_InitStruct->PSEL = CHP0;
     OPA_InitStruct->NSEL = CHN0;
     OPA_InitStruct->OPA_NUM = OPA1;
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_pwr.c b/vendor/ch32v307/peripheral/src/ch32v30x_pwr.c
index a36907d..1cc4c60 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_pwr.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_pwr.c
@@ -319,3 +319,45 @@ void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
 
     __WFI();
 }
+
+
+/*********************************************************************
+ * @fn      PWR_EnterSTOPMode_RAM_LV
+ *
+ * @brief   Enters STOP mode with RAM data retention function and LV mode on.
+ *
+ * @param   PWR_Regulator - specifies the regulator state in STOP mode.
+ *            PWR_Regulator_ON - STOP mode with regulator ON
+ *            PWR_Regulator_LowPower - STOP mode with regulator in low power mode
+ *          PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
+ *            PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
+ *            PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
+ *
+ * @return  none
+ */
+void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_DS_MASK;
+    tmpreg |= PWR_Regulator;
+
+    //2K+30K in standby power.
+    tmpreg |= (0x1 << 16) | (0x1 << 17);
+    //2K+30K in standby LV .
+    tmpreg |= (0x1 << 20);
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+    {
+        __WFI();
+    }
+    else
+    {
+        __WFE();
+    }
+
+    NVIC->SCTLR &= ~(1 << 2);
+}
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_rcc.c b/vendor/ch32v307/peripheral/src/ch32v30x_rcc.c
index 63ce4e3..f257b8c 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_rcc.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_rcc.c
@@ -143,7 +143,7 @@ ErrorStatus RCC_WaitForHSEStartUp(void)
 {
     __IO uint32_t StartUpCounter = 0;
 
-    ErrorStatus status = ERROR;
+    ErrorStatus status = NoREADY;
     FlagStatus  HSEStatus = RESET;
 
     do
@@ -154,11 +154,11 @@ ErrorStatus RCC_WaitForHSEStartUp(void)
 
     if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
     {
-        status = SUCCESS;
+        status = READY;
     }
     else
     {
-        status = ERROR;
+        status = NoREADY;
     }
 
     return (status);
@@ -391,11 +391,10 @@ void RCC_PCLK1Config(uint32_t RCC_HCLK)
  *
  * @param   RCC_HCLK - defines the APB2 clock divider. This clock is derived from
  *        the AHB clock (HCLK).
- *            RCC_HCLK_Div1 - APB1 clock = HCLK.
- *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
- *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
- *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
- *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *            RCC_PCLK2_Div2 - APB2 clock = HCLK.
+ *            RCC_PCLK2_Div4 - APB2 clock = HCLK/2.
+ *            RCC_PCLK2_Div6 - APB2 clock = HCLK/4.
+ *            RCC_PCLK2_Div8 - APB2 clock = HCLK/8.
  *
  * @return  none
  */
@@ -565,7 +564,13 @@ void RCC_RTCCLKCmd(FunctionalState NewState)
  */
 void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
 {
-    uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0, Pll_6_5 = 0;
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+    uint8_t Pll_6_5 = 0;
+
+#ifdef CH32V30x_D8C
+    uint8_t Pll2mull = 0;
+
+#endif
 
     tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
 
@@ -618,6 +623,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
             }
             else
             {
+#ifdef CH32V30x_D8
                 if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
                 {
                     RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
@@ -626,6 +632,26 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
                 {
                     RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
                 }
+#else
+                if(RCC->CFGR2 & (1<<16)){ /* PLL2 */
+                    RCC_Clocks->SYSCLK_Frequency = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1);  /* PREDIV2 */
+
+                    Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8);
+
+                    if(Pll2mull == 0) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency * 5)>>1;
+                    else if(Pll2mull == 1) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency * 25)>>1;
+                    else if(Pll2mull == 15) RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * 20;
+                    else  RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * (Pll2mull + 2);
+
+                    RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency/((RCC->CFGR2 & 0xF) + 1);  /* PREDIV1 */
+                }
+                else{/* HSE */
+                    RCC_Clocks->SYSCLK_Frequency = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1);  /* PREDIV1 */
+                }
+
+                RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * pllmull;
+
+#endif
             }
 
             if(Pll_6_5 == 1)
diff --git a/vendor/ch32v307/peripheral/src/ch32v30x_usart.c b/vendor/ch32v307/peripheral/src/ch32v30x_usart.c
index b7749ce..dc3093b 100644
--- a/vendor/ch32v307/peripheral/src/ch32v30x_usart.c
+++ b/vendor/ch32v307/peripheral/src/ch32v30x_usart.c
@@ -278,7 +278,6 @@ void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
  *
  * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
  *          USART_IT - specifies the USART interrupt sources to be enabled or disabled.
- *            USART_IT_CTS - CTS change interrupt.
  *            USART_IT_LBD - LIN Break detection interrupt.
  *            USART_IT_TXE - Transmit Data Register empty interrupt.
  *            USART_IT_TC - Transmission complete interrupt.
@@ -295,10 +294,6 @@ void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState Ne
     uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
     uint32_t usartxbase = 0x00;
 
-    if(USART_IT == USART_IT_CTS)
-    {
-    }
-
     usartxbase = (uint32_t)USARTx;
     usartreg = (((uint8_t)USART_IT) >> 0x05);
     itpos = USART_IT & IT_Mask;
@@ -680,7 +675,6 @@ void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
  *
  * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
  *          USART_FLAG - specifies the flag to check.
- *            USART_FLAG_CTS - CTS Change flag.
  *            USART_FLAG_LBD - LIN Break detection flag.
  *            USART_FLAG_TXE - Transmit data register empty flag.
  *            USART_FLAG_TC - Transmission Complete flag.
@@ -697,10 +691,6 @@ FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
 {
     FlagStatus bitstatus = RESET;
 
-    if(USART_FLAG == USART_FLAG_CTS)
-    {
-    }
-
     if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
     {
         bitstatus = SET;
@@ -719,7 +709,6 @@ FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
  *
  * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
  *          USART_FLAG - specifies the flag to clear.
- *            USART_FLAG_CTS - CTS Change flag.
  *            USART_FLAG_LBD - LIN Break detection flag.
  *            USART_FLAG_TC - Transmission Complete flag.
  *            USART_FLAG_RXNE - Receive data register not empty flag.
@@ -728,9 +717,6 @@ FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
  */
 void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
 {
-    if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
-    {
-    }
 
     USARTx->STATR = (uint16_t)~USART_FLAG;
 }
@@ -742,7 +728,6 @@ void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
  *
  * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
  *          USART_IT - specifies the USART interrupt source to check.
- *            USART_IT_CTS - CTS change interrupt.
  *            USART_IT_LBD - LIN Break detection interrupt.
  *            USART_IT_TXE - Tansmit Data Register empty interrupt.
  *            USART_IT_TC - Transmission complete interrupt.
@@ -761,10 +746,6 @@ ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
     uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
     ITStatus bitstatus = RESET;
 
-    if(USART_IT == USART_IT_CTS)
-    {
-    }
-
     usartreg = (((uint8_t)USART_IT) >> 0x05);
     itmask = USART_IT & IT_Mask;
     itmask = (uint32_t)0x01 << itmask;
@@ -805,7 +786,6 @@ ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
  *
  * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
  *          USART_IT - specifies the interrupt pending bit to clear.
- *            USART_IT_CTS - CTS change interrupt.
  *            USART_IT_LBD - LIN Break detection interrupt.
  *            USART_IT_TC - Transmission complete interrupt.
  *            USART_IT_RXNE - Receive Data register not empty interrupt.
@@ -816,10 +796,6 @@ void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
 {
     uint16_t bitpos = 0x00, itmask = 0x00;
 
-    if(USART_IT == USART_IT_CTS)
-    {
-    }
-
     bitpos = USART_IT >> 0x08;
     itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
     USARTx->STATR = (uint16_t)~itmask;
diff --git a/vendor/ch32v307/startup/startup_ch32v30x_D8C.S b/vendor/ch32v307/startup/startup_ch32v30x_D8C.S
index 5798014..9fb4208 100644
--- a/vendor/ch32v307/startup/startup_ch32v30x_D8C.S
+++ b/vendor/ch32v307/startup/startup_ch32v30x_D8C.S
@@ -3,7 +3,7 @@
 * Author             : WCH
 * Version            : V1.0.0
 * Date               : 2021/06/06
-* Description        : CH32V307-CH32V305 vector table for eclipse toolchain.
+* Description        : CH32V307x-CH32V305x vector table for eclipse toolchain.
 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
 * SPDX-License-Identifier: Apache-2.0
 *******************************************************************************/
@@ -136,7 +136,7 @@ _vector_base:
     .word   DMA2_Channel10_IRQHandler  /* DMA2 Channel 10 */
     .word   DMA2_Channel11_IRQHandler  /* DMA2 Channel 11 */
 
-    //.option rvc;
+    .option rvc;
 
     .section    .text.vector_handler, "ax", @progbits
     .weak   NMI_Handler                /* NMI */
@@ -334,7 +334,7 @@ DMA2_Channel11_IRQHandler:  1:  j 1b
 
 	.section	.text.handle_reset,"ax",@progbits
 	.weak	handle_reset
-	.align	4
+	.align	1
 handle_reset:
 .option push 
 .option	norelax 
@@ -368,11 +368,10 @@ handle_reset:
     csrw 0xbc0, t0
 
     /* Enable nested and hardware stack */
-    /* HWSTKOVEN -  1 = interrupt enabled after hardware stack overflow */
-    /* PMTCFG    - 11 = 8 nested levels, 3 preemption bits */
+    /* PMTCFG    - 10 = 4 levels of nesting, with 2 preemption bits */
     /* INESTEN   -  1 = interrupt nesting enabled */
     /* HWSTKEN   -  1 = hardware stack enabled */
-    li t0, 0x1f /* HWSTKOVEN[4], PMTCFG[3:2], INESTEN[1], HWSTKEN[0] */
+    li t0, 0x0b /* PMTCFG[3:2], INESTEN[1], HWSTKEN[0] */
     csrw 0x804, t0 /* INTSYSCR (CSR) */
 
     /* Enable floating point and interrupt */
@@ -383,6 +382,10 @@ handle_reset:
     ori t0, t0, 3           
 	csrw mtvec, t0
 
+    la a0,__libc_fini_array
+    call atexit
+    call __libc_init_array
+
     jal  SystemInit
 	la t0, main
 	csrw mepc, t0