From 6506c1ad9bdc77bf1e6ed02fe298f771f05208cb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E6=9D=8E=E6=88=90=E5=88=9A?= <lichenggang@uniontech.com>
Date: Fri, 15 Mar 2024 19:25:22 +0800
Subject: [PATCH] Fix compilation errors under riscv64 architecture

---
 src/co/context/arch.h | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/co/context/arch.h b/src/co/context/arch.h
index 0b36920c..6b1f44d5 100644
--- a/src/co/context/arch.h
+++ b/src/co/context/arch.h
@@ -54,15 +54,13 @@
   #define ARCH_MIPS
 
 #elif defined(loongarch) || \
-      defined(_loongarch) || \
-      defined(_loongarch64) || \
+      defined(__loongarch64) || \
       defined(__loongarch__)
   #define ARCH_LOONGARCH
 
 #elif defined(riscv) || \
-      defined(_riscv) || \
-      defined(_riscv64) || \
-      defined(__riscv__)
+      defined(__riscv) || \
+      defined(__riscv_xlen)
   #define ARCH_RISCV
 
 
@@ -129,7 +127,7 @@
     defined(__ppc64__) || \
     defined(__powerpc64__) || \
     defined(__loongarch64) || \
-    defined(__riscv64) || \
+    defined(__riscv_xlen) || \
     defined(_M_X64) || \
     defined(_M_AMD64) || \
     defined(_M_IA64) || \