Tool options and defines

To run ICSC tool for the custom project it needs to create CMakeList.txt file. SystemVeriog code generation is done with svc_target function. svc_target is CMake function defined in $ICSC_HOME/lib64/cmake/SVC/svc_target.cmake.

ICSC has several options, which can be specified as svc_target parameters:

• ELAB_TOP – design top module name, it needs to be specified if top module is instantiated outside of sc_main() or if there are more than one modules in sc_main();
• MODULE_PREFIX – module prefix string, no prefix if not specified, prefix applied for every module excluding Verilog intrinsic (module with __SC_TOOL_VERILOG_MOD__) and memory modules (modules with __SC_TOOL_MEMORY_NAME__);
• REPLACE_CONST_VALUE – replace constant with its evaluated value if possible, by default constant variable is used;
• INIT_LOCAL_VARS – initialize non-initialized process local variables with zero to avoid latches, that related to CPP data types only, SC data types always initialized with 0;
• NO_SVA_GENERATE – do not generate SVA from immediate and temporal SystemC assertions, normally SVA are generated;
• NO_REMOVE_EXTRA_CODE – do not remove unused variable and unused code in generated SV, normally such code is removed to improve readability.

ICSC tool provides __SC_TOOL__ define for input SystemC project translation. This define used in temporal assertions and other ICSC library modules to have different behavior for simulation and SV generation. __SC_TOOL__ can also be used in project code to hide pieces of code which is not targeted for translation to SystemVerilog.

To completely disable SystemC temporal assertion macro SCT_ASSERT_OFF can be defined. That allows to hide all assertion specific code to meet SystemC synthesizable standard requirements. SCT_ASSERT_OFF is required if the SystemC design is passed through a tool which includes its own (not patched) SystemC library.