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Tool options and defines

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Mikhail Moiseev edited this page Oct 8, 2021 · 8 revisions

To run ICSC tool it needs to create general CMakeList.txt file for the project. Veriog code generation is done with svc_target function. svc_target is CMake function defned in $ICSC_HOME/lib64/cmake/SVC/svc_target.cmake.

There is simple CMakeList.txt example for target my_project. The design contains dut.cpp and fifo.cpp source files and headers placed in include and include/fifo folders.

add_executable(my_project dut.cpp fifo.cpp)
set(MY_INCLUDE_FOLDERS include include/fifo)
target_include_directories(my_project PUBLIC MY_INCLUDE_FOLDERS)

set(MY_COMPILE_DEFINES ...)             # User specified defines
set(MY_COMPILE_OPTION ...)              # User specified options
set(MY_PROJECT_LIBRARIES ...)           # User specified libraries w/o source code

target_compile_definitions(my_project PUBLIC MY_COMPILE_DEFINES)
target_compile_options(my_project PUBLIC MY_COMPILE_OPTIONS)
# Do not add SystemC library (it added in svc_target)
target_link_libraries(my_project PUBLIC MY_PROJECT_LIBRARIES)

svc_target(my_project ELAB_TOP tb.top)  # Top module instance name blocks

ICSC has several options, which can be specified as svc_target parameters:

  • ELAB_TOP – design top module name, it needs to be specified if top module is instantiated outside of sc_main() or if there are more than one modules in sc_main();
  • MODULE_PREFIX – module prefix string, no prefix if not specified, prefix applied for every module excluding SV intrinsic (module with __SC_TOOL_VERILOG_MOD__) and memory modules (modules with __SC_TOOL_MEMORY_NAME__);
  • REPLACE_CONST_VALUE – replace constant with its evaluated value if possible, by default constant variable is used;
  • INIT_LOCAL_VARS – initialize non-initialized process local variables with zero to avoid latches, that related to CPP data types only, SC data types always initialized with 0;
  • INIT_RESET_LOCAL_VARS – initialize non-initialized clocked thread local variables declared in reset section with zero, that related to CPP data types only, SC data types always initialized with 0;
  • PORT_MAP_GENERATE - generate port map file and top module wrapper with flatten port arrays, port map file used for SC/SV mixed language simulation, top module wrapper used for logic synthesis tools which do not support unpacked port array in top module interface;
  • NO_SVA_GENERATE – do not generate SVA from immediate and temporal SystemC assertions, normally SVA are generated;
  • NO_REMOVE_EXTRA_CODE – do not remove unused variable and unused code in generated SV, normally such code is removed to improve readability.

ICSC tool provides __SC_TOOL__ define for input SystemC project translation. This define used in temporal assertions and other ICSC library modules to have different behavior for simulation and SV generation. __SC_TOOL__ can also be used in project code to hide pieces of code which is not targeted for translation to SystemVerilog.

To completely disable SystemC temporal assertion macro SCT_ASSERT_OFF can be defined. That allows to hide all assertion specific code to meet SystemC synthesizable standard requirements. SCT_ASSERT_OFF is required if the SystemC design is passed through a tool which includes its own (not patched) SystemC library.

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