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1 parent 5db1331 commit 0b77a97Copy full SHA for 0b77a97
examples/uart2wb/sw/wishbone.py
@@ -44,7 +44,7 @@ def close(self):
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if __name__ == '__main__':
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print("Test of access to CSR (control status registers) via UART2WBM module...")
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print("=======================================================================")
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- wb = wishbone("COM4")
+ wb = wishbone("COM1")
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print("\nREAD from 0x0:")
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rd = wb.read(0x0)
examples/uart2wb/uart2wb_fpga_cyc1000.vhd
@@ -68,10 +68,10 @@ begin
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WB_STB => wb_stb,
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WB_WE => wb_we,
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WB_ADDR => wb_addr,
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- WB_DOUT => wb_dout,
+ WB_DOUT => wb_din,
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WB_STALL => wb_stall,
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WB_ACK => wb_ack,
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- WB_DIN => wb_din
+ WB_DIN => wb_dout
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);
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debug_reg_sel <= '1' when (wb_addr = X"0004") else '0';
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