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lines changed Original file line number Diff line number Diff line change @@ -52,3 +52,43 @@ Registers
5252 * The same 10 inputs discussed above
5353 * An additional 3 inputs specifying which register the output should be saved to
5454
55+
56+
57+ New Operation
58+ =============
59+
60+ Currently there is no way to actually load data into the system.
61+
62+ #. Add a new mode/instruction such that data can be loaded into a specific register
63+
64+ * Currently 1 bit is used to specify ALU or comparator operations
65+
66+ * These can be thought of as *modes *
67+
68+
69+ * Add an additional bit to allow for selecting between up to 4 modes
70+
71+ * 2 mode bits
72+ * 3 bits that served as selecting a specific operation
73+ * Two sets of 3 bits for specifying 2 source registers
74+ * 3 bits for a destination register
75+
76+
77+ * Update the system such that one of these 4 modes allows for loading data directly to a register
78+
79+ * The 3 destination register bits specify where the data is to be stored
80+ * 8 bits of the 9 available for the operator and 3 source registers specify the 8 bit data
81+
82+
83+ * For example, consider the below bit patterns and their meanings
84+
85+ * ``00 110 101 010 111 `` --- ``add `` on registers 5 and 2 and store in 7
86+ * ``01 110 101 010 111 `` --- ``>= `` on registers 5 and 2 and store in 7
87+ * ``10 1 10101010 111 `` --- Store ``0b10101010 `` (``170 ``) in register 7
88+
89+
90+
91+ #. Add a new forth mode such that data can be copy between registers
92+
93+ * Here, only one set of 3 bits specifying the source register is required
94+ * ``11 110 101 010 111 `` --- Copy contests of register 2 to register 7
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