From a415482cfcef692775fff3ae2834b2fecbda919e Mon Sep 17 00:00:00 2001 From: James Alexander Hughes Date: Wed, 19 Mar 2025 14:52:02 -0300 Subject: [PATCH 1/5] add new part --- .../decoding-instructions-registers.rst | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/site/labs/decoding-instructions/decoding-instructions-registers.rst b/site/labs/decoding-instructions/decoding-instructions-registers.rst index d00f23e8..6b9f17e8 100644 --- a/site/labs/decoding-instructions/decoding-instructions-registers.rst +++ b/site/labs/decoding-instructions/decoding-instructions-registers.rst @@ -52,3 +52,33 @@ Registers * The same 10 inputs discussed above * An additional 3 inputs specifying which register the output should be saved to + + +New Operation +============= + +Currently there is no way to actually load data into the system. + +#. Add a new mode/instruction such that data can be loaded into a specific register + + * Currently 1 bit is used to specify ALU or comparator operations, or *modes* + * Add an additional bit to allow for selecting between up to 4 modes + + * 2 mode bits + + * 3 bits that served as selecting a specific operation + * Two sets of 3 bits for specifying 2 source registers + * 3 bits for a destination register + + + * Design the system such that one of these 4 modes allows for loading data directly to a register + + * The 3 destination register bits specify where the data is to be stored + * 8 bits of the 9 available for the operator and 3 source registers specify the 8 bit data + + + * For example, consider the below bit patterns and their meanings + + * ``00 110 101 010 111`` --- ``add`` on registers 5 and 2 and store in 7 + * ``01 110 101 010 111`` --- ``>=`` on registers 5 and 2 and store in 7 + * ``10 1 10101010 111`` --- Store ``0b10101010`` (``170``) in register 7 From f47ea83755cabbba2a9742c63fc48e91d1b73102 Mon Sep 17 00:00:00 2001 From: James Alexander Hughes Date: Wed, 19 Mar 2025 14:55:38 -0300 Subject: [PATCH 2/5] swap instruction --- .../decoding-instructions-registers.rst | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/site/labs/decoding-instructions/decoding-instructions-registers.rst b/site/labs/decoding-instructions/decoding-instructions-registers.rst index 6b9f17e8..9d69b415 100644 --- a/site/labs/decoding-instructions/decoding-instructions-registers.rst +++ b/site/labs/decoding-instructions/decoding-instructions-registers.rst @@ -65,13 +65,12 @@ Currently there is no way to actually load data into the system. * Add an additional bit to allow for selecting between up to 4 modes * 2 mode bits - * 3 bits that served as selecting a specific operation * Two sets of 3 bits for specifying 2 source registers * 3 bits for a destination register - * Design the system such that one of these 4 modes allows for loading data directly to a register + * Update the system such that one of these 4 modes allows for loading data directly to a register * The 3 destination register bits specify where the data is to be stored * 8 bits of the 9 available for the operator and 3 source registers specify the 8 bit data @@ -82,3 +81,10 @@ Currently there is no way to actually load data into the system. * ``00 110 101 010 111`` --- ``add`` on registers 5 and 2 and store in 7 * ``01 110 101 010 111`` --- ``>=`` on registers 5 and 2 and store in 7 * ``10 1 10101010 111`` --- Store ``0b10101010`` (``170``) in register 7 + + + +#. Add a new mode such that data can be moved between registers + + * Here, only one set of 3 bits specifying the source register is required + * ``11 110 101 010 111`` --- Move contests of register 2 to register 7 \ No newline at end of file From 6229a72137b16fe79bb7d5d58eb7bea7f9b4e516 Mon Sep 17 00:00:00 2001 From: James Alexander Hughes Date: Wed, 19 Mar 2025 14:58:10 -0300 Subject: [PATCH 3/5] move "modes" --- .../decoding-instructions-registers.rst | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/site/labs/decoding-instructions/decoding-instructions-registers.rst b/site/labs/decoding-instructions/decoding-instructions-registers.rst index 9d69b415..b23fe40a 100644 --- a/site/labs/decoding-instructions/decoding-instructions-registers.rst +++ b/site/labs/decoding-instructions/decoding-instructions-registers.rst @@ -61,7 +61,11 @@ Currently there is no way to actually load data into the system. #. Add a new mode/instruction such that data can be loaded into a specific register - * Currently 1 bit is used to specify ALU or comparator operations, or *modes* + * Currently 1 bit is used to specify ALU or comparator operations + + * These can be thought of as *modes* + + * Add an additional bit to allow for selecting between up to 4 modes * 2 mode bits From 3fce2d0e4a39a9f112c3685bfef7b2ae515ba856 Mon Sep 17 00:00:00 2001 From: James Alexander Hughes Date: Wed, 19 Mar 2025 14:58:42 -0300 Subject: [PATCH 4/5] emph 4th --- .../decoding-instructions/decoding-instructions-registers.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/site/labs/decoding-instructions/decoding-instructions-registers.rst b/site/labs/decoding-instructions/decoding-instructions-registers.rst index b23fe40a..aad56699 100644 --- a/site/labs/decoding-instructions/decoding-instructions-registers.rst +++ b/site/labs/decoding-instructions/decoding-instructions-registers.rst @@ -88,7 +88,7 @@ Currently there is no way to actually load data into the system. -#. Add a new mode such that data can be moved between registers +#. Add a new forth mode such that data can be moved between registers * Here, only one set of 3 bits specifying the source register is required * ``11 110 101 010 111`` --- Move contests of register 2 to register 7 \ No newline at end of file From 0c94a75f5f0845f164967ae3ffbdec08be4995e5 Mon Sep 17 00:00:00 2001 From: James Alexander Hughes Date: Wed, 19 Mar 2025 15:12:29 -0300 Subject: [PATCH 5/5] move -> copy --- .../decoding-instructions/decoding-instructions-registers.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/site/labs/decoding-instructions/decoding-instructions-registers.rst b/site/labs/decoding-instructions/decoding-instructions-registers.rst index aad56699..94df5734 100644 --- a/site/labs/decoding-instructions/decoding-instructions-registers.rst +++ b/site/labs/decoding-instructions/decoding-instructions-registers.rst @@ -88,7 +88,7 @@ Currently there is no way to actually load data into the system. -#. Add a new forth mode such that data can be moved between registers +#. Add a new forth mode such that data can be copy between registers * Here, only one set of 3 bits specifying the source register is required - * ``11 110 101 010 111`` --- Move contests of register 2 to register 7 \ No newline at end of file + * ``11 110 101 010 111`` --- Copy contests of register 2 to register 7 \ No newline at end of file